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37 lines
557 B
Systemverilog
37 lines
557 B
Systemverilog
module CLIO_INTERPOL
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(
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input CLK,
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input RST_N,
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input EN,
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input CE,
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input ACLK1,
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input ACLK2,
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input [23: 0] LP0,
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input [23: 0] LP1,
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input [23: 0] LP2,
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input [23: 0] LP3,
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input DE_IN,
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output reg [23: 0] OUT,
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output reg DE
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);
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bit [23: 0] SUM;
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bit DE_IN_FF;
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always @(posedge CLK) begin
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if (EN && CE) begin
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SUM <= LP3;
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OUT <= SUM;
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DE_IN_FF <= DE_IN;
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DE <= DE_IN_FF;
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end
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end
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endmodule
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