From add502f1c78c399400f24f6ad0313667a7c28753 Mon Sep 17 00:00:00 2001 From: Philip Smart Date: Sun, 6 Sep 2020 00:51:00 +0100 Subject: [PATCH] Updates to allow the tranZPUter v2.2 to work with the new pin allocation --- common/tranzputer.c | 746 +------ include/tranzputer.h | 94 +- libraries/lib/libimath2-k64f.a | Bin 12504 -> 12504 bytes libraries/lib/libumansi-k64f.a | Bin 124218 -> 124218 bytes libraries/lib/libummath-k64f.a | Bin 2660 -> 2660 bytes libraries/lib/libummathf-k64f.a | Bin 63972 -> 63972 bytes libraries/lib/libummisc-k64f.a | Bin 6222 -> 6222 bytes libraries/lib/libumstdio-k64f.a | Bin 80050 -> 80138 bytes teensy3/core_pins.h | 3726 ++++++++++++++++--------------- teensy3/pins_teensy.c | 12 + 10 files changed, 2015 insertions(+), 2563 deletions(-) diff --git a/common/tranzputer.c b/common/tranzputer.c index e454d67..f4a34ec 100644 --- a/common/tranzputer.c +++ b/common/tranzputer.c @@ -37,6 +37,10 @@ // v1.2 July 2020 - Updates for the v2.1 tranZPUter board. I've used macro processing // to seperate v1+ and v2+ but I may well create two seperate directories // as both projects are updated. Alternatively I use git flow or similar, TBD! +// v1.3 Sep 2020 - Updates for the v2.2 tranZPUter board using an MK64FX512LLVQ 100 pin CPU +// instead of the Teensy board. As the v2.2 continues on its own branch, all +// references to previous boards and conditonal compilation have been removed +// to make the code simpler to read. // // Notes: See Makefile to enable/disable conditional components // @@ -165,7 +169,6 @@ static void __attribute((naked, noinline)) irqPortC_dummy(void) } #endif -#if TZBOARD == 100 || TZBOARD == 110 || TZBOARD == 200 || TZBOARD == 210 // This method is called everytime an active irq triggers on Port E. For this design, this means the two IO CS // lines, TZ_SVCREQ and TZ_SYSREQ. The SVCREQ is used when the Z80 requires a service, the SYSREQ is yet to // be utilised. @@ -181,17 +184,11 @@ static void __attribute((naked, noinline)) irqPortE(void) " ldr r5, [r4, #0] \n" " str r5, [r4, #0] \n" - // Is TZ_SVCREQ (E10) active (low), set flag and exit if it is. + // Is TZ_SVCREQ (E24) active (low), set flag and exit if it is. " movs r4, #1 \n" - " tst r5, #0x400 \n" - " beq ebr0 \n" - " strb r4, %[val0] \n" - - " ebr0: \n" - // Is TZ_SYSREQ (E11) active (low), set flag and exit if it is. - " tst r5, #0x800 \n" + " tst r5, #0x01000000 \n" " beq irqPortE_Exit \n" - " strb r4, %[val1] \n" + " strb r4, %[val0] \n" " irqPortE_Exit: \n" @@ -204,23 +201,12 @@ static void __attribute((naked, noinline)) irqPortE(void) return; } -#endif -#if TZBOARD == 110 || TZBOARD == 200 || TZBOARD == 210 // This method is called everytime an active irq triggers on Port D. For this design, this means the IORQ and RESET lines. // -// There are 3 versions of the same routine, originally using #if macro preprocessor statements but it became -// unwieldy. The purpose of the 3 versions are: -// 0 = Basic IRQ just sets the reset flag if the user presses reset on the host. -// 1,2 = Captures I/O and memory events, stores the address/data of the I/O command or processes the memory mapped transaction. -// 3 = MZ700 mode - this mode detects the MZ700 OUT commands and changes memory mode. Unfortunately it doesnt work 100% due to another -// ISR occasionally delaying the activation of this routine which means we cannot apply a WAIT state and consequently the data on the Z80 -// address bus has changed. Other than removing realtime clock and threads I cant see a way around it in software, will have to look at -// a hardware solution. +// Basic RESET detection. // -// Mode 0 - Basic RESET detection. -// -static void __attribute((naked, noinline)) irqPortD_Mode0(void) +static void __attribute((naked, noinline)) irqPortD(void) { // This code is critical, if the Z80 is running at higher frequencies then very little time to capture it's requests. asm volatile(" push {r0-r3,lr} \n"); @@ -247,606 +233,6 @@ static void __attribute((naked, noinline)) irqPortD_Mode0(void) return; } -#endif -// -// Mode 1 & 2 - Capture and store an IORQ or MREQ Memory Mapped event for the main thread to process. -// -#if TZBOARD == 110 -static void __attribute((naked, noinline)) irqPortD_Mode12(void) -{ - // Save minimum number of registers, cycles matter as we need to capture the address and halt the Z80 whilst we decode it. - asm volatile(" push {r0-r8,lr} \n" - - // Get the triggering interrupt. - " ldr r0, =0x4004c0a0 \n" - " ldr r4, [r0, #0] \n" - - // Assert BUSRQ so we keep the Z80 from moving to the next instruction in-case we need to update the memory latch. - " ldr r0, =0x43fe1900 \n" // CTL_BUSRQ - " movs r1, #1 \n" - " str r1, [r0,#0] \n" - ); - - asm volatile( // Is Z80_RESET active, set flag and exit. - // NB: We are testing the interrupt register, a bit is set if the given signal caused the interrupt, so a 1 means the signal went active. - " tst r4, #0x0010 \n" - " beq irqd0 \n" - " movs r6, #1 \n" - " strb r6, %[val1] \n" - " b irqPortD_Exit3 \n" - - : [val1] "=m" (z80Control.resetEvent) - : - : "r4","r5","r6","r7","r8","r9","r10","r11","r12"); - - asm volatile( // If the IORQ line and MREQ lines are high (another interrupt triggered us or false trigger) get out, cant work with incomplete data. - " irqd0: tst r4, #0x0008 \n" - " bne irqd1 \n" - " tst r4, #0x0004 \n" - " bne irqd10 \n" - " b irqPortD_Exit3 \n" - ); - - //////////////////////////////////////////// - // IORQ logic, intercept IO operations. - //////////////////////////////////////////// - - // Capture GPIO ports - this is necessary in order to make a clean capture and then decode. - asm volatile(" irqd1: ldr r0, =0x400ff010 \n" // GPIOA_PDIR - " ldr r4, [r0, #0] \n" - " add.w r0, #64 \n" // GPIOB_PDIR - " ldr r5, [r0, #0] \n" - " add.w r0, #64 \n" // GPIOC_PDIR - " ldr r6, [r0, #0] \n" - " add.w r0, #64 \n" // GPIOD_PDIR - " ldr r7, [r0, #0] \n" - " add.w r0, #64 \n" // GPIOE_PDIR - " ldr r8, [r0, #0] \n" - - : - : - : "r0","r1","r4","r5","r6","r7","r8","r9","r10","r11","r12"); - - asm volatile( // Is TZ_SVCREQ (E10) active (low), set flag and exit if it is. - " movs r0, #1 \n" - " tst r8, #0x400 \n" - " bne irqd2 \n" - " strb r0, %[val0] \n" - " b irqPortD_Exit3 \n" - - // Is TZ_SYSREQ (E11) active (low), set flag and exit if it is. - " irqd2: tst r8, #0x800 \n" - " bne irqd3 \n" - " strb r0, %[val1] \n" - " b irqPortD_Exit3 \n" - - : [val0] "+m" (z80Control.svcRequest), - [val1] "+m" (z80Control.sysRequest) - : - : "r0","r4","r5","r7","r8","r9","r10","r11","r12"); - - asm volatile( // Is Z80_WR active, continue if it is as we consider IO WRITE cycles. - " irqd3: tst r7, #0x200 \n" // Z80_WR = D9 v1.1+ - " beq irqd4 \n" - - // Is Z80_RD active, continue if it is as we consider IO READ cycles. - " tst r7, #0x800 \n" // Z80_RD = D11 v1.1+ - " bne irqPortD_Exit3 \n" - " irqd4: \n" - ); - - // Convert lower 8 address bits into a byte and store. - // - asm volatile(" and r0, r6, #0xFF \n" // Port C 7:0 = Z80 A7:A0 - - // Store the address for later processing.. - " strb r0, %[val0] \n" - " mov r8, r0 \n" // Addr in R8 - - : [val0] "=m" (z80Control.ioAddr) - : - : "r0","r1","r4","r5","r6","r7","r8","r9","r10","r11","r12"); - - #if 0 - // Convert data port bits into a byte and store. - asm volatile(" lsrs r1, r5, 16 \n" // Data Port B 23:17 = Z80 D7:D0 - " and r1, r1, #0xFF \n" // Clear out top bits. - " strb r1, %[val0] \n" - " mov r7, r0 \n" // Data in R7 - - : [val0] "=m" (z80Control.ioData) - : - : "r0","r1","r4","r5","r6","r7","r8","r9","r10","r11","r12"); - #endif - - // Process the IO request by setting the ioEvent flag as it wasnt an MZ700 memory switch request. - asm volatile(" movs r4, #1 \n" - " strb r4, %[val2] \n" - " b irqPortD_Exit12 \n" - - : [val2] "=m" (z80Control.ioEvent) - : - : "r4","r5","r6","r7","r8","r9","r10","r11","r12"); - - - //////////////////////////////////////////// - // MREQ logic, intercept memory operations. - //////////////////////////////////////////// - - // Convert 16 address bits into a byte and store. - // - asm volatile(" and r0, r4, #0xF000 \n" // Port A 15:12 = Z80 A15:A12 - " and r1, r6, #0xFFF \n" // Port C 11:0 = Z80 A11:A0 - " orr r0, r1 \n" // Complete address into R0 - - // Store the address for later processing.. - " strb r0, %[val0] \n" - " mov r8, r0 \n" // Addr in R8 - - : [val0] "=m" (z80Control.ioAddr) - : - : "r0","r1","r4","r5","r6","r7","r8","r9","r10","r11","r12"); - - #if 0 - // Convert data port bits into a byte and store. - asm volatile(" lsrs r1, r5, 16 \n" // Data Port B 23:17 = Z80 D7:D0 - " and r1, r1, #0xFF \n" // Clear out top bits. - " strb r1, %[val0] \n" - " mov r7, r0 \n" // Data in R7 - - : [val0] "=m" (z80Control.ioData) - : - : "r0","r1","r4","r5","r6","r7","r8","r9","r10","r11","r12"); - #endif - - asm volatile( // A memory swap event. - " movw r1," XSTR(MZ_MEMORY_SWAP) "\n" - " cmp r0, r1 \n" - " bne br0 \n" - " movs r2, #1 \n" - " b.n br1 \n" - " br0: \n" - // A memory reset event. - " movw r1, " XSTR(MZ_MEMORY_RESET) "\n" - " cmp r0, r1 \n" - " bne br2 \n" - " movs r2, #0 \n" - " br1: \n" - // Store to memorySwap - " strb r2, %[val0] \n" - " b.n irqPortC_Exit \n" - " br2: \n" - // A CRT to normal mode event. - " movw r1, " XSTR(MZ_CRT_NORMAL) "\n" - " cmp r0, r1 \n" - " bne br3 \n" - " movs r2, #0 \n" - " b.n br4 \n" - " br3: \n" - // A CRT to inverse mode event. - " movw r1, " XSTR(MZ_CRT_INVERSE) "\n" - " cmp r0, r1 \n" - " bne br5 \n" - " movs r2, #0 \n" - " br4: \n" - // Store to crtMode. - " strb r2, %[val1] \n" - " b.n irqPortC_Exit \n" - " br5: \n" - // Memory address in SCROLL region? - " sub.w r1, r0, " XSTR(MZ_SCROL_END - MZ_SCROL_BASE) "\n" - " cmp r1, #255 \n" - " bhi.n irqPortC_Exit \n" - " strb r0, %[val2] \n" - - : [val0] "+m" (z80Control.memorySwap), - [val1] "+m" (z80Control.crtMode), - [val2] "+m" (z80Control.scroll) - : - : "r2","r3","r4","r5","r7","r8","r9","r10","r11","r12"); - - - asm volatile(" irqPortD_Exit12: \n" - - // De-assert BUSRQ nothing more to do. - " ldr r4, =0x43fe1800 \n" // CTL_BUSRQ, Set=43fe1800, Clear=43fe1900 - " movs r5, #1 \n" - " str r5, [r4,#0] \n" - - // Reset the triggering interrupt, PORTD_ISFR <= PORTD_ISFR - " ldr r0, =0x4004c0a0 \n" - " ldr r4, [r0, #0] \n" - " str r4, [r0, #0] \n" - - // Restore registers, all done. - " pop {r0-r8,pc} \n" - : - : - : "r4","r5","r6","r7","r8","r9","r10","r11","r12"); - - return; -} -#endif -#if TZBOARD == 110 -// -// Mode 3 - MZ700 processing. -// -// v1.1 address reference: -// CTL_BUSRQ, Set=43fe1800, Clear=43fe1900 -// Z80_WAIT, Set=43fe183c, Clear=43fe193c -// CTL_BUSACK, Set=43fe1818, Clear=43fe1918 -// Z80_IORQ, Set=43fe180c, Clear=43fe190c -// Z80_MREQ, Set=43fe1808, Clear=43fe1908 -// -// -static void __attribute((naked, noinline)) irqPortD_Mode3(void) -{ - // Save minimum number of registers, cycles matter as we need to capture the address and halt the Z80 whilst we decode it. - asm volatile(" push {r0-r8,lr} \n" - - // Get the triggering interrupt. - " ldr r0, =0x4004c0a0 \n" - " ldr r4, [r0, #0] \n" - - // Assert BUSRQ so we keep the Z80 from moving to the next instruction in-case we need to update the memory latch. - " ldr r0, =0x43fe1900 \n" // CTL_BUSRQ - " movs r1, #1 \n" - " str r1, [r0,#0] \n" - ); - - asm volatile( // Is Z80_RESET active, set flag and exit. - // NB: We are testing the interrupt register, a bit is set if the given signal caused the interrupt, so a 1 means the signal went active. - " tst r4, #0x0010 \n" - " beq irqd0 \n" - " movs r6, #1 \n" - " strb r6, %[val1] \n" - " b irqPortD_Exit3 \n" - - : [val1] "=m" (z80Control.resetEvent) - : - : "r4","r5","r6","r7","r8","r9","r10","r11","r12"); - - asm volatile( // If the IORQ line is high (another interrupt triggered us or false trigger) get out, cant work with incomplete data. - " irqd0: tst r4, #0x0008 \n" - " beq irqPortD_Exit3 \n" - ); - - // Capture GPIO ports - this is necessary in order to make a clean capture and then decode. - asm volatile(" ldr r0, =0x400ff010 \n" // GPIOA_PDIR - " ldr r4, [r0, #0] \n" - " add.w r0, #64 \n" // GPIOB_PDIR - " ldr r5, [r0, #0] \n" - " add.w r0, #64 \n" // GPIOC_PDIR - " ldr r6, [r0, #0] \n" - " add.w r0, #64 \n" // GPIOD_PDIR - " ldr r7, [r0, #0] \n" - " add.w r0, #64 \n" // GPIOE_PDIR - " ldr r8, [r0, #0] \n" - - : - : - : "r0","r1","r4","r5","r6","r7","r8","r9","r10","r11","r12"); - - asm volatile( // Is TZ_SVCREQ (E10) active (low), set flag and exit if it is. - " movs r0, #1 \n" - " tst r8, #0x400 \n" - " bne irqd1 \n" - " strb r0, %[val0] \n" - " b irqPortD_Exit3 \n" - - // Is TZ_SYSREQ (E11) active (low), set flag and exit if it is. - " irqd1: tst r8, #0x800 \n" - " bne irqd2 \n" - " strb r0, %[val1] \n" - " b irqPortD_Exit3 \n" - - : [val0] "+m" (z80Control.svcRequest), - [val1] "+m" (z80Control.sysRequest) - : - : "r0","r4","r5","r7","r8","r9","r10","r11","r12"); - - asm volatile( // Is Z80_WR active, continue if it is as we consider IO WRITE cycles. - " irqd2: tst r7, #0x200 \n" // Z80_WR = D9 v1.1+ - " beq irqd3 \n" - - // Is Z80_RD active, continue if it is as we consider IO READ cycles. - " tst r7, #0x800 \n" // Z80_RD = D11 v1.1+ - " bne irqPortD_Exit3 \n" - " irqd3: \n" - ); - - // Convert lower 8 address bits into a byte and store. - // - asm volatile(" and r0, r6, #0xFF \n" // Port C 7:0 = Z80 A7:A0 - - // Store the address for later processing.. - " strb r0, %[val0] \n" - " mov r8, r0 \n" // Addr in R8 - - : [val0] "=m" (z80Control.ioAddr) - : - : "r0","r1","r4","r5","r6","r7","r8","r9","r10","r11","r12"); - - // MZ700 memory mode switch? - // 0x0000:0x0FFF 0xD000:0xFFFF - // 0xE0 = DRAM - // 0xE1 = DRAM - // 0xE2 = MONITOR - // 0xE3 = Memory Mapped I/O - // 0xE4 = MONITOR Memory Mapped I/O - // 0xE5 = Inhibit - // 0xE6 = Return to state prior to 0xE5 - // - // Must be in range 0xE0-0xE6 to be an MZ700 operation. - // - // ADDR 7 ADDR 6 ADDR 5 ADDR 4 ADDR 3 ADDR 2 ADDR 1 ADDR 0 - // PORT C:7 PORT C:6 PORT C:5 PORT C:4 PORT C:3 PORT C:2 PORT C:1 PORT C:0 - // - // DATA 7 DATA 6 DATA 5 DATA 4 DATA 3 DATA 2 DATA 1 DATA 0 - // PORT B:23 PORT B:22 PORT B:21 PORT B:20 PORT B:19 PORT B:18 PORT B:17 PORT B:16 - // - // - // Z80 WAIT SYSCLK CTL BUSACK CTL BUSRQ Z80 IORQ Z80 WR - // PORT D:15 PORT A:5 PORT D:6 PORT D:0 PORT D:3 PORT D:9 - // - // CTL_BUSRQ, Set=43fe1800, Clear=43fe1900 - // Z80_WAIT, Set=43fe183c, Clear=43fe193c - // CTL_BUSACK, Set=43fe1818, Clear=43fe1918 - // Z80_IORQ, Set=43fe180c, Clear=43fe190c - // Z80_MREQ, Set=43fe1808, Clear=43fe1908 - // Z80_RD, Set=43fe182c, Clear=43fe192c - // Z80_WR, Set=43fe1824, Clear=43fe1924 - // - asm volatile(" cmp.w r8, #224 \n" - " blt irqd20 \n" - " cmp.w r8, #230 \n" - " bgt irqd20 \n" - " \n" - " ldr r6, %[val1] \n" // Retrieve the config value for the MZ700. - " tst r6, #0x40000 \n" - " bne irqd16 \n" // For locked mode, only service E4, E5 & E6. - " and r6, r6, #0xFFFFFF00 \n" // Clear out the memoryMode[current[ as a new value will be stored. - - // 0xE0 - " irqd12: cmp.w r8, #224 \n" // R8 = address location of OUT command on Z80. - " bne irqd13 \n" - " orr r6, #65536 \n" // mode[16] = 1 - " b irqd11x \n" - - // 0xE1 - " irqd13: cmp.w r8, #225 \n" - " bne irqd14 \n" - " orr r6, #131072 \n" // mode[17] = 1 - " b irqd11x \n" - - // 0xE2 - " irqd14: cmp.w r9, #226 \n" - " bne irqd15 \n" - " bic r6, #65536 \n" // mode[16] = 0 - " b irqd11x \n" - - // 0xE3 - " irqd15: cmp.w r8, #227 \n" - " bne irqd16 \n" - " bic r6, #131072 \n" // mode[17] = 0 - - // if(z80Control.mz700.mode[17:16] == '00') - " irqd11x: tst r6, #0x30000 \n" - " bne irqd12x \n" - " orr r6," XSTR(TZMM_TZFS + TZMM_ENIOWAIT) "\n" // memoryMode = 2 - " b irqd19 \n" - - // if(z80Control.mz700.mode[17:16] == '10') - " irqd12x: tst r6, #0x20000 \n" - " beq irqd13x \n" - " tst r6, #0x10000 \n" - " bne irqd14x \n" - " orr r6," XSTR(TZMM_MZ700_1 + TZMM_ENIOWAIT) "\n" // memoryMode = 11 - " b irqd19 \n" - - // if(z80Control.mz700.mode[17:16] == '01') - " irqd13x: orr r6," XSTR(TZMM_MZ700_0 + TZMM_ENIOWAIT) "\n" // memoryMode = 10 - " b irqd19 \n" - - // if(z80Control.mz700.mode[17:16] == '11) - " irqd14x: orr r6," XSTR(TZMM_MZ700_2 + TZMM_ENIOWAIT) "\n" // memoryMode = 12 - " b irqd19 \n" - - // 0xE4 - Reset to default. - " irqd16: cmp.w r8, #228 \n" - " bne irqd17 \n" - " mov r6," XSTR(TZMM_TZFS + TZMM_ENIOWAIT) "\n" // mode[17:16] = '00', mode[inhibit] = '0', memoryMode[current] = 2, memoryMode[old] = 2 - " b irqd19 \n" - - // 0xE5 - Lock the region D000-FFFF by setting memory mode to 13. - " irqd17: cmp.w r8, #229 \n" - " bne irqd18 \n" - " orr r6, #0x40000 \n" // mode[inhibit] = 1 - " and r5, r6, #0x0000FF00 \n" // Look at previous memory mode and use to decide the mode we lock into. - " cmp r5, #0xB00 \n" - " bne irqd17x \n" - " orr r6," XSTR(TZMM_MZ700_3 + TZMM_ENIOWAIT) "\n" // memoryMode[current] = 13 - Monitor ROM at 0000:0FFF - " b irqd19 \n" - " irqd17x: orr r6," XSTR(TZMM_MZ700_4 + TZMM_ENIOWAIT) "\n" // memoryMode[current] = 14 - System RAM at 0000:0FFF - " b irqd19 \n" - - // 0xE6 - Unlock the region D000-FFF by returning the memory mode to original. - " irqd18: cmp.w r8, #230 \n" - " bne irqd2 \n" - " and r6, #0xFFFBFFFF \n" // mode[inhibit] = 0 - " and r5, r6, #0x0000FF00 \n" - " lsrs r5, r5, #8 \n" - " orr r6, r5 \n" // memoryMode[current] = memoryMode[old] - - // Store the changed value back to the control structure. - " irqd19: lsls r8, r8, #24 \n" - " and r6, r6, #0x00FFFFFF \n" - " orr r6, r8 \n" - " and r5, r6, #0x000000FF \n" - " lsls r5, r5, #8 \n" - " and r6, r6, #0xFFFF00FF \n" - " orr r6, r5 \n" // memoryMode[old] = memoryMode[current] - " str r6, %[val1] \n" - - // Output to variables. - : [val1] "=m" (z80Control.mz700.config) - // Input from variables. - : - : "r5","r6","r7","r8","r9","r10","r11","r12"); - - // Write memory mode to the latch. - // This requires all signals A7-A0, D7-D0, WR, IORQ be set to output and de-asserted, data and address set - // control signals asserted, de-asserted then all signals returned to being inputs. Finally reset the IRQ!! - // - asm volatile(" mov r2, r6 \n" - - // Read current PDOR values ready to be changed. - // - " ldr r0, =0x400FF040 \n" // PDOR B - " ldr r5, [r0, #0] \n" - " lsls r2, r2, 16 \n" // Data into position. - " and r2, #0b00000000111111110000000000000000 \n" // Mask the shifted data. - " and r5, #0b11111111000000001111111111111111 \n" // Clear out the data bits in the output register. - " orr r5, r2 \n" // Add data onto register bits. - " str r5, [r0, #0] \n" // And put back to output register. - - " add r0, #0x40 \n" // PDOR C - " ldr r6, [r0, #0] \n" - " and r6, #0b11111111111111111111111100000000 \n" // Port C - " orr r6, #0b00000000000000000000000001100000 \n" // Set address to 60H - " str r6, [r0, #0] \n" - - " add r0, #0x40 \n" // PDOR D - " ldr r7, [r0, #0] \n" - " orr r7, #0b00000000000000000000000000001000 \n" // Set all control signals to inactive. - " orr r1, #0b00000000000000000000001000000000 \n" - " str r7, [r0, #0] \n" - - // Setup the Data Direction Register PDDR[x]. - // - " ldr r0, =0x400FF054 \n" // Port B - " ldr r1, [r0, #0] \n" - " orr r1, #0b00000000111111110000000000000000 \n" - " str r1, [r0, #0] \n" - " add r0, #0x40 \n" // Port C - " ldr r1, [r0, #0] \n" - " orr r1, #0b00000000000000000000000011111111 \n" - " str r1, [r0, #0] \n" - " add r0, #0x40 \n" // Port D - " ldr r1, [r0, #0] \n" - " orr r1, #0b00000000000000000000000000001000 \n" - " orr r1, #0b00000000000000000000001000000000 \n" - " str r1, [r0, #0] \n" - ); - - // Setup the required pins for output mode (CTL_BUSRQ, Z80_WR). - // - asm volatile(" ldr r0, =0x4004A084 \n" // Port B high - " ldr r1, =0x00FF0143 \n" // Bits 23:16 - " str r1, [r0,#0] \n" - - " add r0, #0xFFC \n" // Port C low - " ldr r1, =0x00FF0143 \n" // Bits 7:0 - " str r1, [r0,#0] \n" - - " add r0, #0x1000 \n" // Port D low - " ldr r1, =0x02080143 \n" // Bits 9, 3 - " str r1, [r0,#0] \n" - - // Update the PDOR registers with the determined values. - // - " ldr r0, =0x400FF040 \n" // PDOR B - " str r5, [r0, #0] \n" - " add r0, #0x40 \n" // PDOR C - " str r6, [r0, #0] \n" - " add r0, #0x40 \n" // PDOR D - " str r7, [r0, #0] \n" - ); - - // Start the write cycle, IORQ and WR go low. - asm volatile(" mov r1, #1 \n" - " ldr r0, =0x43fe190c \n" // Set IORQ Set=43fe180c, Clear=43fe190c - " str r1, [r0,#0] \n" - " add r0, #0x18 \n" // Set WR Set=43fe1824, Clear=43fe1924 - " str r1, [r0,#0] \n" - - // A small delay to ensure the pulse width is sufficient to cater for 55ns of the flash decoder + 40ns for the HCT138 + latch timing. - // The main criteria is data settle time prior to rising edge on the latch. - " movs r1, #8 \n" - " sd8: subs r1, #1 \n" - " bne sd8 \n" - - // Complete the write cycle by raising the WR and IORQ signals. - " mov r1, #1 \n" - " ldr r0, =0x43fe180c \n" // Set IORQ Set=43fe180c, Clear=43fe190c - " str r1, [r0,#0] \n" - " add r0, #0x18 \n" // Set WR Set=43fe1824, Clear=43fe1924 - " str r1, [r0,#0] \n" - ); - - // Revert the Data Direction Register PDDR[x]. - // - asm volatile(" ldr r0, =0x400FF0D4 \n" // Port D - " ldr r1, [r0, #0] \n" - " and r1, #0b11111111111111111111110111110111 \n" - " str r1, [r0, #0] \n" - " sub r0, #0x40 \n" // Port C - " ldr r1, [r0, #0] \n" - " and r1, #0b11111111111111111111111100000000 \n" - " str r1, [r0, #0] \n" - " sub r0, #0x40 \n" // Port B - " ldr r1, [r0, #0] \n" - " and r1, #0b11111111000000001111111111111111 \n" - " str r1, [r0, #0] \n" - ); - - // Global Pin Control Register - // Setup all changed signals to now be inputs. - asm volatile(" ldr r0, =0x4004A084 \n" // Port B high - " ldr r1, =0x00FF0103 \n" // Bits 23:16 - " str r1, [r0,#0] \n" - - " add r0, #0xFFC \n" // Port C low - " ldr r1, =0x00FF0103 \n" // Bits 7:0 - " str r1, [r0,#0] \n" - - " add r0, #0x1000 \n" // Port D low - " ldr r1, =0x02080103 \n" // Bits 9, 3 - " str r1, [r0,#0] \n" - - // After writing out the data, jump to exit, we dont set the ioEvent flag as the event has been processed already. - " b irqPortD_Exit3 \n" - ); - - asm volatile( // Process the IO request by setting the ioEvent flag as it wasnt an MZ700 memory switch request. - " irqd20: movs r4, #1 \n" - " strb r4, %[val2] \n" - - : [val2] "+m" (z80Control.ioEvent) - : - : "r4","r5","r6","r7","r8","r9","r10","r11","r12"); - - asm volatile(" irqPortD_Exit3: \n" - - // De-assert BUSRQ nothing more to do. - " ldr r4, =0x43fe1800 \n" // CTL_BUSRQ, Set=43fe1800, Clear=43fe1900 - " movs r5, #1 \n" - " str r5, [r4,#0] \n" - - // Reset the triggering interrupt, PORTD_ISFR <= PORTD_ISFR - " ldr r0, =0x4004c0a0 \n" - " ldr r4, [r0, #0] \n" - " str r4, [r0, #0] \n" - - // Restore registers, all done. - " pop {r0-r8,pc} \n" - : - : - : "r4","r5","r6","r7","r8","r9","r10","r11","r12"); - - return; -} -#endif // Method to install the interrupt vector and enable it to capture Z80 memory/IO operations. // @@ -860,18 +246,10 @@ static void setupIRQ(void) // For the MZ700 we need to enable IORQ to process the OUT statements the Z80 generates for memory mode selection. case MZ700: // Install the dummy method to be called when PortE triggers. -#if TZBOARD == 110 - _VectorsRam[IRQ_PORTE + 16] = irqPortE_dummy; -#elif TZBOARD == 200 || TZBOARD == 210 _VectorsRam[IRQ_PORTE + 16] = irqPortE; -#endif // Install the method to be called when PortD triggers. -#if TZBOARD == 110 - _VectorsRam[IRQ_PORTD + 16] = irqPortD_Mode3; -#elif TZBOARD == 200 || TZBOARD == 210 - _VectorsRam[IRQ_PORTD + 16] = irqPortD_Mode0; -#endif + _VectorsRam[IRQ_PORTD + 16] = irqPortD; // Setup the IRQ for Z80_IORQ. installIRQ(Z80_IORQ, IRQ_MASK_FALLING); @@ -879,21 +257,8 @@ static void setupIRQ(void) // Setup the IRQ for Z80_RESET. installIRQ(Z80_RESET, IRQ_MASK_FALLING); -#if TZBOARD == 110 - // Setup the IRQ for Z80_MREQ. - //installIRQ(Z80_MREQ, IRQ_MASK_RISING); - - // Remove previous interrupts not needed in this mode. - removeIRQ(TZ_SVCREQ); - removeIRQ(TZ_SYSREQ); - -#elif TZBOARD == 200 || TZBOARD == 210 - // Setup the IRQ for TZ_SYSREQ. - installIRQ(TZ_SYSREQ, IRQ_MASK_FALLING); - // Setup the IRQ for Z80_RESET. installIRQ(Z80_RESET, IRQ_MASK_FALLING); -#endif // Set relevant priorities to meet latency. NVIC_SET_PRIORITY(IRQ_PORTD, 0); @@ -906,11 +271,7 @@ static void setupIRQ(void) _VectorsRam[IRQ_PORTE + 16] = irqPortE_dummy; // Install the method to be called when PortD triggers. -#if TZBOARD == 110 - _VectorsRam[IRQ_PORTD + 16] = irqPortD_Mode3; -#elif TZBOARD == 200 || TZBOARD == 210 - _VectorsRam[IRQ_PORTD + 16] = irqPortD_Mode0; -#endif + _VectorsRam[IRQ_PORTD + 16] = irqPortD; // Setup the IRQ for Z80_IORQ. installIRQ(Z80_IORQ, IRQ_MASK_FALLING); @@ -918,14 +279,8 @@ static void setupIRQ(void) // Setup the IRQ for Z80_RESET. installIRQ(Z80_RESET, IRQ_MASK_FALLING); -#if TZBOARD == 110 - // Setup the IRQ for Z80_MREQ. - //installIRQ(Z80_MREQ, IRQ_MASK_RISING); -#endif - // Remove previous interrupts not needed in this mode. removeIRQ(TZ_SVCREQ); - removeIRQ(TZ_SYSREQ); // Set relevant priorities to meet latency. NVIC_SET_PRIORITY(IRQ_PORTD, 0); @@ -939,14 +294,11 @@ static void setupIRQ(void) _VectorsRam[IRQ_PORTE + 16] = irqPortE; // Install the method to be called when PortD triggers. - _VectorsRam[IRQ_PORTD + 16] = irqPortD_Mode0; + _VectorsRam[IRQ_PORTD + 16] = irqPortD; // Setup the IRQ for TZ_SVCREQ. installIRQ(TZ_SVCREQ, IRQ_MASK_FALLING); - // Setup the IRQ for TZ_SYSREQ. - installIRQ(TZ_SYSREQ, IRQ_MASK_FALLING); - // Setup the IRQ for Z80_RESET. installIRQ(Z80_RESET, IRQ_MASK_FALLING); @@ -976,7 +328,6 @@ static void disableIRQ(void) // Remove the interrupts. removeIRQ(TZ_SVCREQ); - removeIRQ(TZ_SYSREQ); removeIRQ(Z80_IORQ); removeIRQ(Z80_RESET); @@ -999,11 +350,6 @@ static void restoreIRQ(void) // Setup the IRQ for Z80_IORQ. installIRQ(Z80_IORQ, IRQ_MASK_FALLING); -#if TZBOARD == 110 - // Setup the IRQ for Z80_MREQ. - //installIRQ(Z80_MREQ, IRQ_MASK_FALLING); -#endif - // Setup the IRQ for Z80_RESET. installIRQ(Z80_RESET, IRQ_MASK_FALLING); break; @@ -1013,11 +359,6 @@ static void restoreIRQ(void) // Setup the IRQ for Z80_IORQ. installIRQ(Z80_IORQ, IRQ_MASK_FALLING); -#if TZBOARD == 110 - // Setup the IRQ for Z80_MREQ. - //installIRQ(Z80_MREQ, IRQ_MASK_FALLING); -#endif - // Setup the IRQ for Z80_RESET. installIRQ(Z80_RESET, IRQ_MASK_FALLING); break; @@ -1028,9 +369,6 @@ static void restoreIRQ(void) // Setup the IRQ for TZ_SVCREQ. installIRQ(TZ_SVCREQ, IRQ_MASK_FALLING); - // Setup the IRQ for TZ_SYSREQ. - installIRQ(TZ_SYSREQ, IRQ_MASK_FALLING); - // Setup the IRQ for Z80_RESET. installIRQ(Z80_RESET, IRQ_MASK_FALLING); break; @@ -1098,7 +436,6 @@ void setupZ80Pins(uint8_t initTeensy, volatile uint32_t *millisecondTick) pinMap[Z80_MEM2] = Z80_MEM2_PIN; pinMap[Z80_MEM3] = Z80_MEM3_PIN; pinMap[Z80_MEM4] = Z80_MEM4_PIN; - pinMap[ENIOWAIT] = ENIOWAIT_PIN; pinMap[Z80_IORQ] = Z80_IORQ_PIN; pinMap[Z80_MREQ] = Z80_MREQ_PIN; @@ -1113,7 +450,6 @@ void setupZ80Pins(uint8_t initTeensy, volatile uint32_t *millisecondTick) pinMap[MB_SYSCLK] = SYSCLK_PIN; pinMap[TZ_BUSACK] = TZ_BUSACK_PIN; pinMap[TZ_SVCREQ] = TZ_SVCREQ_PIN; - pinMap[TZ_SYSREQ] = TZ_SYSREQ_PIN; pinMap[CTL_BUSACK] = CTL_BUSACK_PIN; pinMap[CTL_BUSRQ] = CTL_BUSRQ_PIN; @@ -1207,7 +543,7 @@ void resetZ80(void) // __disable_irq(); pinOutputSet(Z80_RESET, LOW); - for(volatile uint32_t pulseWidth=0; pulseWidth < 100; pulseWidth++); + for(volatile uint32_t pulseWidth=0; pulseWidth < 200; pulseWidth++); pinHigh(Z80_RESET); pinInput(Z80_RESET); __enable_irq(); @@ -1459,11 +795,7 @@ uint8_t writeZ80Memory(uint16_t addr, uint8_t data) pinLow(Z80_WR); // On a Teensy3.5 K64F running at 120MHz this delay gives a pulsewidth of 760nS. -#if TZBOARD == 100 || TZBOARD == 110 for(volatile uint32_t pulseWidth=0; pulseWidth < 4; pulseWidth++); -#elif TZBOARD == 200 || TZBOARD == 210 - for(volatile uint32_t pulseWidth=0; pulseWidth < 4; pulseWidth++); -#endif // Another wait loop check as the Z80 can assert wait at the time of Write or anytime before it is deasserted. while((*ms - startTime) < 200 && pinGet(Z80_WAIT) == 0); @@ -1473,12 +805,8 @@ uint8_t writeZ80Memory(uint16_t addr, uint8_t data) pinLow(Z80_WR); // On a Teensy3.5 K64F running at 120MHz this delay gives a pulsewidth of 760nS. -#if TZBOARD == 100 || TZBOARD == 110 - for(volatile uint32_t pulseWidth = 0; pulseWidth < 2; pulseWidth++); // With the tranZPUter SW v2 boards, need to increase the write pulse width, alternatively wait until a positive edge on the CPU clock. -#elif TZBOARD == 200 || TZBOARD == 210 for(volatile uint32_t pulseWidth=0; pulseWidth < 3; pulseWidth++); -#endif } // Complete the write cycle. @@ -1529,24 +857,14 @@ uint8_t readZ80Memory(uint16_t addr) { // On a Teensy3.5 K64F running at 120MHz this delay gives a pulsewidth of 760nS. This gives time for the addressed device to present the data // on the data bus. -#if TZBOARD == 100 || TZBOARD == 110 - for(volatile uint32_t pulseWidth=0; pulseWidth < 1; pulseWidth++); - // With the tranZPUter SW v2 boards, need to increase the write pulse width, alternatively wait until a positive edge on the CPU clock. -#elif TZBOARD == 200 || TZBOARD == 210 for(volatile uint32_t pulseWidth=0; pulseWidth < 4; pulseWidth++); -#endif // A wait loop check as the Z80 can assert wait during the Read operation to request more time. Set a timeout in case of hardware lockup. while((*ms - startTime) < 100 && pinGet(Z80_WAIT) == 0); } else { // On the tranZPUter v1.1, because of reorganisation of the signals, the time to process is less and so the pulse width under v1.0 is insufficient. -#if TZBOARD == 100 || TZBOARD == 110 - for(volatile uint32_t pulseWidth=0; pulseWidth < 1; pulseWidth++); - // With the tranZPUter SW v2 boards, need to increase the write pulse width to accommodate the different memories used. -#elif TZBOARD == 200 || TZBOARD == 210 for(volatile uint32_t pulseWidth=0; pulseWidth < 4; pulseWidth++); -#endif } // Fetch the data before deasserting the signals. @@ -1593,11 +911,7 @@ uint8_t writeZ80IO(uint16_t addr, uint8_t data) pinLow(Z80_WR); // On a Teensy3.5 K64F running at 120MHz this delay gives a pulsewidth of 760nS. -#if TZBOARD == 100 || TZBOARD == 110 - //for(volatile uint32_t pulseWidth=0; pulseWidth < 2; pulseWidth++); -#elif TZBOARD == 200 || TZBOARD == 210 for(volatile uint32_t pulseWidth=0; pulseWidth < 2; pulseWidth++); -#endif // Another wait loop check as the Z80 can assert wait at the time of Write or anytime before it is deasserted. while((*ms - startTime) < 200 && pinGet(Z80_WAIT) == 0); @@ -1607,9 +921,7 @@ uint8_t writeZ80IO(uint16_t addr, uint8_t data) pinLow(Z80_WR); // With the tranZPUter SW v2 boards, need to increase the write pulse width as the latch is synchronous, alternatively wait until a positive edge on the CPU clock. -#if TZBOARD == 200 || TZBOARD == 210 for(volatile uint32_t pulseWidth=0; pulseWidth < 8; pulseWidth++); -#endif } // Complete the write cycle. @@ -1769,7 +1081,7 @@ void setCtrlLatch(uint8_t latchVal) { // Gain control of the bus then set the latch value. // - if(reqTranZPUterBus(500) == 0) + if(reqTranZPUterBus(DEFAULT_BUSREQ_TIMEOUT) == 0) { // Setup the pins to perform a write operation. // @@ -1806,7 +1118,7 @@ uint32_t setZ80CPUFrequency(float frequency, uint8_t action) { // Gain control of the bus to change the CPU frequency latch. // - if(reqTranZPUterBus(500) == 0) + if(reqTranZPUterBus(DEFAULT_BUSREQ_TIMEOUT) == 0) { // Setup the pins to perform a write operation. // @@ -1836,7 +1148,7 @@ uint8_t copyFromZ80(uint8_t *dst, uint32_t src, uint32_t size, uint8_t mainBoard // Request the correct bus. // - if( (mainBoard == 0 && reqTranZPUterBus(500) == 0) || (mainBoard != 0 && reqMainboardBus(500) == 0) ) + if( (mainBoard == 0 && reqTranZPUterBus(DEFAULT_BUSREQ_TIMEOUT) == 0) || (mainBoard != 0 && reqMainboardBus(DEFAULT_BUSREQ_TIMEOUT) == 0) ) { // Setup the pins to perform a read operation (after setting the latch to starting value). // @@ -1895,7 +1207,7 @@ uint8_t copyToZ80(uint32_t dst, uint8_t *src, uint32_t size, uint8_t mainBoard) // Request the correct bus. // - if( (mainBoard == 0 && reqTranZPUterBus(500) == 0) || (mainBoard != 0 && reqMainboardBus(500) == 0) ) + if( (mainBoard == 0 && reqTranZPUterBus(DEFAULT_BUSREQ_TIMEOUT) == 0) || (mainBoard != 0 && reqMainboardBus(DEFAULT_BUSREQ_TIMEOUT) == 0) ) { // Setup the pins to perform a write operation. // @@ -1943,7 +1255,7 @@ void fillZ80Memory(uint32_t addr, uint32_t size, uint8_t data, uint8_t mainBoard // Locals. uint8_t upperAddrBits = 0; - if( (mainBoard == 0 && reqTranZPUterBus(500) == 0) || (mainBoard != 0 && reqMainboardBus(500) == 0) ) + if( (mainBoard == 0 && reqTranZPUterBus(DEFAULT_BUSREQ_TIMEOUT) == 0) || (mainBoard != 0 && reqMainboardBus(DEFAULT_BUSREQ_TIMEOUT) == 0) ) { // Setup the pins to perform a read operation (after setting the latch to starting value). // @@ -1986,7 +1298,7 @@ void captureVideoFrame(enum VIDEO_FRAMES frame, uint8_t noAttributeFrame) { // Locals. - if(reqMainboardBus(500) == 0) + if(reqMainboardBus(DEFAULT_BUSREQ_TIMEOUT) == 0) { // Setup the pins to perform a read operation (after setting the latch to starting value). // @@ -2033,7 +1345,7 @@ void refreshVideoFrame(enum VIDEO_FRAMES frame, uint8_t scrolHome, uint8_t noAtt { // Locals. - if(reqMainboardBus(500) == 0) + if(reqMainboardBus(DEFAULT_BUSREQ_TIMEOUT) == 0) { // Setup the pins to perform a write operation. // @@ -2220,10 +1532,10 @@ FRESULT loadZ80Memory(const char *src, uint32_t fileOffset, uint32_t addr, uint3 // Request the board according to the mainboard flag, mainboard = 1 then the mainboard is controlled otherwise the tranZPUter board. if(mainBoard == 0) { - reqTranZPUterBus(500); + reqTranZPUterBus(DEFAULT_BUSREQ_TIMEOUT); } else { - reqMainboardBus(500); + reqMainboardBus(DEFAULT_BUSREQ_TIMEOUT); } // If successful, setup the control pins for upload mode. @@ -2407,7 +1719,7 @@ FRESULT saveZ80Memory(const char *dst, uint32_t addr, uint32_t size, t_svcDirEnt if(!fr0) { - if( (mainBoard == 0 && reqTranZPUterBus(500) == 0) || (mainBoard != 0 && reqMainboardBus(500) == 0) ) + if( (mainBoard == 0 && reqTranZPUterBus(DEFAULT_BUSREQ_TIMEOUT) == 0) || (mainBoard != 0 && reqMainboardBus(DEFAULT_BUSREQ_TIMEOUT) == 0) ) { // Setup the pins to perform a read operation (after setting the latch to starting value). // @@ -2501,7 +1813,7 @@ int memoryDumpZ80(uint32_t memaddr, uint32_t memsize, uint32_t dispaddr, uint8_t // Request the correct bus. // - if( (mainBoard == 0 && reqTranZPUterBus(500) == 0) || (mainBoard != 0 && reqMainboardBus(500) == 0) ) + if( (mainBoard == 0 && reqTranZPUterBus(DEFAULT_BUSREQ_TIMEOUT) == 0) || (mainBoard != 0 && reqMainboardBus(DEFAULT_BUSREQ_TIMEOUT) == 0) ) { // Setup the pins to perform a read operation (after setting the latch to starting value). // @@ -2789,7 +2101,7 @@ uint8_t setZ80SvcStatus(uint8_t status) // Request the tranZPUter bus. // - if(reqTranZPUterBus(500) == 0) + if(reqTranZPUterBus(DEFAULT_BUSREQ_TIMEOUT) == 0) { // Setup the pins to perform a write operation. // @@ -4321,11 +3633,7 @@ void processServiceRequest(void) // Load the 40 column MZ700 1Z-013A bios into memory for compatibility switch. case TZSVC_CMD_LOAD700BIOS40: -#if TZBOARD == 100 || TZBOARD == 110 - if((status=loadZ80Memory((const char *)MZ_ROM_1Z_013A_KM_40C, 0, MZ_MROM_ADDR, 0, 0, 0, 1)) != FR_OK) -#elif TZBOARD == 200 || TZBOARD == 210 if((status=loadZ80Memory((const char *)MZ_ROM_1Z_013A_40C, 0, MZ_MROM_ADDR, 0, 0, 0, 1)) != FR_OK) -#endif { printf("Error: Failed to load %s into tranZPUter memory.\n", MZ_ROM_1Z_013A_40C); } @@ -4342,11 +3650,7 @@ void processServiceRequest(void) // Load the 80 column MZ700 1Z-013A bios into memory for compatibility switch. case TZSVC_CMD_LOAD700BIOS80: -#if TZBOARD == 100 || TZBOARD == 110 - if((status=loadZ80Memory((const char *)MZ_ROM_1Z_013A_KM_80C, 0, MZ_MROM_ADDR, 0, 0, 0, 1)) != FR_OK) -#elif TZBOARD == 200 || TZBOARD == 210 if((status=loadZ80Memory((const char *)MZ_ROM_1Z_013A_80C, 0, MZ_MROM_ADDR, 0, 0, 0, 1)) != FR_OK) -#endif { printf("Error: Failed to load %s into tranZPUter memory.\n", MZ_ROM_1Z_013A_80C); } diff --git a/include/tranzputer.h b/include/tranzputer.h index f0322b4..97ea4dc 100755 --- a/include/tranzputer.h +++ b/include/tranzputer.h @@ -9,7 +9,8 @@ // Copyright: (c) 2019-2020 Philip Smart // // History: May 2020 - Initial write of the TranZPUter software. -// July 2020- Updates to accommodate v2.1 of the tranZPUter board. +// Jul 2020 - Updates to accommodate v2.1 of the tranZPUter board. +// Sep 2020 - Updates to accommodate v2.2 of the tranZPUter board. // // Notes: See Makefile to enable/disable conditional components // @@ -36,15 +37,10 @@ // Configurable constants. // -//#define DECODE_Z80_IO 3 // Flag to enable code, via interrupt, to capture Z80 actions on I/O ports an Memory mapped I/O. - // 0 = No code other than direct service request interrupts. - // 1 = Decode Z80 I/O address operations. - // 2 = Decode Z80 I/O operations with data. - // 3 = NZ700 memory mode decode - This doesnt work per original, the memory change occurs one instruction after the OUT instruction due to the way the Z80 functions in respect to BUSRQ. #define REFRESH_BYTE_COUNT 8 // This constant controls the number of bytes read/written to the z80 bus before a refresh cycle is needed. #define RFSH_BYTE_CNT 256 // Number of bytes we can write before needing a full refresh for the DRAM. -#define TZBOARD 210 // tranZPUter SW Hardware versions - v1.0 = 110, v1.1 = 110, v2.0 = 200 and v2.1 = 210 #define HOST_MON_TEST_VECTOR 0x4 // Address in the host monitor to test to identify host type. +#define DEFAULT_BUSREQ_TIMEOUT 1000 // Timeout for a Z80 Bus request operation in milliseconds. // tranZPUter Memory Modes - select one of the 32 possible memory models using these constants. // @@ -199,15 +195,14 @@ // Pin Constants - Pins assigned at the hardware level to specific tasks/signals. // -#define MAX_TRANZPUTER_PINS 53 +#define MAX_TRANZPUTER_PINS 51 #define Z80_MEM0_PIN 16 #define Z80_MEM1_PIN 17 #define Z80_MEM2_PIN 19 #define Z80_MEM3_PIN 18 -#define Z80_MEM4_PIN 49 -#define ENIOWAIT_PIN 50 -#define Z80_WR_PIN 48 -#define Z80_RD_PIN 55 +#define Z80_MEM4_PIN 71 // 49 +#define Z80_WR_PIN 20 // 48 +#define Z80_RD_PIN 5 // 55 #define Z80_IORQ_PIN 8 #define Z80_MREQ_PIN 7 #define Z80_A0_PIN 15 @@ -222,13 +217,13 @@ #define Z80_A9_PIN 36 #define Z80_A10_PIN 37 #define Z80_A11_PIN 38 -#define Z80_A12_PIN 3 -#define Z80_A13_PIN 4 -#define Z80_A14_PIN 26 -#define Z80_A15_PIN 27 -#define Z80_A16_PIN 33 -#define Z80_A17_PIN 34 -#define Z80_A18_PIN 24 +#define Z80_A12_PIN 64 // 3 +#define Z80_A13_PIN 65 // 4 +#define Z80_A14_PIN 66 // 26 +#define Z80_A15_PIN 67 // 27 +#define Z80_A16_PIN 68 // 33 +#define Z80_A17_PIN 69 // 34 +#define Z80_A18_PIN 70 // 24 #define Z80_D0_PIN 0 #define Z80_D1_PIN 1 #define Z80_D2_PIN 29 @@ -237,22 +232,21 @@ #define Z80_D5_PIN 46 #define Z80_D6_PIN 44 #define Z80_D7_PIN 45 -#define Z80_WAIT_PIN 54 -#define Z80_BUSACK_PIN 5 +#define Z80_WAIT_PIN 31 // 54 +#define Z80_BUSACK_PIN 24 // 5 #define Z80_NMI_PIN 39 #define Z80_INT_PIN 28 #define Z80_RESET_PIN 6 #define SYSCLK_PIN 25 -#define CTL_RFSH_PIN 53 -#define CTL_HALT_PIN 51 -#define CTL_M1_PIN 20 +#define CTL_RFSH_PIN 4 // 53 +#define CTL_HALT_PIN 26 // 51 +#define CTL_M1_PIN 3 // 20 #define CTL_BUSRQ_PIN 2 #define CTL_BUSACK_PIN 21 #define CTL_CLK_PIN 14 -#define CTL_CLKSLCT_PIN 47 +#define CTL_CLKSLCT_PIN 32 // 47 #define TZ_BUSACK_PIN 52 -#define TZ_SVCREQ_PIN 56 -#define TZ_SYSREQ_PIN 57 +#define TZ_SVCREQ_PIN 33 // 56 // IRQ mask values for the different types of IRQ trigger. // @@ -294,13 +288,13 @@ #define pinIndex(a) getPinIndex(pinMap[a]) #define setZ80Data(a) { GPIOB_PDOR = (GPIOB_PDOR & 0xff00ffff) | ((a << 16) & 0x00ff0000); } -#define setZ80Addr(a) { GPIOA_PDOR = (GPIOA_PDOR & 0xffff0fff) | (a & 0x00000f000); GPIOC_PDOR = (GPIOC_PDOR & 0xfffff000) | (a & 0x00000fff); } +#define setZ80Addr(a) { GPIOC_PDOR = (GPIOC_PDOR & 0xffff0000) | (a & 0x0000ffff); } #define setZ80AddrLower(a) { GPIOC_PDOR = (GPIOC_PDOR & 0xffffff00) | (a & 0x000000ff); } #define setZ80RefreshAddr(a) { GPIOC_PDOR = (GPIOC_PDOR & 0xffffff80) | (a & 0x0000007f); } #define readZ80AddrLower() ( GPIOC_PDIR & 0x000000ff ) -#define readZ80Addr() ( (GPIOA_PDIR & 0x00000f000) | (GPIOC_PDIR & 0x00000fff) ) +#define readZ80Addr() ( (GPIOC_PDIR & 0x0000ffff) ) #define readZ80DataBus() ( (GPIOB_PDIR >> 16) & 0x000000ff ) -#define readCtrlLatch() ( GPIOB_PDIR & 0x0000003f ) +#define readCtrlLatch() ( ((GPIOB_PDIR & 0x00000200) >> 5) | (GPIOB_PDIR & 0x0000000f) ) #define writeCtrlLatch(a) { writeZ80IO(IO_TZ_CTRLLATCH, a); } #define setZ80Direction(a) { for(uint8_t idx=Z80_D0; idx <= Z80_D7; idx++) { if(a == WRITE) { pinOutput(idx); } else { pinInput(idx); } }; z80Control.busDir = a; } #define reqZ80BusChange(a) { if(a == MAINBOARD_ACCESS && z80Control.ctrlMode == TRANZPUTER_ACCESS) \ @@ -366,30 +360,28 @@ enum pinIdxToPinNumMap { Z80_MEM2 = 29, Z80_MEM3 = 30, Z80_MEM4 = 31, - ENIOWAIT = 32, - Z80_IORQ = 33, - Z80_MREQ = 34, - Z80_RD = 35, - Z80_WR = 36, - Z80_WAIT = 37, - Z80_BUSACK = 38, + Z80_IORQ = 32, + Z80_MREQ = 33, + Z80_RD = 34, + Z80_WR = 35, + Z80_WAIT = 36, + Z80_BUSACK = 37, - Z80_NMI = 39, - Z80_INT = 40, - Z80_RESET = 41, - MB_SYSCLK = 42, - TZ_BUSACK = 43, - TZ_SVCREQ = 44, - TZ_SYSREQ = 45, + Z80_NMI = 38, + Z80_INT = 39, + Z80_RESET = 40, + MB_SYSCLK = 41, + TZ_BUSACK = 42, + TZ_SVCREQ = 43, - CTL_BUSACK = 46, - CTL_BUSRQ = 47, - CTL_RFSH = 48, - CTL_HALT = 49, - CTL_M1 = 50, - CTL_CLK = 51, - CTL_CLKSLCT = 52 + CTL_BUSACK = 44, + CTL_BUSRQ = 45, + CTL_RFSH = 46, + CTL_HALT = 47, + CTL_M1 = 48, + CTL_CLK = 49, + CTL_CLKSLCT = 50 }; // Possible control modes that the K64F can be in, do nothing where the Z80 runs normally, control the Z80 and mainboard, or control the Z80 and tranZPUter. diff --git a/libraries/lib/libimath2-k64f.a b/libraries/lib/libimath2-k64f.a index c9cec1c9fdffbe4c0efd61b6f12e9816af43f15e..2033885a9f0fec6268c4feba0ddbd77a726f78f6 100644 GIT binary patch delta 71 zcmcbScq4Iw44aXefrW|LM5Q_?Yw|it@r`?D^Fg_r>}!OM*@_fB&4{7F)Tt4Xq$Wb@=vqhvM7YLYB0F)J)A40myB@-MSe zQ~n$|H486NdMsw1^=X~)CXZ*q$t}1NnZ1r{+`#+!a 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zt}ivX{PhWuD8^P03Hha(vYl?x)Ed3#07!RICF3vbUMJs#Vm}skgY^{yFlG)=b?1%T zkN*t%mD1C7UdNxBBL>3q&>%7kz2<4z(1u(wmTktuM6VwzRpy7GP{pH+G^N+#Zwoxt o%u_F8o;oD+R39@>Q2}TyPk4WG6^BJ2{^I4KpS3Qz&0lK%55xwCJOBUy diff --git a/teensy3/core_pins.h b/teensy3/core_pins.h index 7f5714b..92318b6 100644 --- a/teensy3/core_pins.h +++ b/teensy3/core_pins.h @@ -1,6 +1,7 @@ /* Teensyduino Core Library * http://www.pjrc.com/teensy/ * Copyright (c) 2017 PJRC.COM, LLC. + * Copyright (c) 2020 P. D. Smart, tranZPUter SW updates. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the @@ -34,66 +35,66 @@ #include "kinetis.h" #include "pins_arduino.h" -#define HIGH 1 -#define LOW 0 -#define INPUT 0 -#define OUTPUT 1 -#define INPUT_PULLUP 2 +#define HIGH 1 +#define LOW 0 +#define INPUT 0 +#define OUTPUT 1 +#define INPUT_PULLUP 2 #define INPUT_PULLDOWN 3 #define OUTPUT_OPENDRAIN 4 #define INPUT_DISABLE 5 -#define LSBFIRST 0 -#define MSBFIRST 1 -#define _BV(n) (1<<(n)) -#define CHANGE 4 -#define FALLING 2 -#define RISING 3 +#define LSBFIRST 0 +#define MSBFIRST 1 +#define _BV(n) (1<<(n)) +#define CHANGE 4 +#define FALLING 2 +#define RISING 3 -// Pin Arduino -// 0 B16 RXD -// 1 B17 TXD -// 2 D0 -// 3 A12 FTM1_CH0 -// 4 A13 FTM1_CH1 -// 5 D7 FTM0_CH7 OC0B/T1 -// 6 D4 FTM0_CH4 OC0A -// 7 D2 -// 8 D3 ICP1 -// 9 C3 FTM0_CH2 OC1A -// 10 C4 FTM0_CH3 SS/OC1B -// 11 C6 MOSI/OC2A -// 12 C7 MISO -// 13 C5 SCK -// 14 D1 -// 15 C0 -// 16 B0 (FTM1_CH0) -// 17 B1 (FTM1_CH1) -// 18 B3 SDA -// 19 B2 SCL -// 20 D5 FTM0_CH5 -// 21 D6 FTM0_CH6 -// 22 C1 FTM0_CH0 -// 23 C2 FTM0_CH1 -// 24 A5 (FTM0_CH2) -// 25 B19 -// 26 E1 -// 27 C9 -// 28 C8 -// 29 C10 -// 30 C11 -// 31 E0 -// 32 B18 -// 33 A4 (FTM0_CH1) -// (34) analog only -// (35) analog only -// (36) analog only -// (37) analog only +// Pin Arduino +// 0 B16 RXD +// 1 B17 TXD +// 2 D0 +// 3 A12 FTM1_CH0 +// 4 A13 FTM1_CH1 +// 5 D7 FTM0_CH7 OC0B/T1 +// 6 D4 FTM0_CH4 OC0A +// 7 D2 +// 8 D3 ICP1 +// 9 C3 FTM0_CH2 OC1A +// 10 C4 FTM0_CH3 SS/OC1B +// 11 C6 MOSI/OC2A +// 12 C7 MISO +// 13 C5 SCK +// 14 D1 +// 15 C0 +// 16 B0 (FTM1_CH0) +// 17 B1 (FTM1_CH1) +// 18 B3 SDA +// 19 B2 SCL +// 20 D5 FTM0_CH5 +// 21 D6 FTM0_CH6 +// 22 C1 FTM0_CH0 +// 23 C2 FTM0_CH1 +// 24 A5 (FTM0_CH2) +// 25 B19 +// 26 E1 +// 27 C9 +// 28 C8 +// 29 C10 +// 30 C11 +// 31 E0 +// 32 B18 +// 33 A4 (FTM0_CH1) +// (34) analog only +// (35) analog only +// (36) analog only +// (37) analog only // not available to user: -// A0 FTM0_CH5 SWD Clock -// A1 FTM0_CH6 USB ID -// A2 FTM0_CH7 SWD Trace -// A3 FTM0_CH0 SWD Data +// A0 FTM0_CH5 SWD Clock +// A1 FTM0_CH6 USB ID +// A2 FTM0_CH7 SWD Trace +// A3 FTM0_CH0 SWD Data #if defined(__MK20DX128__) #define CORE_NUM_TOTAL_PINS 34 @@ -152,1322 +153,1405 @@ #if defined(__MK20DX128__) || defined(__MK20DX256__) -#define CORE_PIN0_BIT 16 -#define CORE_PIN1_BIT 17 -#define CORE_PIN2_BIT 0 -#define CORE_PIN3_BIT 12 -#define CORE_PIN4_BIT 13 -#define CORE_PIN5_BIT 7 -#define CORE_PIN6_BIT 4 -#define CORE_PIN7_BIT 2 -#define CORE_PIN8_BIT 3 -#define CORE_PIN9_BIT 3 -#define CORE_PIN10_BIT 4 -#define CORE_PIN11_BIT 6 -#define CORE_PIN12_BIT 7 -#define CORE_PIN13_BIT 5 -#define CORE_PIN14_BIT 1 -#define CORE_PIN15_BIT 0 -#define CORE_PIN16_BIT 0 -#define CORE_PIN17_BIT 1 -#define CORE_PIN18_BIT 3 -#define CORE_PIN19_BIT 2 -#define CORE_PIN20_BIT 5 -#define CORE_PIN21_BIT 6 -#define CORE_PIN22_BIT 1 -#define CORE_PIN23_BIT 2 -#define CORE_PIN24_BIT 5 -#define CORE_PIN25_BIT 19 -#define CORE_PIN26_BIT 1 -#define CORE_PIN27_BIT 9 -#define CORE_PIN28_BIT 8 -#define CORE_PIN29_BIT 10 -#define CORE_PIN30_BIT 11 -#define CORE_PIN31_BIT 0 -#define CORE_PIN32_BIT 18 -#define CORE_PIN33_BIT 4 +#define CORE_PIN0_BIT 16 +#define CORE_PIN1_BIT 17 +#define CORE_PIN2_BIT 0 +#define CORE_PIN3_BIT 12 +#define CORE_PIN4_BIT 13 +#define CORE_PIN5_BIT 7 +#define CORE_PIN6_BIT 4 +#define CORE_PIN7_BIT 2 +#define CORE_PIN8_BIT 3 +#define CORE_PIN9_BIT 3 +#define CORE_PIN10_BIT 4 +#define CORE_PIN11_BIT 6 +#define CORE_PIN12_BIT 7 +#define CORE_PIN13_BIT 5 +#define CORE_PIN14_BIT 1 +#define CORE_PIN15_BIT 0 +#define CORE_PIN16_BIT 0 +#define CORE_PIN17_BIT 1 +#define CORE_PIN18_BIT 3 +#define CORE_PIN19_BIT 2 +#define CORE_PIN20_BIT 5 +#define CORE_PIN21_BIT 6 +#define CORE_PIN22_BIT 1 +#define CORE_PIN23_BIT 2 +#define CORE_PIN24_BIT 5 +#define CORE_PIN25_BIT 19 +#define CORE_PIN26_BIT 1 +#define CORE_PIN27_BIT 9 +#define CORE_PIN28_BIT 8 +#define CORE_PIN29_BIT 10 +#define CORE_PIN30_BIT 11 +#define CORE_PIN31_BIT 0 +#define CORE_PIN32_BIT 18 +#define CORE_PIN33_BIT 4 -#define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT)) -#define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT)) -#define CORE_PIN2_BITMASK (1<<(CORE_PIN2_BIT)) -#define CORE_PIN3_BITMASK (1<<(CORE_PIN3_BIT)) -#define CORE_PIN4_BITMASK (1<<(CORE_PIN4_BIT)) -#define CORE_PIN5_BITMASK (1<<(CORE_PIN5_BIT)) -#define CORE_PIN6_BITMASK (1<<(CORE_PIN6_BIT)) -#define CORE_PIN7_BITMASK (1<<(CORE_PIN7_BIT)) -#define CORE_PIN8_BITMASK (1<<(CORE_PIN8_BIT)) -#define CORE_PIN9_BITMASK (1<<(CORE_PIN9_BIT)) -#define CORE_PIN10_BITMASK (1<<(CORE_PIN10_BIT)) -#define CORE_PIN11_BITMASK (1<<(CORE_PIN11_BIT)) -#define CORE_PIN12_BITMASK (1<<(CORE_PIN12_BIT)) -#define CORE_PIN13_BITMASK (1<<(CORE_PIN13_BIT)) -#define CORE_PIN14_BITMASK (1<<(CORE_PIN14_BIT)) -#define CORE_PIN15_BITMASK (1<<(CORE_PIN15_BIT)) -#define CORE_PIN16_BITMASK (1<<(CORE_PIN16_BIT)) -#define CORE_PIN17_BITMASK (1<<(CORE_PIN17_BIT)) -#define CORE_PIN18_BITMASK (1<<(CORE_PIN18_BIT)) -#define CORE_PIN19_BITMASK (1<<(CORE_PIN19_BIT)) -#define CORE_PIN20_BITMASK (1<<(CORE_PIN20_BIT)) -#define CORE_PIN21_BITMASK (1<<(CORE_PIN21_BIT)) -#define CORE_PIN22_BITMASK (1<<(CORE_PIN22_BIT)) -#define CORE_PIN23_BITMASK (1<<(CORE_PIN23_BIT)) -#define CORE_PIN24_BITMASK (1<<(CORE_PIN24_BIT)) -#define CORE_PIN25_BITMASK (1<<(CORE_PIN25_BIT)) -#define CORE_PIN26_BITMASK (1<<(CORE_PIN26_BIT)) -#define CORE_PIN27_BITMASK (1<<(CORE_PIN27_BIT)) -#define CORE_PIN28_BITMASK (1<<(CORE_PIN28_BIT)) -#define CORE_PIN29_BITMASK (1<<(CORE_PIN29_BIT)) -#define CORE_PIN30_BITMASK (1<<(CORE_PIN30_BIT)) -#define CORE_PIN31_BITMASK (1<<(CORE_PIN31_BIT)) -#define CORE_PIN32_BITMASK (1<<(CORE_PIN32_BIT)) -#define CORE_PIN33_BITMASK (1<<(CORE_PIN33_BIT)) +#define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT)) +#define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT)) +#define CORE_PIN2_BITMASK (1<<(CORE_PIN2_BIT)) +#define CORE_PIN3_BITMASK (1<<(CORE_PIN3_BIT)) +#define CORE_PIN4_BITMASK (1<<(CORE_PIN4_BIT)) +#define CORE_PIN5_BITMASK (1<<(CORE_PIN5_BIT)) +#define CORE_PIN6_BITMASK (1<<(CORE_PIN6_BIT)) +#define CORE_PIN7_BITMASK (1<<(CORE_PIN7_BIT)) +#define CORE_PIN8_BITMASK (1<<(CORE_PIN8_BIT)) +#define CORE_PIN9_BITMASK (1<<(CORE_PIN9_BIT)) +#define CORE_PIN10_BITMASK (1<<(CORE_PIN10_BIT)) +#define CORE_PIN11_BITMASK (1<<(CORE_PIN11_BIT)) +#define CORE_PIN12_BITMASK (1<<(CORE_PIN12_BIT)) +#define CORE_PIN13_BITMASK (1<<(CORE_PIN13_BIT)) +#define CORE_PIN14_BITMASK (1<<(CORE_PIN14_BIT)) +#define CORE_PIN15_BITMASK (1<<(CORE_PIN15_BIT)) +#define CORE_PIN16_BITMASK (1<<(CORE_PIN16_BIT)) +#define CORE_PIN17_BITMASK (1<<(CORE_PIN17_BIT)) +#define CORE_PIN18_BITMASK (1<<(CORE_PIN18_BIT)) +#define CORE_PIN19_BITMASK (1<<(CORE_PIN19_BIT)) +#define CORE_PIN20_BITMASK (1<<(CORE_PIN20_BIT)) +#define CORE_PIN21_BITMASK (1<<(CORE_PIN21_BIT)) +#define CORE_PIN22_BITMASK (1<<(CORE_PIN22_BIT)) +#define CORE_PIN23_BITMASK (1<<(CORE_PIN23_BIT)) +#define CORE_PIN24_BITMASK (1<<(CORE_PIN24_BIT)) +#define CORE_PIN25_BITMASK (1<<(CORE_PIN25_BIT)) +#define CORE_PIN26_BITMASK (1<<(CORE_PIN26_BIT)) +#define CORE_PIN27_BITMASK (1<<(CORE_PIN27_BIT)) +#define CORE_PIN28_BITMASK (1<<(CORE_PIN28_BIT)) +#define CORE_PIN29_BITMASK (1<<(CORE_PIN29_BIT)) +#define CORE_PIN30_BITMASK (1<<(CORE_PIN30_BIT)) +#define CORE_PIN31_BITMASK (1<<(CORE_PIN31_BIT)) +#define CORE_PIN32_BITMASK (1<<(CORE_PIN32_BIT)) +#define CORE_PIN33_BITMASK (1<<(CORE_PIN33_BIT)) -#define CORE_PIN0_PORTREG GPIOB_PDOR -#define CORE_PIN1_PORTREG GPIOB_PDOR -#define CORE_PIN2_PORTREG GPIOD_PDOR -#define CORE_PIN3_PORTREG GPIOA_PDOR -#define CORE_PIN4_PORTREG GPIOA_PDOR -#define CORE_PIN5_PORTREG GPIOD_PDOR -#define CORE_PIN6_PORTREG GPIOD_PDOR -#define CORE_PIN7_PORTREG GPIOD_PDOR -#define CORE_PIN8_PORTREG GPIOD_PDOR -#define CORE_PIN9_PORTREG GPIOC_PDOR -#define CORE_PIN10_PORTREG GPIOC_PDOR -#define CORE_PIN11_PORTREG GPIOC_PDOR -#define CORE_PIN12_PORTREG GPIOC_PDOR -#define CORE_PIN13_PORTREG GPIOC_PDOR -#define CORE_PIN14_PORTREG GPIOD_PDOR -#define CORE_PIN15_PORTREG GPIOC_PDOR -#define CORE_PIN16_PORTREG GPIOB_PDOR -#define CORE_PIN17_PORTREG GPIOB_PDOR -#define CORE_PIN18_PORTREG GPIOB_PDOR -#define CORE_PIN19_PORTREG GPIOB_PDOR -#define CORE_PIN20_PORTREG GPIOD_PDOR -#define CORE_PIN21_PORTREG GPIOD_PDOR -#define CORE_PIN22_PORTREG GPIOC_PDOR -#define CORE_PIN23_PORTREG GPIOC_PDOR -#define CORE_PIN24_PORTREG GPIOA_PDOR -#define CORE_PIN25_PORTREG GPIOB_PDOR -#define CORE_PIN26_PORTREG GPIOE_PDOR -#define CORE_PIN27_PORTREG GPIOC_PDOR -#define CORE_PIN28_PORTREG GPIOC_PDOR -#define CORE_PIN29_PORTREG GPIOC_PDOR -#define CORE_PIN30_PORTREG GPIOC_PDOR -#define CORE_PIN31_PORTREG GPIOE_PDOR -#define CORE_PIN32_PORTREG GPIOB_PDOR -#define CORE_PIN33_PORTREG GPIOA_PDOR +#define CORE_PIN0_PORTREG GPIOB_PDOR +#define CORE_PIN1_PORTREG GPIOB_PDOR +#define CORE_PIN2_PORTREG GPIOD_PDOR +#define CORE_PIN3_PORTREG GPIOA_PDOR +#define CORE_PIN4_PORTREG GPIOA_PDOR +#define CORE_PIN5_PORTREG GPIOD_PDOR +#define CORE_PIN6_PORTREG GPIOD_PDOR +#define CORE_PIN7_PORTREG GPIOD_PDOR +#define CORE_PIN8_PORTREG GPIOD_PDOR +#define CORE_PIN9_PORTREG GPIOC_PDOR +#define CORE_PIN10_PORTREG GPIOC_PDOR +#define CORE_PIN11_PORTREG GPIOC_PDOR +#define CORE_PIN12_PORTREG GPIOC_PDOR +#define CORE_PIN13_PORTREG GPIOC_PDOR +#define CORE_PIN14_PORTREG GPIOD_PDOR +#define CORE_PIN15_PORTREG GPIOC_PDOR +#define CORE_PIN16_PORTREG GPIOB_PDOR +#define CORE_PIN17_PORTREG GPIOB_PDOR +#define CORE_PIN18_PORTREG GPIOB_PDOR +#define CORE_PIN19_PORTREG GPIOB_PDOR +#define CORE_PIN20_PORTREG GPIOD_PDOR +#define CORE_PIN21_PORTREG GPIOD_PDOR +#define CORE_PIN22_PORTREG GPIOC_PDOR +#define CORE_PIN23_PORTREG GPIOC_PDOR +#define CORE_PIN24_PORTREG GPIOA_PDOR +#define CORE_PIN25_PORTREG GPIOB_PDOR +#define CORE_PIN26_PORTREG GPIOE_PDOR +#define CORE_PIN27_PORTREG GPIOC_PDOR +#define CORE_PIN28_PORTREG GPIOC_PDOR +#define CORE_PIN29_PORTREG GPIOC_PDOR +#define CORE_PIN30_PORTREG GPIOC_PDOR +#define CORE_PIN31_PORTREG GPIOE_PDOR +#define CORE_PIN32_PORTREG GPIOB_PDOR +#define CORE_PIN33_PORTREG GPIOA_PDOR -#define CORE_PIN0_PORTSET GPIOB_PSOR -#define CORE_PIN1_PORTSET GPIOB_PSOR -#define CORE_PIN2_PORTSET GPIOD_PSOR -#define CORE_PIN3_PORTSET GPIOA_PSOR -#define CORE_PIN4_PORTSET GPIOA_PSOR -#define CORE_PIN5_PORTSET GPIOD_PSOR -#define CORE_PIN6_PORTSET GPIOD_PSOR -#define CORE_PIN7_PORTSET GPIOD_PSOR -#define CORE_PIN8_PORTSET GPIOD_PSOR -#define CORE_PIN9_PORTSET GPIOC_PSOR -#define CORE_PIN10_PORTSET GPIOC_PSOR -#define CORE_PIN11_PORTSET GPIOC_PSOR -#define CORE_PIN12_PORTSET GPIOC_PSOR -#define CORE_PIN13_PORTSET GPIOC_PSOR -#define CORE_PIN14_PORTSET GPIOD_PSOR -#define CORE_PIN15_PORTSET GPIOC_PSOR -#define CORE_PIN16_PORTSET GPIOB_PSOR -#define CORE_PIN17_PORTSET GPIOB_PSOR -#define CORE_PIN18_PORTSET GPIOB_PSOR -#define CORE_PIN19_PORTSET GPIOB_PSOR -#define CORE_PIN20_PORTSET GPIOD_PSOR -#define CORE_PIN21_PORTSET GPIOD_PSOR -#define CORE_PIN22_PORTSET GPIOC_PSOR -#define CORE_PIN23_PORTSET GPIOC_PSOR -#define CORE_PIN24_PORTSET GPIOA_PSOR -#define CORE_PIN25_PORTSET GPIOB_PSOR -#define CORE_PIN26_PORTSET GPIOE_PSOR -#define CORE_PIN27_PORTSET GPIOC_PSOR -#define CORE_PIN28_PORTSET GPIOC_PSOR -#define CORE_PIN29_PORTSET GPIOC_PSOR -#define CORE_PIN30_PORTSET GPIOC_PSOR -#define CORE_PIN31_PORTSET GPIOE_PSOR -#define CORE_PIN32_PORTSET GPIOB_PSOR -#define CORE_PIN33_PORTSET GPIOA_PSOR +#define CORE_PIN0_PORTSET GPIOB_PSOR +#define CORE_PIN1_PORTSET GPIOB_PSOR +#define CORE_PIN2_PORTSET GPIOD_PSOR +#define CORE_PIN3_PORTSET GPIOA_PSOR +#define CORE_PIN4_PORTSET GPIOA_PSOR +#define CORE_PIN5_PORTSET GPIOD_PSOR +#define CORE_PIN6_PORTSET GPIOD_PSOR +#define CORE_PIN7_PORTSET GPIOD_PSOR +#define CORE_PIN8_PORTSET GPIOD_PSOR +#define CORE_PIN9_PORTSET GPIOC_PSOR +#define CORE_PIN10_PORTSET GPIOC_PSOR +#define CORE_PIN11_PORTSET GPIOC_PSOR +#define CORE_PIN12_PORTSET GPIOC_PSOR +#define CORE_PIN13_PORTSET GPIOC_PSOR +#define CORE_PIN14_PORTSET GPIOD_PSOR +#define CORE_PIN15_PORTSET GPIOC_PSOR +#define CORE_PIN16_PORTSET GPIOB_PSOR +#define CORE_PIN17_PORTSET GPIOB_PSOR +#define CORE_PIN18_PORTSET GPIOB_PSOR +#define CORE_PIN19_PORTSET GPIOB_PSOR +#define CORE_PIN20_PORTSET GPIOD_PSOR +#define CORE_PIN21_PORTSET GPIOD_PSOR +#define CORE_PIN22_PORTSET GPIOC_PSOR +#define CORE_PIN23_PORTSET GPIOC_PSOR +#define CORE_PIN24_PORTSET GPIOA_PSOR +#define CORE_PIN25_PORTSET GPIOB_PSOR +#define CORE_PIN26_PORTSET GPIOE_PSOR +#define CORE_PIN27_PORTSET GPIOC_PSOR +#define CORE_PIN28_PORTSET GPIOC_PSOR +#define CORE_PIN29_PORTSET GPIOC_PSOR +#define CORE_PIN30_PORTSET GPIOC_PSOR +#define CORE_PIN31_PORTSET GPIOE_PSOR +#define CORE_PIN32_PORTSET GPIOB_PSOR +#define CORE_PIN33_PORTSET GPIOA_PSOR -#define CORE_PIN0_PORTCLEAR GPIOB_PCOR -#define CORE_PIN1_PORTCLEAR GPIOB_PCOR -#define CORE_PIN2_PORTCLEAR GPIOD_PCOR -#define CORE_PIN3_PORTCLEAR GPIOA_PCOR -#define CORE_PIN4_PORTCLEAR GPIOA_PCOR -#define CORE_PIN5_PORTCLEAR GPIOD_PCOR -#define CORE_PIN6_PORTCLEAR GPIOD_PCOR -#define CORE_PIN7_PORTCLEAR GPIOD_PCOR -#define CORE_PIN8_PORTCLEAR GPIOD_PCOR -#define CORE_PIN9_PORTCLEAR GPIOC_PCOR -#define CORE_PIN10_PORTCLEAR GPIOC_PCOR -#define CORE_PIN11_PORTCLEAR GPIOC_PCOR -#define CORE_PIN12_PORTCLEAR GPIOC_PCOR -#define CORE_PIN13_PORTCLEAR GPIOC_PCOR -#define CORE_PIN14_PORTCLEAR GPIOD_PCOR -#define CORE_PIN15_PORTCLEAR GPIOC_PCOR -#define CORE_PIN16_PORTCLEAR GPIOB_PCOR -#define CORE_PIN17_PORTCLEAR GPIOB_PCOR -#define CORE_PIN18_PORTCLEAR GPIOB_PCOR -#define CORE_PIN19_PORTCLEAR GPIOB_PCOR -#define CORE_PIN20_PORTCLEAR GPIOD_PCOR -#define CORE_PIN21_PORTCLEAR GPIOD_PCOR -#define CORE_PIN22_PORTCLEAR GPIOC_PCOR -#define CORE_PIN23_PORTCLEAR GPIOC_PCOR -#define CORE_PIN24_PORTCLEAR GPIOA_PCOR -#define CORE_PIN25_PORTCLEAR GPIOB_PCOR -#define CORE_PIN26_PORTCLEAR GPIOE_PCOR -#define CORE_PIN27_PORTCLEAR GPIOC_PCOR -#define CORE_PIN28_PORTCLEAR GPIOC_PCOR -#define CORE_PIN29_PORTCLEAR GPIOC_PCOR -#define CORE_PIN30_PORTCLEAR GPIOC_PCOR -#define CORE_PIN31_PORTCLEAR GPIOE_PCOR -#define CORE_PIN32_PORTCLEAR GPIOB_PCOR -#define CORE_PIN33_PORTCLEAR GPIOA_PCOR +#define CORE_PIN0_PORTCLEAR GPIOB_PCOR +#define CORE_PIN1_PORTCLEAR GPIOB_PCOR +#define CORE_PIN2_PORTCLEAR GPIOD_PCOR +#define CORE_PIN3_PORTCLEAR GPIOA_PCOR +#define CORE_PIN4_PORTCLEAR GPIOA_PCOR +#define CORE_PIN5_PORTCLEAR GPIOD_PCOR +#define CORE_PIN6_PORTCLEAR GPIOD_PCOR +#define CORE_PIN7_PORTCLEAR GPIOD_PCOR +#define CORE_PIN8_PORTCLEAR GPIOD_PCOR +#define CORE_PIN9_PORTCLEAR GPIOC_PCOR +#define CORE_PIN10_PORTCLEAR GPIOC_PCOR +#define CORE_PIN11_PORTCLEAR GPIOC_PCOR +#define CORE_PIN12_PORTCLEAR GPIOC_PCOR +#define CORE_PIN13_PORTCLEAR GPIOC_PCOR +#define CORE_PIN14_PORTCLEAR GPIOD_PCOR +#define CORE_PIN15_PORTCLEAR GPIOC_PCOR +#define CORE_PIN16_PORTCLEAR GPIOB_PCOR +#define CORE_PIN17_PORTCLEAR GPIOB_PCOR +#define CORE_PIN18_PORTCLEAR GPIOB_PCOR +#define CORE_PIN19_PORTCLEAR GPIOB_PCOR +#define CORE_PIN20_PORTCLEAR GPIOD_PCOR +#define CORE_PIN21_PORTCLEAR GPIOD_PCOR +#define CORE_PIN22_PORTCLEAR GPIOC_PCOR +#define CORE_PIN23_PORTCLEAR GPIOC_PCOR +#define CORE_PIN24_PORTCLEAR GPIOA_PCOR +#define CORE_PIN25_PORTCLEAR GPIOB_PCOR +#define CORE_PIN26_PORTCLEAR GPIOE_PCOR +#define CORE_PIN27_PORTCLEAR GPIOC_PCOR +#define CORE_PIN28_PORTCLEAR GPIOC_PCOR +#define CORE_PIN29_PORTCLEAR GPIOC_PCOR +#define CORE_PIN30_PORTCLEAR GPIOC_PCOR +#define CORE_PIN31_PORTCLEAR GPIOE_PCOR +#define CORE_PIN32_PORTCLEAR GPIOB_PCOR +#define CORE_PIN33_PORTCLEAR GPIOA_PCOR -#define CORE_PIN0_DDRREG GPIOB_PDDR -#define CORE_PIN1_DDRREG GPIOB_PDDR -#define CORE_PIN2_DDRREG GPIOD_PDDR -#define CORE_PIN3_DDRREG GPIOA_PDDR -#define CORE_PIN4_DDRREG GPIOA_PDDR -#define CORE_PIN5_DDRREG GPIOD_PDDR -#define CORE_PIN6_DDRREG GPIOD_PDDR -#define CORE_PIN7_DDRREG GPIOD_PDDR -#define CORE_PIN8_DDRREG GPIOD_PDDR -#define CORE_PIN9_DDRREG GPIOC_PDDR -#define CORE_PIN10_DDRREG GPIOC_PDDR -#define CORE_PIN11_DDRREG GPIOC_PDDR -#define CORE_PIN12_DDRREG GPIOC_PDDR -#define CORE_PIN13_DDRREG GPIOC_PDDR -#define CORE_PIN14_DDRREG GPIOD_PDDR -#define CORE_PIN15_DDRREG GPIOC_PDDR -#define CORE_PIN16_DDRREG GPIOB_PDDR -#define CORE_PIN17_DDRREG GPIOB_PDDR -#define CORE_PIN18_DDRREG GPIOB_PDDR -#define CORE_PIN19_DDRREG GPIOB_PDDR -#define CORE_PIN20_DDRREG GPIOD_PDDR -#define CORE_PIN21_DDRREG GPIOD_PDDR -#define CORE_PIN22_DDRREG GPIOC_PDDR -#define CORE_PIN23_DDRREG GPIOC_PDDR -#define CORE_PIN24_DDRREG GPIOA_PDDR -#define CORE_PIN25_DDRREG GPIOB_PDDR -#define CORE_PIN26_DDRREG GPIOE_PDDR -#define CORE_PIN27_DDRREG GPIOC_PDDR -#define CORE_PIN28_DDRREG GPIOC_PDDR -#define CORE_PIN29_DDRREG GPIOC_PDDR -#define CORE_PIN30_DDRREG GPIOC_PDDR -#define CORE_PIN31_DDRREG GPIOE_PDDR -#define CORE_PIN32_DDRREG GPIOB_PDDR -#define CORE_PIN33_DDRREG GPIOA_PDDR +#define CORE_PIN0_DDRREG GPIOB_PDDR +#define CORE_PIN1_DDRREG GPIOB_PDDR +#define CORE_PIN2_DDRREG GPIOD_PDDR +#define CORE_PIN3_DDRREG GPIOA_PDDR +#define CORE_PIN4_DDRREG GPIOA_PDDR +#define CORE_PIN5_DDRREG GPIOD_PDDR +#define CORE_PIN6_DDRREG GPIOD_PDDR +#define CORE_PIN7_DDRREG GPIOD_PDDR +#define CORE_PIN8_DDRREG GPIOD_PDDR +#define CORE_PIN9_DDRREG GPIOC_PDDR +#define CORE_PIN10_DDRREG GPIOC_PDDR +#define CORE_PIN11_DDRREG GPIOC_PDDR +#define CORE_PIN12_DDRREG GPIOC_PDDR +#define CORE_PIN13_DDRREG GPIOC_PDDR +#define CORE_PIN14_DDRREG GPIOD_PDDR +#define CORE_PIN15_DDRREG GPIOC_PDDR +#define CORE_PIN16_DDRREG GPIOB_PDDR +#define CORE_PIN17_DDRREG GPIOB_PDDR +#define CORE_PIN18_DDRREG GPIOB_PDDR +#define CORE_PIN19_DDRREG GPIOB_PDDR +#define CORE_PIN20_DDRREG GPIOD_PDDR +#define CORE_PIN21_DDRREG GPIOD_PDDR +#define CORE_PIN22_DDRREG GPIOC_PDDR +#define CORE_PIN23_DDRREG GPIOC_PDDR +#define CORE_PIN24_DDRREG GPIOA_PDDR +#define CORE_PIN25_DDRREG GPIOB_PDDR +#define CORE_PIN26_DDRREG GPIOE_PDDR +#define CORE_PIN27_DDRREG GPIOC_PDDR +#define CORE_PIN28_DDRREG GPIOC_PDDR +#define CORE_PIN29_DDRREG GPIOC_PDDR +#define CORE_PIN30_DDRREG GPIOC_PDDR +#define CORE_PIN31_DDRREG GPIOE_PDDR +#define CORE_PIN32_DDRREG GPIOB_PDDR +#define CORE_PIN33_DDRREG GPIOA_PDDR -#define CORE_PIN0_PINREG GPIOB_PDIR -#define CORE_PIN1_PINREG GPIOB_PDIR -#define CORE_PIN2_PINREG GPIOD_PDIR -#define CORE_PIN3_PINREG GPIOA_PDIR -#define CORE_PIN4_PINREG GPIOA_PDIR -#define CORE_PIN5_PINREG GPIOD_PDIR -#define CORE_PIN6_PINREG GPIOD_PDIR -#define CORE_PIN7_PINREG GPIOD_PDIR -#define CORE_PIN8_PINREG GPIOD_PDIR -#define CORE_PIN9_PINREG GPIOC_PDIR -#define CORE_PIN10_PINREG GPIOC_PDIR -#define CORE_PIN11_PINREG GPIOC_PDIR -#define CORE_PIN12_PINREG GPIOC_PDIR -#define CORE_PIN13_PINREG GPIOC_PDIR -#define CORE_PIN14_PINREG GPIOD_PDIR -#define CORE_PIN15_PINREG GPIOC_PDIR -#define CORE_PIN16_PINREG GPIOB_PDIR -#define CORE_PIN17_PINREG GPIOB_PDIR -#define CORE_PIN18_PINREG GPIOB_PDIR -#define CORE_PIN19_PINREG GPIOB_PDIR -#define CORE_PIN20_PINREG GPIOD_PDIR -#define CORE_PIN21_PINREG GPIOD_PDIR -#define CORE_PIN22_PINREG GPIOC_PDIR -#define CORE_PIN23_PINREG GPIOC_PDIR -#define CORE_PIN24_PINREG GPIOA_PDIR -#define CORE_PIN25_PINREG GPIOB_PDIR -#define CORE_PIN26_PINREG GPIOE_PDIR -#define CORE_PIN27_PINREG GPIOC_PDIR -#define CORE_PIN28_PINREG GPIOC_PDIR -#define CORE_PIN29_PINREG GPIOC_PDIR -#define CORE_PIN30_PINREG GPIOC_PDIR -#define CORE_PIN31_PINREG GPIOE_PDIR -#define CORE_PIN32_PINREG GPIOB_PDIR -#define CORE_PIN33_PINREG GPIOA_PDIR +#define CORE_PIN0_PINREG GPIOB_PDIR +#define CORE_PIN1_PINREG GPIOB_PDIR +#define CORE_PIN2_PINREG GPIOD_PDIR +#define CORE_PIN3_PINREG GPIOA_PDIR +#define CORE_PIN4_PINREG GPIOA_PDIR +#define CORE_PIN5_PINREG GPIOD_PDIR +#define CORE_PIN6_PINREG GPIOD_PDIR +#define CORE_PIN7_PINREG GPIOD_PDIR +#define CORE_PIN8_PINREG GPIOD_PDIR +#define CORE_PIN9_PINREG GPIOC_PDIR +#define CORE_PIN10_PINREG GPIOC_PDIR +#define CORE_PIN11_PINREG GPIOC_PDIR +#define CORE_PIN12_PINREG GPIOC_PDIR +#define CORE_PIN13_PINREG GPIOC_PDIR +#define CORE_PIN14_PINREG GPIOD_PDIR +#define CORE_PIN15_PINREG GPIOC_PDIR +#define CORE_PIN16_PINREG GPIOB_PDIR +#define CORE_PIN17_PINREG GPIOB_PDIR +#define CORE_PIN18_PINREG GPIOB_PDIR +#define CORE_PIN19_PINREG GPIOB_PDIR +#define CORE_PIN20_PINREG GPIOD_PDIR +#define CORE_PIN21_PINREG GPIOD_PDIR +#define CORE_PIN22_PINREG GPIOC_PDIR +#define CORE_PIN23_PINREG GPIOC_PDIR +#define CORE_PIN24_PINREG GPIOA_PDIR +#define CORE_PIN25_PINREG GPIOB_PDIR +#define CORE_PIN26_PINREG GPIOE_PDIR +#define CORE_PIN27_PINREG GPIOC_PDIR +#define CORE_PIN28_PINREG GPIOC_PDIR +#define CORE_PIN29_PINREG GPIOC_PDIR +#define CORE_PIN30_PINREG GPIOC_PDIR +#define CORE_PIN31_PINREG GPIOE_PDIR +#define CORE_PIN32_PINREG GPIOB_PDIR +#define CORE_PIN33_PINREG GPIOA_PDIR -#define CORE_PIN0_CONFIG PORTB_PCR16 -#define CORE_PIN1_CONFIG PORTB_PCR17 -#define CORE_PIN2_CONFIG PORTD_PCR0 -#define CORE_PIN3_CONFIG PORTA_PCR12 -#define CORE_PIN4_CONFIG PORTA_PCR13 -#define CORE_PIN5_CONFIG PORTD_PCR7 -#define CORE_PIN6_CONFIG PORTD_PCR4 -#define CORE_PIN7_CONFIG PORTD_PCR2 -#define CORE_PIN8_CONFIG PORTD_PCR3 -#define CORE_PIN9_CONFIG PORTC_PCR3 -#define CORE_PIN10_CONFIG PORTC_PCR4 -#define CORE_PIN11_CONFIG PORTC_PCR6 -#define CORE_PIN12_CONFIG PORTC_PCR7 -#define CORE_PIN13_CONFIG PORTC_PCR5 -#define CORE_PIN14_CONFIG PORTD_PCR1 -#define CORE_PIN15_CONFIG PORTC_PCR0 -#define CORE_PIN16_CONFIG PORTB_PCR0 -#define CORE_PIN17_CONFIG PORTB_PCR1 -#define CORE_PIN18_CONFIG PORTB_PCR3 -#define CORE_PIN19_CONFIG PORTB_PCR2 -#define CORE_PIN20_CONFIG PORTD_PCR5 -#define CORE_PIN21_CONFIG PORTD_PCR6 -#define CORE_PIN22_CONFIG PORTC_PCR1 -#define CORE_PIN23_CONFIG PORTC_PCR2 -#define CORE_PIN24_CONFIG PORTA_PCR5 -#define CORE_PIN25_CONFIG PORTB_PCR19 -#define CORE_PIN26_CONFIG PORTE_PCR1 -#define CORE_PIN27_CONFIG PORTC_PCR9 -#define CORE_PIN28_CONFIG PORTC_PCR8 -#define CORE_PIN29_CONFIG PORTC_PCR10 -#define CORE_PIN30_CONFIG PORTC_PCR11 -#define CORE_PIN31_CONFIG PORTE_PCR0 -#define CORE_PIN32_CONFIG PORTB_PCR18 -#define CORE_PIN33_CONFIG PORTA_PCR4 +#define CORE_PIN0_CONFIG PORTB_PCR16 +#define CORE_PIN1_CONFIG PORTB_PCR17 +#define CORE_PIN2_CONFIG PORTD_PCR0 +#define CORE_PIN3_CONFIG PORTA_PCR12 +#define CORE_PIN4_CONFIG PORTA_PCR13 +#define CORE_PIN5_CONFIG PORTD_PCR7 +#define CORE_PIN6_CONFIG PORTD_PCR4 +#define CORE_PIN7_CONFIG PORTD_PCR2 +#define CORE_PIN8_CONFIG PORTD_PCR3 +#define CORE_PIN9_CONFIG PORTC_PCR3 +#define CORE_PIN10_CONFIG PORTC_PCR4 +#define CORE_PIN11_CONFIG PORTC_PCR6 +#define CORE_PIN12_CONFIG PORTC_PCR7 +#define CORE_PIN13_CONFIG PORTC_PCR5 +#define CORE_PIN14_CONFIG PORTD_PCR1 +#define CORE_PIN15_CONFIG PORTC_PCR0 +#define CORE_PIN16_CONFIG PORTB_PCR0 +#define CORE_PIN17_CONFIG PORTB_PCR1 +#define CORE_PIN18_CONFIG PORTB_PCR3 +#define CORE_PIN19_CONFIG PORTB_PCR2 +#define CORE_PIN20_CONFIG PORTD_PCR5 +#define CORE_PIN21_CONFIG PORTD_PCR6 +#define CORE_PIN22_CONFIG PORTC_PCR1 +#define CORE_PIN23_CONFIG PORTC_PCR2 +#define CORE_PIN24_CONFIG PORTA_PCR5 +#define CORE_PIN25_CONFIG PORTB_PCR19 +#define CORE_PIN26_CONFIG PORTE_PCR1 +#define CORE_PIN27_CONFIG PORTC_PCR9 +#define CORE_PIN28_CONFIG PORTC_PCR8 +#define CORE_PIN29_CONFIG PORTC_PCR10 +#define CORE_PIN30_CONFIG PORTC_PCR11 +#define CORE_PIN31_CONFIG PORTE_PCR0 +#define CORE_PIN32_CONFIG PORTB_PCR18 +#define CORE_PIN33_CONFIG PORTA_PCR4 -#define CORE_ADC0_PIN 14 -#define CORE_ADC1_PIN 15 -#define CORE_ADC2_PIN 16 -#define CORE_ADC3_PIN 17 -#define CORE_ADC4_PIN 18 -#define CORE_ADC5_PIN 19 -#define CORE_ADC6_PIN 20 -#define CORE_ADC7_PIN 21 -#define CORE_ADC8_PIN 22 -#define CORE_ADC9_PIN 23 -#define CORE_ADC10_PIN 34 -#define CORE_ADC11_PIN 35 -#define CORE_ADC12_PIN 36 -#define CORE_ADC13_PIN 37 +#define CORE_ADC0_PIN 14 +#define CORE_ADC1_PIN 15 +#define CORE_ADC2_PIN 16 +#define CORE_ADC3_PIN 17 +#define CORE_ADC4_PIN 18 +#define CORE_ADC5_PIN 19 +#define CORE_ADC6_PIN 20 +#define CORE_ADC7_PIN 21 +#define CORE_ADC8_PIN 22 +#define CORE_ADC9_PIN 23 +#define CORE_ADC10_PIN 34 +#define CORE_ADC11_PIN 35 +#define CORE_ADC12_PIN 36 +#define CORE_ADC13_PIN 37 -#define CORE_RXD0_PIN 0 -#define CORE_TXD0_PIN 1 -#define CORE_RXD1_PIN 9 -#define CORE_TXD1_PIN 10 -#define CORE_RXD2_PIN 7 -#define CORE_TXD2_PIN 8 +#define CORE_RXD0_PIN 0 +#define CORE_TXD0_PIN 1 +#define CORE_RXD1_PIN 9 +#define CORE_TXD1_PIN 10 +#define CORE_RXD2_PIN 7 +#define CORE_TXD2_PIN 8 -#define CORE_INT0_PIN 0 -#define CORE_INT1_PIN 1 -#define CORE_INT2_PIN 2 -#define CORE_INT3_PIN 3 -#define CORE_INT4_PIN 4 -#define CORE_INT5_PIN 5 -#define CORE_INT6_PIN 6 -#define CORE_INT7_PIN 7 -#define CORE_INT8_PIN 8 -#define CORE_INT9_PIN 9 -#define CORE_INT10_PIN 10 -#define CORE_INT11_PIN 11 -#define CORE_INT12_PIN 12 -#define CORE_INT13_PIN 13 -#define CORE_INT14_PIN 14 -#define CORE_INT15_PIN 15 -#define CORE_INT16_PIN 16 -#define CORE_INT17_PIN 17 -#define CORE_INT18_PIN 18 -#define CORE_INT19_PIN 19 -#define CORE_INT20_PIN 20 -#define CORE_INT21_PIN 21 -#define CORE_INT22_PIN 22 -#define CORE_INT23_PIN 23 -#define CORE_INT24_PIN 24 -#define CORE_INT25_PIN 25 -#define CORE_INT26_PIN 26 -#define CORE_INT27_PIN 27 -#define CORE_INT28_PIN 28 -#define CORE_INT29_PIN 29 -#define CORE_INT30_PIN 30 -#define CORE_INT31_PIN 31 -#define CORE_INT32_PIN 32 -#define CORE_INT33_PIN 33 -#define CORE_INT_EVERY_PIN 1 +#define CORE_INT0_PIN 0 +#define CORE_INT1_PIN 1 +#define CORE_INT2_PIN 2 +#define CORE_INT3_PIN 3 +#define CORE_INT4_PIN 4 +#define CORE_INT5_PIN 5 +#define CORE_INT6_PIN 6 +#define CORE_INT7_PIN 7 +#define CORE_INT8_PIN 8 +#define CORE_INT9_PIN 9 +#define CORE_INT10_PIN 10 +#define CORE_INT11_PIN 11 +#define CORE_INT12_PIN 12 +#define CORE_INT13_PIN 13 +#define CORE_INT14_PIN 14 +#define CORE_INT15_PIN 15 +#define CORE_INT16_PIN 16 +#define CORE_INT17_PIN 17 +#define CORE_INT18_PIN 18 +#define CORE_INT19_PIN 19 +#define CORE_INT20_PIN 20 +#define CORE_INT21_PIN 21 +#define CORE_INT22_PIN 22 +#define CORE_INT23_PIN 23 +#define CORE_INT24_PIN 24 +#define CORE_INT25_PIN 25 +#define CORE_INT26_PIN 26 +#define CORE_INT27_PIN 27 +#define CORE_INT28_PIN 28 +#define CORE_INT29_PIN 29 +#define CORE_INT30_PIN 30 +#define CORE_INT31_PIN 31 +#define CORE_INT32_PIN 32 +#define CORE_INT33_PIN 33 +#define CORE_INT_EVERY_PIN 1 #elif defined(__MKL26Z64__) -#define CORE_PIN0_BIT 16 -#define CORE_PIN1_BIT 17 -#define CORE_PIN2_BIT 0 -#define CORE_PIN3_BIT 1 -#define CORE_PIN4_BIT 2 -#define CORE_PIN5_BIT 7 -#define CORE_PIN6_BIT 4 -#define CORE_PIN7_BIT 2 -#define CORE_PIN8_BIT 3 -#define CORE_PIN9_BIT 3 -#define CORE_PIN10_BIT 4 -#define CORE_PIN11_BIT 6 -#define CORE_PIN12_BIT 7 -#define CORE_PIN13_BIT 5 -#define CORE_PIN14_BIT 1 -#define CORE_PIN15_BIT 0 -#define CORE_PIN16_BIT 0 -#define CORE_PIN17_BIT 1 -#define CORE_PIN18_BIT 3 -#define CORE_PIN19_BIT 2 -#define CORE_PIN20_BIT 5 -#define CORE_PIN21_BIT 6 -#define CORE_PIN22_BIT 1 -#define CORE_PIN23_BIT 2 -#define CORE_PIN24_BIT 20 -#define CORE_PIN25_BIT 21 -#define CORE_PIN26_BIT 30 +#define CORE_PIN0_BIT 16 +#define CORE_PIN1_BIT 17 +#define CORE_PIN2_BIT 0 +#define CORE_PIN3_BIT 1 +#define CORE_PIN4_BIT 2 +#define CORE_PIN5_BIT 7 +#define CORE_PIN6_BIT 4 +#define CORE_PIN7_BIT 2 +#define CORE_PIN8_BIT 3 +#define CORE_PIN9_BIT 3 +#define CORE_PIN10_BIT 4 +#define CORE_PIN11_BIT 6 +#define CORE_PIN12_BIT 7 +#define CORE_PIN13_BIT 5 +#define CORE_PIN14_BIT 1 +#define CORE_PIN15_BIT 0 +#define CORE_PIN16_BIT 0 +#define CORE_PIN17_BIT 1 +#define CORE_PIN18_BIT 3 +#define CORE_PIN19_BIT 2 +#define CORE_PIN20_BIT 5 +#define CORE_PIN21_BIT 6 +#define CORE_PIN22_BIT 1 +#define CORE_PIN23_BIT 2 +#define CORE_PIN24_BIT 20 +#define CORE_PIN25_BIT 21 +#define CORE_PIN26_BIT 30 -#define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT)) -#define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT)) -#define CORE_PIN2_BITMASK (1<<(CORE_PIN2_BIT)) -#define CORE_PIN3_BITMASK (1<<(CORE_PIN3_BIT)) -#define CORE_PIN4_BITMASK (1<<(CORE_PIN4_BIT)) -#define CORE_PIN5_BITMASK (1<<(CORE_PIN5_BIT)) -#define CORE_PIN6_BITMASK (1<<(CORE_PIN6_BIT)) -#define CORE_PIN7_BITMASK (1<<(CORE_PIN7_BIT)) -#define CORE_PIN8_BITMASK (1<<(CORE_PIN8_BIT)) -#define CORE_PIN9_BITMASK (1<<(CORE_PIN9_BIT)) -#define CORE_PIN10_BITMASK (1<<(CORE_PIN10_BIT)) -#define CORE_PIN11_BITMASK (1<<(CORE_PIN11_BIT)) -#define CORE_PIN12_BITMASK (1<<(CORE_PIN12_BIT)) -#define CORE_PIN13_BITMASK (1<<(CORE_PIN13_BIT)) -#define CORE_PIN14_BITMASK (1<<(CORE_PIN14_BIT)) -#define CORE_PIN15_BITMASK (1<<(CORE_PIN15_BIT)) -#define CORE_PIN16_BITMASK (1<<(CORE_PIN16_BIT)) -#define CORE_PIN17_BITMASK (1<<(CORE_PIN17_BIT)) -#define CORE_PIN18_BITMASK (1<<(CORE_PIN18_BIT)) -#define CORE_PIN19_BITMASK (1<<(CORE_PIN19_BIT)) -#define CORE_PIN20_BITMASK (1<<(CORE_PIN20_BIT)) -#define CORE_PIN21_BITMASK (1<<(CORE_PIN21_BIT)) -#define CORE_PIN22_BITMASK (1<<(CORE_PIN22_BIT)) -#define CORE_PIN23_BITMASK (1<<(CORE_PIN23_BIT)) -#define CORE_PIN24_BITMASK (1<<(CORE_PIN24_BIT)) -#define CORE_PIN25_BITMASK (1<<(CORE_PIN25_BIT)) -#define CORE_PIN26_BITMASK (1<<(CORE_PIN26_BIT)) +#define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT)) +#define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT)) +#define CORE_PIN2_BITMASK (1<<(CORE_PIN2_BIT)) +#define CORE_PIN3_BITMASK (1<<(CORE_PIN3_BIT)) +#define CORE_PIN4_BITMASK (1<<(CORE_PIN4_BIT)) +#define CORE_PIN5_BITMASK (1<<(CORE_PIN5_BIT)) +#define CORE_PIN6_BITMASK (1<<(CORE_PIN6_BIT)) +#define CORE_PIN7_BITMASK (1<<(CORE_PIN7_BIT)) +#define CORE_PIN8_BITMASK (1<<(CORE_PIN8_BIT)) +#define CORE_PIN9_BITMASK (1<<(CORE_PIN9_BIT)) +#define CORE_PIN10_BITMASK (1<<(CORE_PIN10_BIT)) +#define CORE_PIN11_BITMASK (1<<(CORE_PIN11_BIT)) +#define CORE_PIN12_BITMASK (1<<(CORE_PIN12_BIT)) +#define CORE_PIN13_BITMASK (1<<(CORE_PIN13_BIT)) +#define CORE_PIN14_BITMASK (1<<(CORE_PIN14_BIT)) +#define CORE_PIN15_BITMASK (1<<(CORE_PIN15_BIT)) +#define CORE_PIN16_BITMASK (1<<(CORE_PIN16_BIT)) +#define CORE_PIN17_BITMASK (1<<(CORE_PIN17_BIT)) +#define CORE_PIN18_BITMASK (1<<(CORE_PIN18_BIT)) +#define CORE_PIN19_BITMASK (1<<(CORE_PIN19_BIT)) +#define CORE_PIN20_BITMASK (1<<(CORE_PIN20_BIT)) +#define CORE_PIN21_BITMASK (1<<(CORE_PIN21_BIT)) +#define CORE_PIN22_BITMASK (1<<(CORE_PIN22_BIT)) +#define CORE_PIN23_BITMASK (1<<(CORE_PIN23_BIT)) +#define CORE_PIN24_BITMASK (1<<(CORE_PIN24_BIT)) +#define CORE_PIN25_BITMASK (1<<(CORE_PIN25_BIT)) +#define CORE_PIN26_BITMASK (1<<(CORE_PIN26_BIT)) -#define CORE_PIN0_PORTREG FGPIOB_PDOR -#define CORE_PIN1_PORTREG FGPIOB_PDOR -#define CORE_PIN2_PORTREG FGPIOD_PDOR -#define CORE_PIN3_PORTREG FGPIOA_PDOR -#define CORE_PIN4_PORTREG FGPIOA_PDOR -#define CORE_PIN5_PORTREG FGPIOD_PDOR -#define CORE_PIN6_PORTREG FGPIOD_PDOR -#define CORE_PIN7_PORTREG FGPIOD_PDOR -#define CORE_PIN8_PORTREG FGPIOD_PDOR -#define CORE_PIN9_PORTREG FGPIOC_PDOR -#define CORE_PIN10_PORTREG FGPIOC_PDOR -#define CORE_PIN11_PORTREG FGPIOC_PDOR -#define CORE_PIN12_PORTREG FGPIOC_PDOR -#define CORE_PIN13_PORTREG FGPIOC_PDOR -#define CORE_PIN14_PORTREG FGPIOD_PDOR -#define CORE_PIN15_PORTREG FGPIOC_PDOR -#define CORE_PIN16_PORTREG FGPIOB_PDOR -#define CORE_PIN17_PORTREG FGPIOB_PDOR -#define CORE_PIN18_PORTREG FGPIOB_PDOR -#define CORE_PIN19_PORTREG FGPIOB_PDOR -#define CORE_PIN20_PORTREG FGPIOD_PDOR -#define CORE_PIN21_PORTREG FGPIOD_PDOR -#define CORE_PIN22_PORTREG FGPIOC_PDOR -#define CORE_PIN23_PORTREG FGPIOC_PDOR -#define CORE_PIN24_PORTREG FGPIOE_PDOR -#define CORE_PIN25_PORTREG FGPIOE_PDOR -#define CORE_PIN26_PORTREG FGPIOE_PDOR +#define CORE_PIN0_PORTREG FGPIOB_PDOR +#define CORE_PIN1_PORTREG FGPIOB_PDOR +#define CORE_PIN2_PORTREG FGPIOD_PDOR +#define CORE_PIN3_PORTREG FGPIOA_PDOR +#define CORE_PIN4_PORTREG FGPIOA_PDOR +#define CORE_PIN5_PORTREG FGPIOD_PDOR +#define CORE_PIN6_PORTREG FGPIOD_PDOR +#define CORE_PIN7_PORTREG FGPIOD_PDOR +#define CORE_PIN8_PORTREG FGPIOD_PDOR +#define CORE_PIN9_PORTREG FGPIOC_PDOR +#define CORE_PIN10_PORTREG FGPIOC_PDOR +#define CORE_PIN11_PORTREG FGPIOC_PDOR +#define CORE_PIN12_PORTREG FGPIOC_PDOR +#define CORE_PIN13_PORTREG FGPIOC_PDOR +#define CORE_PIN14_PORTREG FGPIOD_PDOR +#define CORE_PIN15_PORTREG FGPIOC_PDOR +#define CORE_PIN16_PORTREG FGPIOB_PDOR +#define CORE_PIN17_PORTREG FGPIOB_PDOR +#define CORE_PIN18_PORTREG FGPIOB_PDOR +#define CORE_PIN19_PORTREG FGPIOB_PDOR +#define CORE_PIN20_PORTREG FGPIOD_PDOR +#define CORE_PIN21_PORTREG FGPIOD_PDOR +#define CORE_PIN22_PORTREG FGPIOC_PDOR +#define CORE_PIN23_PORTREG FGPIOC_PDOR +#define CORE_PIN24_PORTREG FGPIOE_PDOR +#define CORE_PIN25_PORTREG FGPIOE_PDOR +#define CORE_PIN26_PORTREG FGPIOE_PDOR -#define CORE_PIN0_PORTSET FGPIOB_PSOR -#define CORE_PIN1_PORTSET FGPIOB_PSOR -#define CORE_PIN2_PORTSET FGPIOD_PSOR -#define CORE_PIN3_PORTSET FGPIOA_PSOR -#define CORE_PIN4_PORTSET FGPIOA_PSOR -#define CORE_PIN5_PORTSET FGPIOD_PSOR -#define CORE_PIN6_PORTSET FGPIOD_PSOR -#define CORE_PIN7_PORTSET FGPIOD_PSOR -#define CORE_PIN8_PORTSET FGPIOD_PSOR -#define CORE_PIN9_PORTSET FGPIOC_PSOR -#define CORE_PIN10_PORTSET FGPIOC_PSOR -#define CORE_PIN11_PORTSET FGPIOC_PSOR -#define CORE_PIN12_PORTSET FGPIOC_PSOR -#define CORE_PIN13_PORTSET FGPIOC_PSOR -#define CORE_PIN14_PORTSET FGPIOD_PSOR -#define CORE_PIN15_PORTSET FGPIOC_PSOR -#define CORE_PIN16_PORTSET FGPIOB_PSOR -#define CORE_PIN17_PORTSET FGPIOB_PSOR -#define CORE_PIN18_PORTSET FGPIOB_PSOR -#define CORE_PIN19_PORTSET FGPIOB_PSOR -#define CORE_PIN20_PORTSET FGPIOD_PSOR -#define CORE_PIN21_PORTSET FGPIOD_PSOR -#define CORE_PIN22_PORTSET FGPIOC_PSOR -#define CORE_PIN23_PORTSET FGPIOC_PSOR -#define CORE_PIN24_PORTSET FGPIOE_PSOR -#define CORE_PIN25_PORTSET FGPIOE_PSOR -#define CORE_PIN26_PORTSET FGPIOE_PSOR +#define CORE_PIN0_PORTSET FGPIOB_PSOR +#define CORE_PIN1_PORTSET FGPIOB_PSOR +#define CORE_PIN2_PORTSET FGPIOD_PSOR +#define CORE_PIN3_PORTSET FGPIOA_PSOR +#define CORE_PIN4_PORTSET FGPIOA_PSOR +#define CORE_PIN5_PORTSET FGPIOD_PSOR +#define CORE_PIN6_PORTSET FGPIOD_PSOR +#define CORE_PIN7_PORTSET FGPIOD_PSOR +#define CORE_PIN8_PORTSET FGPIOD_PSOR +#define CORE_PIN9_PORTSET FGPIOC_PSOR +#define CORE_PIN10_PORTSET FGPIOC_PSOR +#define CORE_PIN11_PORTSET FGPIOC_PSOR +#define CORE_PIN12_PORTSET FGPIOC_PSOR +#define CORE_PIN13_PORTSET FGPIOC_PSOR +#define CORE_PIN14_PORTSET FGPIOD_PSOR +#define CORE_PIN15_PORTSET FGPIOC_PSOR +#define CORE_PIN16_PORTSET FGPIOB_PSOR +#define CORE_PIN17_PORTSET FGPIOB_PSOR +#define CORE_PIN18_PORTSET FGPIOB_PSOR +#define CORE_PIN19_PORTSET FGPIOB_PSOR +#define CORE_PIN20_PORTSET FGPIOD_PSOR +#define CORE_PIN21_PORTSET FGPIOD_PSOR +#define CORE_PIN22_PORTSET FGPIOC_PSOR +#define CORE_PIN23_PORTSET FGPIOC_PSOR +#define CORE_PIN24_PORTSET FGPIOE_PSOR +#define CORE_PIN25_PORTSET FGPIOE_PSOR +#define CORE_PIN26_PORTSET FGPIOE_PSOR -#define CORE_PIN0_PORTCLEAR FGPIOB_PCOR -#define CORE_PIN1_PORTCLEAR FGPIOB_PCOR -#define CORE_PIN2_PORTCLEAR FGPIOD_PCOR -#define CORE_PIN3_PORTCLEAR FGPIOA_PCOR -#define CORE_PIN4_PORTCLEAR FGPIOA_PCOR -#define CORE_PIN5_PORTCLEAR FGPIOD_PCOR -#define CORE_PIN6_PORTCLEAR FGPIOD_PCOR -#define CORE_PIN7_PORTCLEAR FGPIOD_PCOR -#define CORE_PIN8_PORTCLEAR FGPIOD_PCOR -#define CORE_PIN9_PORTCLEAR FGPIOC_PCOR -#define CORE_PIN10_PORTCLEAR FGPIOC_PCOR -#define CORE_PIN11_PORTCLEAR FGPIOC_PCOR -#define CORE_PIN12_PORTCLEAR FGPIOC_PCOR -#define CORE_PIN13_PORTCLEAR FGPIOC_PCOR -#define CORE_PIN14_PORTCLEAR FGPIOD_PCOR -#define CORE_PIN15_PORTCLEAR FGPIOC_PCOR -#define CORE_PIN16_PORTCLEAR FGPIOB_PCOR -#define CORE_PIN17_PORTCLEAR FGPIOB_PCOR -#define CORE_PIN18_PORTCLEAR FGPIOB_PCOR -#define CORE_PIN19_PORTCLEAR FGPIOB_PCOR -#define CORE_PIN20_PORTCLEAR FGPIOD_PCOR -#define CORE_PIN21_PORTCLEAR FGPIOD_PCOR -#define CORE_PIN22_PORTCLEAR FGPIOC_PCOR -#define CORE_PIN23_PORTCLEAR FGPIOC_PCOR -#define CORE_PIN24_PORTCLEAR FGPIOE_PCOR -#define CORE_PIN25_PORTCLEAR FGPIOE_PCOR -#define CORE_PIN26_PORTCLEAR FGPIOE_PCOR +#define CORE_PIN0_PORTCLEAR FGPIOB_PCOR +#define CORE_PIN1_PORTCLEAR FGPIOB_PCOR +#define CORE_PIN2_PORTCLEAR FGPIOD_PCOR +#define CORE_PIN3_PORTCLEAR FGPIOA_PCOR +#define CORE_PIN4_PORTCLEAR FGPIOA_PCOR +#define CORE_PIN5_PORTCLEAR FGPIOD_PCOR +#define CORE_PIN6_PORTCLEAR FGPIOD_PCOR +#define CORE_PIN7_PORTCLEAR FGPIOD_PCOR +#define CORE_PIN8_PORTCLEAR FGPIOD_PCOR +#define CORE_PIN9_PORTCLEAR FGPIOC_PCOR +#define CORE_PIN10_PORTCLEAR FGPIOC_PCOR +#define CORE_PIN11_PORTCLEAR FGPIOC_PCOR +#define CORE_PIN12_PORTCLEAR FGPIOC_PCOR +#define CORE_PIN13_PORTCLEAR FGPIOC_PCOR +#define CORE_PIN14_PORTCLEAR FGPIOD_PCOR +#define CORE_PIN15_PORTCLEAR FGPIOC_PCOR +#define CORE_PIN16_PORTCLEAR FGPIOB_PCOR +#define CORE_PIN17_PORTCLEAR FGPIOB_PCOR +#define CORE_PIN18_PORTCLEAR FGPIOB_PCOR +#define CORE_PIN19_PORTCLEAR FGPIOB_PCOR +#define CORE_PIN20_PORTCLEAR FGPIOD_PCOR +#define CORE_PIN21_PORTCLEAR FGPIOD_PCOR +#define CORE_PIN22_PORTCLEAR FGPIOC_PCOR +#define CORE_PIN23_PORTCLEAR FGPIOC_PCOR +#define CORE_PIN24_PORTCLEAR FGPIOE_PCOR +#define CORE_PIN25_PORTCLEAR FGPIOE_PCOR +#define CORE_PIN26_PORTCLEAR FGPIOE_PCOR -#define CORE_PIN0_DDRREG FGPIOB_PDDR -#define CORE_PIN1_DDRREG FGPIOB_PDDR -#define CORE_PIN2_DDRREG FGPIOD_PDDR -#define CORE_PIN3_DDRREG FGPIOA_PDDR -#define CORE_PIN4_DDRREG FGPIOA_PDDR -#define CORE_PIN5_DDRREG FGPIOD_PDDR -#define CORE_PIN6_DDRREG FGPIOD_PDDR -#define CORE_PIN7_DDRREG FGPIOD_PDDR -#define CORE_PIN8_DDRREG FGPIOD_PDDR -#define CORE_PIN9_DDRREG FGPIOC_PDDR -#define CORE_PIN10_DDRREG FGPIOC_PDDR -#define CORE_PIN11_DDRREG FGPIOC_PDDR -#define CORE_PIN12_DDRREG FGPIOC_PDDR -#define CORE_PIN13_DDRREG FGPIOC_PDDR -#define CORE_PIN14_DDRREG FGPIOD_PDDR -#define CORE_PIN15_DDRREG FGPIOC_PDDR -#define CORE_PIN16_DDRREG FGPIOB_PDDR -#define CORE_PIN17_DDRREG FGPIOB_PDDR -#define CORE_PIN18_DDRREG FGPIOB_PDDR -#define CORE_PIN19_DDRREG FGPIOB_PDDR -#define CORE_PIN20_DDRREG FGPIOD_PDDR -#define CORE_PIN21_DDRREG FGPIOD_PDDR -#define CORE_PIN22_DDRREG FGPIOC_PDDR -#define CORE_PIN23_DDRREG FGPIOC_PDDR -#define CORE_PIN24_DDRREG FGPIOE_PDDR -#define CORE_PIN25_DDRREG FGPIOE_PDDR -#define CORE_PIN26_DDRREG FGPIOE_PDDR +#define CORE_PIN0_DDRREG FGPIOB_PDDR +#define CORE_PIN1_DDRREG FGPIOB_PDDR +#define CORE_PIN2_DDRREG FGPIOD_PDDR +#define CORE_PIN3_DDRREG FGPIOA_PDDR +#define CORE_PIN4_DDRREG FGPIOA_PDDR +#define CORE_PIN5_DDRREG FGPIOD_PDDR +#define CORE_PIN6_DDRREG FGPIOD_PDDR +#define CORE_PIN7_DDRREG FGPIOD_PDDR +#define CORE_PIN8_DDRREG FGPIOD_PDDR +#define CORE_PIN9_DDRREG FGPIOC_PDDR +#define CORE_PIN10_DDRREG FGPIOC_PDDR +#define CORE_PIN11_DDRREG FGPIOC_PDDR +#define CORE_PIN12_DDRREG FGPIOC_PDDR +#define CORE_PIN13_DDRREG FGPIOC_PDDR +#define CORE_PIN14_DDRREG FGPIOD_PDDR +#define CORE_PIN15_DDRREG FGPIOC_PDDR +#define CORE_PIN16_DDRREG FGPIOB_PDDR +#define CORE_PIN17_DDRREG FGPIOB_PDDR +#define CORE_PIN18_DDRREG FGPIOB_PDDR +#define CORE_PIN19_DDRREG FGPIOB_PDDR +#define CORE_PIN20_DDRREG FGPIOD_PDDR +#define CORE_PIN21_DDRREG FGPIOD_PDDR +#define CORE_PIN22_DDRREG FGPIOC_PDDR +#define CORE_PIN23_DDRREG FGPIOC_PDDR +#define CORE_PIN24_DDRREG FGPIOE_PDDR +#define CORE_PIN25_DDRREG FGPIOE_PDDR +#define CORE_PIN26_DDRREG FGPIOE_PDDR -#define CORE_PIN0_PINREG FGPIOB_PDIR -#define CORE_PIN1_PINREG FGPIOB_PDIR -#define CORE_PIN2_PINREG FGPIOD_PDIR -#define CORE_PIN3_PINREG FGPIOA_PDIR -#define CORE_PIN4_PINREG FGPIOA_PDIR -#define CORE_PIN5_PINREG FGPIOD_PDIR -#define CORE_PIN6_PINREG FGPIOD_PDIR -#define CORE_PIN7_PINREG FGPIOD_PDIR -#define CORE_PIN8_PINREG FGPIOD_PDIR -#define CORE_PIN9_PINREG FGPIOC_PDIR -#define CORE_PIN10_PINREG FGPIOC_PDIR -#define CORE_PIN11_PINREG FGPIOC_PDIR -#define CORE_PIN12_PINREG FGPIOC_PDIR -#define CORE_PIN13_PINREG FGPIOC_PDIR -#define CORE_PIN14_PINREG FGPIOD_PDIR -#define CORE_PIN15_PINREG FGPIOC_PDIR -#define CORE_PIN16_PINREG FGPIOB_PDIR -#define CORE_PIN17_PINREG FGPIOB_PDIR -#define CORE_PIN18_PINREG FGPIOB_PDIR -#define CORE_PIN19_PINREG FGPIOB_PDIR -#define CORE_PIN20_PINREG FGPIOD_PDIR -#define CORE_PIN21_PINREG FGPIOD_PDIR -#define CORE_PIN22_PINREG FGPIOC_PDIR -#define CORE_PIN23_PINREG FGPIOC_PDIR -#define CORE_PIN24_PINREG FGPIOE_PDIR -#define CORE_PIN25_PINREG FGPIOE_PDIR -#define CORE_PIN26_PINREG FGPIOE_PDIR +#define CORE_PIN0_PINREG FGPIOB_PDIR +#define CORE_PIN1_PINREG FGPIOB_PDIR +#define CORE_PIN2_PINREG FGPIOD_PDIR +#define CORE_PIN3_PINREG FGPIOA_PDIR +#define CORE_PIN4_PINREG FGPIOA_PDIR +#define CORE_PIN5_PINREG FGPIOD_PDIR +#define CORE_PIN6_PINREG FGPIOD_PDIR +#define CORE_PIN7_PINREG FGPIOD_PDIR +#define CORE_PIN8_PINREG FGPIOD_PDIR +#define CORE_PIN9_PINREG FGPIOC_PDIR +#define CORE_PIN10_PINREG FGPIOC_PDIR +#define CORE_PIN11_PINREG FGPIOC_PDIR +#define CORE_PIN12_PINREG FGPIOC_PDIR +#define CORE_PIN13_PINREG FGPIOC_PDIR +#define CORE_PIN14_PINREG FGPIOD_PDIR +#define CORE_PIN15_PINREG FGPIOC_PDIR +#define CORE_PIN16_PINREG FGPIOB_PDIR +#define CORE_PIN17_PINREG FGPIOB_PDIR +#define CORE_PIN18_PINREG FGPIOB_PDIR +#define CORE_PIN19_PINREG FGPIOB_PDIR +#define CORE_PIN20_PINREG FGPIOD_PDIR +#define CORE_PIN21_PINREG FGPIOD_PDIR +#define CORE_PIN22_PINREG FGPIOC_PDIR +#define CORE_PIN23_PINREG FGPIOC_PDIR +#define CORE_PIN24_PINREG FGPIOE_PDIR +#define CORE_PIN25_PINREG FGPIOE_PDIR +#define CORE_PIN26_PINREG FGPIOE_PDIR -#define CORE_PIN0_CONFIG PORTB_PCR16 -#define CORE_PIN1_CONFIG PORTB_PCR17 -#define CORE_PIN2_CONFIG PORTD_PCR0 -#define CORE_PIN3_CONFIG PORTA_PCR1 -#define CORE_PIN4_CONFIG PORTA_PCR2 -#define CORE_PIN5_CONFIG PORTD_PCR7 -#define CORE_PIN6_CONFIG PORTD_PCR4 -#define CORE_PIN7_CONFIG PORTD_PCR2 -#define CORE_PIN8_CONFIG PORTD_PCR3 -#define CORE_PIN9_CONFIG PORTC_PCR3 -#define CORE_PIN10_CONFIG PORTC_PCR4 -#define CORE_PIN11_CONFIG PORTC_PCR6 -#define CORE_PIN12_CONFIG PORTC_PCR7 -#define CORE_PIN13_CONFIG PORTC_PCR5 -#define CORE_PIN14_CONFIG PORTD_PCR1 -#define CORE_PIN15_CONFIG PORTC_PCR0 -#define CORE_PIN16_CONFIG PORTB_PCR0 -#define CORE_PIN17_CONFIG PORTB_PCR1 -#define CORE_PIN18_CONFIG PORTB_PCR3 -#define CORE_PIN19_CONFIG PORTB_PCR2 -#define CORE_PIN20_CONFIG PORTD_PCR5 -#define CORE_PIN21_CONFIG PORTD_PCR6 -#define CORE_PIN22_CONFIG PORTC_PCR1 -#define CORE_PIN23_CONFIG PORTC_PCR2 -#define CORE_PIN24_CONFIG PORTE_PCR20 -#define CORE_PIN25_CONFIG PORTE_PCR21 -#define CORE_PIN26_CONFIG PORTE_PCR30 +#define CORE_PIN0_CONFIG PORTB_PCR16 +#define CORE_PIN1_CONFIG PORTB_PCR17 +#define CORE_PIN2_CONFIG PORTD_PCR0 +#define CORE_PIN3_CONFIG PORTA_PCR1 +#define CORE_PIN4_CONFIG PORTA_PCR2 +#define CORE_PIN5_CONFIG PORTD_PCR7 +#define CORE_PIN6_CONFIG PORTD_PCR4 +#define CORE_PIN7_CONFIG PORTD_PCR2 +#define CORE_PIN8_CONFIG PORTD_PCR3 +#define CORE_PIN9_CONFIG PORTC_PCR3 +#define CORE_PIN10_CONFIG PORTC_PCR4 +#define CORE_PIN11_CONFIG PORTC_PCR6 +#define CORE_PIN12_CONFIG PORTC_PCR7 +#define CORE_PIN13_CONFIG PORTC_PCR5 +#define CORE_PIN14_CONFIG PORTD_PCR1 +#define CORE_PIN15_CONFIG PORTC_PCR0 +#define CORE_PIN16_CONFIG PORTB_PCR0 +#define CORE_PIN17_CONFIG PORTB_PCR1 +#define CORE_PIN18_CONFIG PORTB_PCR3 +#define CORE_PIN19_CONFIG PORTB_PCR2 +#define CORE_PIN20_CONFIG PORTD_PCR5 +#define CORE_PIN21_CONFIG PORTD_PCR6 +#define CORE_PIN22_CONFIG PORTC_PCR1 +#define CORE_PIN23_CONFIG PORTC_PCR2 +#define CORE_PIN24_CONFIG PORTE_PCR20 +#define CORE_PIN25_CONFIG PORTE_PCR21 +#define CORE_PIN26_CONFIG PORTE_PCR30 -#define CORE_ADC0_PIN 14 -#define CORE_ADC1_PIN 15 -#define CORE_ADC2_PIN 16 -#define CORE_ADC3_PIN 17 -#define CORE_ADC4_PIN 18 -#define CORE_ADC5_PIN 19 -#define CORE_ADC6_PIN 20 -#define CORE_ADC7_PIN 21 -#define CORE_ADC8_PIN 22 -#define CORE_ADC9_PIN 23 -#define CORE_ADC10_PIN 24 -#define CORE_ADC11_PIN 25 -#define CORE_ADC12_PIN 26 +#define CORE_ADC0_PIN 14 +#define CORE_ADC1_PIN 15 +#define CORE_ADC2_PIN 16 +#define CORE_ADC3_PIN 17 +#define CORE_ADC4_PIN 18 +#define CORE_ADC5_PIN 19 +#define CORE_ADC6_PIN 20 +#define CORE_ADC7_PIN 21 +#define CORE_ADC8_PIN 22 +#define CORE_ADC9_PIN 23 +#define CORE_ADC10_PIN 24 +#define CORE_ADC11_PIN 25 +#define CORE_ADC12_PIN 26 -#define CORE_RXD0_PIN 0 -#define CORE_TXD0_PIN 1 -#define CORE_RXD1_PIN 9 -#define CORE_TXD1_PIN 10 -#define CORE_RXD2_PIN 7 -#define CORE_TXD2_PIN 8 +#define CORE_RXD0_PIN 0 +#define CORE_TXD0_PIN 1 +#define CORE_RXD1_PIN 9 +#define CORE_TXD1_PIN 10 +#define CORE_RXD2_PIN 7 +#define CORE_TXD2_PIN 8 -#define CORE_INT2_PIN 2 -#define CORE_INT3_PIN 3 -#define CORE_INT4_PIN 4 -#define CORE_INT5_PIN 5 -#define CORE_INT6_PIN 6 -#define CORE_INT7_PIN 7 -#define CORE_INT8_PIN 8 -#define CORE_INT9_PIN 9 -#define CORE_INT10_PIN 10 -#define CORE_INT11_PIN 11 -#define CORE_INT12_PIN 12 -#define CORE_INT13_PIN 13 -#define CORE_INT14_PIN 14 -#define CORE_INT15_PIN 15 -#define CORE_INT20_PIN 20 -#define CORE_INT21_PIN 21 -#define CORE_INT22_PIN 22 -#define CORE_INT23_PIN 23 +#define CORE_INT2_PIN 2 +#define CORE_INT3_PIN 3 +#define CORE_INT4_PIN 4 +#define CORE_INT5_PIN 5 +#define CORE_INT6_PIN 6 +#define CORE_INT7_PIN 7 +#define CORE_INT8_PIN 8 +#define CORE_INT9_PIN 9 +#define CORE_INT10_PIN 10 +#define CORE_INT11_PIN 11 +#define CORE_INT12_PIN 12 +#define CORE_INT13_PIN 13 +#define CORE_INT14_PIN 14 +#define CORE_INT15_PIN 15 +#define CORE_INT20_PIN 20 +#define CORE_INT21_PIN 21 +#define CORE_INT22_PIN 22 +#define CORE_INT23_PIN 23 #elif defined(__MK64FX512__) || defined(__MK66FX1M0__) -#define CORE_PIN0_BIT 16 -#define CORE_PIN1_BIT 17 -#define CORE_PIN2_BIT 0 -#define CORE_PIN3_BIT 12 -#define CORE_PIN4_BIT 13 -#define CORE_PIN5_BIT 7 -#define CORE_PIN6_BIT 4 -#define CORE_PIN7_BIT 2 -#define CORE_PIN8_BIT 3 -#define CORE_PIN9_BIT 3 -#define CORE_PIN10_BIT 4 -#define CORE_PIN11_BIT 6 -#define CORE_PIN12_BIT 7 -#define CORE_PIN13_BIT 5 -#define CORE_PIN14_BIT 1 -#define CORE_PIN15_BIT 0 -#define CORE_PIN16_BIT 0 -#define CORE_PIN17_BIT 1 -#define CORE_PIN18_BIT 3 -#define CORE_PIN19_BIT 2 -#define CORE_PIN20_BIT 5 -#define CORE_PIN21_BIT 6 -#define CORE_PIN22_BIT 1 -#define CORE_PIN23_BIT 2 -#define CORE_PIN24_BIT 26 -#define CORE_PIN25_BIT 5 -#define CORE_PIN26_BIT 14 -#define CORE_PIN27_BIT 15 -#define CORE_PIN28_BIT 16 -#define CORE_PIN29_BIT 18 -#define CORE_PIN30_BIT 19 -#define CORE_PIN31_BIT 10 -#define CORE_PIN32_BIT 11 -#define CORE_PIN33_BIT 24 -#define CORE_PIN34_BIT 25 -#define CORE_PIN35_BIT 8 -#define CORE_PIN36_BIT 9 -#define CORE_PIN37_BIT 10 -#define CORE_PIN38_BIT 11 -#define CORE_PIN39_BIT 17 -#define CORE_PIN40_BIT 28 -#define CORE_PIN41_BIT 29 -#define CORE_PIN42_BIT 26 -#define CORE_PIN43_BIT 20 -#define CORE_PIN44_BIT 22 -#define CORE_PIN45_BIT 23 -#define CORE_PIN46_BIT 21 -#define CORE_PIN47_BIT 8 -#define CORE_PIN48_BIT 9 -#define CORE_PIN49_BIT 4 -#define CORE_PIN50_BIT 5 -#define CORE_PIN51_BIT 14 -#define CORE_PIN52_BIT 13 -#define CORE_PIN53_BIT 12 -#define CORE_PIN54_BIT 15 -#define CORE_PIN55_BIT 11 -#define CORE_PIN56_BIT 10 -#define CORE_PIN57_BIT 11 -#define CORE_PIN58_BIT 0 -#define CORE_PIN59_BIT 1 -#define CORE_PIN60_BIT 2 -#define CORE_PIN61_BIT 3 -#define CORE_PIN62_BIT 4 -#define CORE_PIN63_BIT 5 - -#define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT)) -#define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT)) -#define CORE_PIN2_BITMASK (1<<(CORE_PIN2_BIT)) -#define CORE_PIN3_BITMASK (1<<(CORE_PIN3_BIT)) -#define CORE_PIN4_BITMASK (1<<(CORE_PIN4_BIT)) -#define CORE_PIN5_BITMASK (1<<(CORE_PIN5_BIT)) -#define CORE_PIN6_BITMASK (1<<(CORE_PIN6_BIT)) -#define CORE_PIN7_BITMASK (1<<(CORE_PIN7_BIT)) -#define CORE_PIN8_BITMASK (1<<(CORE_PIN8_BIT)) -#define CORE_PIN9_BITMASK (1<<(CORE_PIN9_BIT)) -#define CORE_PIN10_BITMASK (1<<(CORE_PIN10_BIT)) -#define CORE_PIN11_BITMASK (1<<(CORE_PIN11_BIT)) -#define CORE_PIN12_BITMASK (1<<(CORE_PIN12_BIT)) -#define CORE_PIN13_BITMASK (1<<(CORE_PIN13_BIT)) -#define CORE_PIN14_BITMASK (1<<(CORE_PIN14_BIT)) -#define CORE_PIN15_BITMASK (1<<(CORE_PIN15_BIT)) -#define CORE_PIN16_BITMASK (1<<(CORE_PIN16_BIT)) -#define CORE_PIN17_BITMASK (1<<(CORE_PIN17_BIT)) -#define CORE_PIN18_BITMASK (1<<(CORE_PIN18_BIT)) -#define CORE_PIN19_BITMASK (1<<(CORE_PIN19_BIT)) -#define CORE_PIN20_BITMASK (1<<(CORE_PIN20_BIT)) -#define CORE_PIN21_BITMASK (1<<(CORE_PIN21_BIT)) -#define CORE_PIN22_BITMASK (1<<(CORE_PIN22_BIT)) -#define CORE_PIN23_BITMASK (1<<(CORE_PIN23_BIT)) -#define CORE_PIN24_BITMASK (1<<(CORE_PIN24_BIT)) -#define CORE_PIN25_BITMASK (1<<(CORE_PIN25_BIT)) -#define CORE_PIN26_BITMASK (1<<(CORE_PIN26_BIT)) -#define CORE_PIN27_BITMASK (1<<(CORE_PIN27_BIT)) -#define CORE_PIN28_BITMASK (1<<(CORE_PIN28_BIT)) -#define CORE_PIN29_BITMASK (1<<(CORE_PIN29_BIT)) -#define CORE_PIN30_BITMASK (1<<(CORE_PIN30_BIT)) -#define CORE_PIN31_BITMASK (1<<(CORE_PIN31_BIT)) -#define CORE_PIN32_BITMASK (1<<(CORE_PIN32_BIT)) -#define CORE_PIN33_BITMASK (1<<(CORE_PIN33_BIT)) -#define CORE_PIN34_BITMASK (1<<(CORE_PIN34_BIT)) -#define CORE_PIN35_BITMASK (1<<(CORE_PIN35_BIT)) -#define CORE_PIN36_BITMASK (1<<(CORE_PIN36_BIT)) -#define CORE_PIN37_BITMASK (1<<(CORE_PIN37_BIT)) -#define CORE_PIN38_BITMASK (1<<(CORE_PIN38_BIT)) -#define CORE_PIN39_BITMASK (1<<(CORE_PIN39_BIT)) -#define CORE_PIN40_BITMASK (1<<(CORE_PIN40_BIT)) -#define CORE_PIN41_BITMASK (1<<(CORE_PIN41_BIT)) -#define CORE_PIN42_BITMASK (1<<(CORE_PIN42_BIT)) -#define CORE_PIN43_BITMASK (1<<(CORE_PIN43_BIT)) -#define CORE_PIN44_BITMASK (1<<(CORE_PIN44_BIT)) -#define CORE_PIN45_BITMASK (1<<(CORE_PIN45_BIT)) -#define CORE_PIN46_BITMASK (1<<(CORE_PIN46_BIT)) -#define CORE_PIN47_BITMASK (1<<(CORE_PIN47_BIT)) -#define CORE_PIN48_BITMASK (1<<(CORE_PIN48_BIT)) -#define CORE_PIN49_BITMASK (1<<(CORE_PIN49_BIT)) -#define CORE_PIN50_BITMASK (1<<(CORE_PIN50_BIT)) -#define CORE_PIN51_BITMASK (1<<(CORE_PIN51_BIT)) -#define CORE_PIN52_BITMASK (1<<(CORE_PIN52_BIT)) -#define CORE_PIN53_BITMASK (1<<(CORE_PIN53_BIT)) -#define CORE_PIN54_BITMASK (1<<(CORE_PIN54_BIT)) -#define CORE_PIN55_BITMASK (1<<(CORE_PIN55_BIT)) -#define CORE_PIN56_BITMASK (1<<(CORE_PIN56_BIT)) -#define CORE_PIN57_BITMASK (1<<(CORE_PIN57_BIT)) -#define CORE_PIN58_BITMASK (1<<(CORE_PIN58_BIT)) -#define CORE_PIN59_BITMASK (1<<(CORE_PIN59_BIT)) -#define CORE_PIN60_BITMASK (1<<(CORE_PIN60_BIT)) -#define CORE_PIN61_BITMASK (1<<(CORE_PIN61_BIT)) -#define CORE_PIN62_BITMASK (1<<(CORE_PIN62_BIT)) -#define CORE_PIN63_BITMASK (1<<(CORE_PIN63_BIT)) +#define CORE_PIN0_BIT 16 +#define CORE_PIN1_BIT 17 +#define CORE_PIN2_BIT 0 +#define CORE_PIN3_BIT 12 +#define CORE_PIN4_BIT 13 +#define CORE_PIN5_BIT 7 +#define CORE_PIN6_BIT 4 +#define CORE_PIN7_BIT 2 +#define CORE_PIN8_BIT 3 +#define CORE_PIN9_BIT 3 +#define CORE_PIN10_BIT 4 +#define CORE_PIN11_BIT 6 +#define CORE_PIN12_BIT 7 +#define CORE_PIN13_BIT 5 +#define CORE_PIN14_BIT 1 +#define CORE_PIN15_BIT 0 +#define CORE_PIN16_BIT 0 +#define CORE_PIN17_BIT 1 +#define CORE_PIN18_BIT 3 +#define CORE_PIN19_BIT 2 +#define CORE_PIN20_BIT 5 +#define CORE_PIN21_BIT 6 +#define CORE_PIN22_BIT 1 +#define CORE_PIN23_BIT 2 +#define CORE_PIN24_BIT 26 +#define CORE_PIN25_BIT 5 +#define CORE_PIN26_BIT 14 +#define CORE_PIN27_BIT 15 +#define CORE_PIN28_BIT 16 +#define CORE_PIN29_BIT 18 +#define CORE_PIN30_BIT 19 +#define CORE_PIN31_BIT 10 +#define CORE_PIN32_BIT 11 +#define CORE_PIN33_BIT 24 +#define CORE_PIN34_BIT 25 +#define CORE_PIN35_BIT 8 +#define CORE_PIN36_BIT 9 +#define CORE_PIN37_BIT 10 +#define CORE_PIN38_BIT 11 +#define CORE_PIN39_BIT 17 +#define CORE_PIN40_BIT 28 +#define CORE_PIN41_BIT 29 +#define CORE_PIN42_BIT 26 +#define CORE_PIN43_BIT 20 +#define CORE_PIN44_BIT 22 +#define CORE_PIN45_BIT 23 +#define CORE_PIN46_BIT 21 +#define CORE_PIN47_BIT 8 +#define CORE_PIN48_BIT 9 +#define CORE_PIN49_BIT 4 +#define CORE_PIN50_BIT 5 +#define CORE_PIN51_BIT 14 +#define CORE_PIN52_BIT 13 +#define CORE_PIN53_BIT 12 +#define CORE_PIN54_BIT 15 +#define CORE_PIN55_BIT 11 +#define CORE_PIN56_BIT 10 +#define CORE_PIN57_BIT 11 +#define CORE_PIN58_BIT 0 +#define CORE_PIN59_BIT 1 +#define CORE_PIN60_BIT 2 +#define CORE_PIN61_BIT 3 +#define CORE_PIN62_BIT 4 +#define CORE_PIN63_BIT 5 +// tranZPUter v2.2 additional pins. +#define CORE_PIN64_BIT 12 // PTC12 +#define CORE_PIN65_BIT 13 // PTC13 +#define CORE_PIN66_BIT 14 // PTC14 +#define CORE_PIN67_BIT 15 // PTC15 +#define CORE_PIN68_BIT 16 // PTC16 +#define CORE_PIN69_BIT 17 // PTC17 +#define CORE_PIN70_BIT 18 // PTC18 +#define CORE_PIN71_BIT 9 // PTB9 -#define CORE_PIN0_PORTREG GPIOB_PDOR -#define CORE_PIN1_PORTREG GPIOB_PDOR -#define CORE_PIN2_PORTREG GPIOD_PDOR -#define CORE_PIN3_PORTREG GPIOA_PDOR -#define CORE_PIN4_PORTREG GPIOA_PDOR -#define CORE_PIN5_PORTREG GPIOD_PDOR -#define CORE_PIN6_PORTREG GPIOD_PDOR -#define CORE_PIN7_PORTREG GPIOD_PDOR -#define CORE_PIN8_PORTREG GPIOD_PDOR -#define CORE_PIN9_PORTREG GPIOC_PDOR -#define CORE_PIN10_PORTREG GPIOC_PDOR -#define CORE_PIN11_PORTREG GPIOC_PDOR -#define CORE_PIN12_PORTREG GPIOC_PDOR -#define CORE_PIN13_PORTREG GPIOC_PDOR -#define CORE_PIN14_PORTREG GPIOD_PDOR -#define CORE_PIN15_PORTREG GPIOC_PDOR -#define CORE_PIN16_PORTREG GPIOB_PDOR -#define CORE_PIN17_PORTREG GPIOB_PDOR -#define CORE_PIN18_PORTREG GPIOB_PDOR -#define CORE_PIN19_PORTREG GPIOB_PDOR -#define CORE_PIN20_PORTREG GPIOD_PDOR -#define CORE_PIN21_PORTREG GPIOD_PDOR -#define CORE_PIN22_PORTREG GPIOC_PDOR -#define CORE_PIN23_PORTREG GPIOC_PDOR -#define CORE_PIN24_PORTREG GPIOE_PDOR -#define CORE_PIN25_PORTREG GPIOA_PDOR -#define CORE_PIN26_PORTREG GPIOA_PDOR -#define CORE_PIN27_PORTREG GPIOA_PDOR -#define CORE_PIN28_PORTREG GPIOA_PDOR -#define CORE_PIN29_PORTREG GPIOB_PDOR -#define CORE_PIN30_PORTREG GPIOB_PDOR -#define CORE_PIN31_PORTREG GPIOB_PDOR -#define CORE_PIN32_PORTREG GPIOB_PDOR -#define CORE_PIN33_PORTREG GPIOE_PDOR -#define CORE_PIN34_PORTREG GPIOE_PDOR -#define CORE_PIN35_PORTREG GPIOC_PDOR -#define CORE_PIN36_PORTREG GPIOC_PDOR -#define CORE_PIN37_PORTREG GPIOC_PDOR -#define CORE_PIN38_PORTREG GPIOC_PDOR -#define CORE_PIN39_PORTREG GPIOA_PDOR -#define CORE_PIN40_PORTREG GPIOA_PDOR -#define CORE_PIN41_PORTREG GPIOA_PDOR -#define CORE_PIN42_PORTREG GPIOA_PDOR -#define CORE_PIN43_PORTREG GPIOB_PDOR -#define CORE_PIN44_PORTREG GPIOB_PDOR -#define CORE_PIN45_PORTREG GPIOB_PDOR -#define CORE_PIN46_PORTREG GPIOB_PDOR -#define CORE_PIN47_PORTREG GPIOD_PDOR -#define CORE_PIN48_PORTREG GPIOD_PDOR -#define CORE_PIN49_PORTREG GPIOB_PDOR -#define CORE_PIN50_PORTREG GPIOB_PDOR -#define CORE_PIN51_PORTREG GPIOD_PDOR -#define CORE_PIN52_PORTREG GPIOD_PDOR -#define CORE_PIN53_PORTREG GPIOD_PDOR -#define CORE_PIN54_PORTREG GPIOD_PDOR -#define CORE_PIN55_PORTREG GPIOD_PDOR -#define CORE_PIN56_PORTREG GPIOE_PDOR -#define CORE_PIN57_PORTREG GPIOE_PDOR -#define CORE_PIN58_PORTREG GPIOE_PDOR -#define CORE_PIN59_PORTREG GPIOE_PDOR -#define CORE_PIN60_PORTREG GPIOE_PDOR -#define CORE_PIN61_PORTREG GPIOE_PDOR -#define CORE_PIN62_PORTREG GPIOE_PDOR -#define CORE_PIN63_PORTREG GPIOE_PDOR +#define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT)) +#define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT)) +#define CORE_PIN2_BITMASK (1<<(CORE_PIN2_BIT)) +#define CORE_PIN3_BITMASK (1<<(CORE_PIN3_BIT)) +#define CORE_PIN4_BITMASK (1<<(CORE_PIN4_BIT)) +#define CORE_PIN5_BITMASK (1<<(CORE_PIN5_BIT)) +#define CORE_PIN6_BITMASK (1<<(CORE_PIN6_BIT)) +#define CORE_PIN7_BITMASK (1<<(CORE_PIN7_BIT)) +#define CORE_PIN8_BITMASK (1<<(CORE_PIN8_BIT)) +#define CORE_PIN9_BITMASK (1<<(CORE_PIN9_BIT)) +#define CORE_PIN10_BITMASK (1<<(CORE_PIN10_BIT)) +#define CORE_PIN11_BITMASK (1<<(CORE_PIN11_BIT)) +#define CORE_PIN12_BITMASK (1<<(CORE_PIN12_BIT)) +#define CORE_PIN13_BITMASK (1<<(CORE_PIN13_BIT)) +#define CORE_PIN14_BITMASK (1<<(CORE_PIN14_BIT)) +#define CORE_PIN15_BITMASK (1<<(CORE_PIN15_BIT)) +#define CORE_PIN16_BITMASK (1<<(CORE_PIN16_BIT)) +#define CORE_PIN17_BITMASK (1<<(CORE_PIN17_BIT)) +#define CORE_PIN18_BITMASK (1<<(CORE_PIN18_BIT)) +#define CORE_PIN19_BITMASK (1<<(CORE_PIN19_BIT)) +#define CORE_PIN20_BITMASK (1<<(CORE_PIN20_BIT)) +#define CORE_PIN21_BITMASK (1<<(CORE_PIN21_BIT)) +#define CORE_PIN22_BITMASK (1<<(CORE_PIN22_BIT)) +#define CORE_PIN23_BITMASK (1<<(CORE_PIN23_BIT)) +#define CORE_PIN24_BITMASK (1<<(CORE_PIN24_BIT)) +#define CORE_PIN25_BITMASK (1<<(CORE_PIN25_BIT)) +#define CORE_PIN26_BITMASK (1<<(CORE_PIN26_BIT)) +#define CORE_PIN27_BITMASK (1<<(CORE_PIN27_BIT)) +#define CORE_PIN28_BITMASK (1<<(CORE_PIN28_BIT)) +#define CORE_PIN29_BITMASK (1<<(CORE_PIN29_BIT)) +#define CORE_PIN30_BITMASK (1<<(CORE_PIN30_BIT)) +#define CORE_PIN31_BITMASK (1<<(CORE_PIN31_BIT)) +#define CORE_PIN32_BITMASK (1<<(CORE_PIN32_BIT)) +#define CORE_PIN33_BITMASK (1<<(CORE_PIN33_BIT)) +#define CORE_PIN34_BITMASK (1<<(CORE_PIN34_BIT)) +#define CORE_PIN35_BITMASK (1<<(CORE_PIN35_BIT)) +#define CORE_PIN36_BITMASK (1<<(CORE_PIN36_BIT)) +#define CORE_PIN37_BITMASK (1<<(CORE_PIN37_BIT)) +#define CORE_PIN38_BITMASK (1<<(CORE_PIN38_BIT)) +#define CORE_PIN39_BITMASK (1<<(CORE_PIN39_BIT)) +#define CORE_PIN40_BITMASK (1<<(CORE_PIN40_BIT)) +#define CORE_PIN41_BITMASK (1<<(CORE_PIN41_BIT)) +#define CORE_PIN42_BITMASK (1<<(CORE_PIN42_BIT)) +#define CORE_PIN43_BITMASK (1<<(CORE_PIN43_BIT)) +#define CORE_PIN44_BITMASK (1<<(CORE_PIN44_BIT)) +#define CORE_PIN45_BITMASK (1<<(CORE_PIN45_BIT)) +#define CORE_PIN46_BITMASK (1<<(CORE_PIN46_BIT)) +#define CORE_PIN47_BITMASK (1<<(CORE_PIN47_BIT)) +#define CORE_PIN48_BITMASK (1<<(CORE_PIN48_BIT)) +#define CORE_PIN49_BITMASK (1<<(CORE_PIN49_BIT)) +#define CORE_PIN50_BITMASK (1<<(CORE_PIN50_BIT)) +#define CORE_PIN51_BITMASK (1<<(CORE_PIN51_BIT)) +#define CORE_PIN52_BITMASK (1<<(CORE_PIN52_BIT)) +#define CORE_PIN53_BITMASK (1<<(CORE_PIN53_BIT)) +#define CORE_PIN54_BITMASK (1<<(CORE_PIN54_BIT)) +#define CORE_PIN55_BITMASK (1<<(CORE_PIN55_BIT)) +#define CORE_PIN56_BITMASK (1<<(CORE_PIN56_BIT)) +#define CORE_PIN57_BITMASK (1<<(CORE_PIN57_BIT)) +#define CORE_PIN58_BITMASK (1<<(CORE_PIN58_BIT)) +#define CORE_PIN59_BITMASK (1<<(CORE_PIN59_BIT)) +#define CORE_PIN60_BITMASK (1<<(CORE_PIN60_BIT)) +#define CORE_PIN61_BITMASK (1<<(CORE_PIN61_BIT)) +#define CORE_PIN62_BITMASK (1<<(CORE_PIN62_BIT)) +#define CORE_PIN63_BITMASK (1<<(CORE_PIN63_BIT)) +// tranZPUter v2.2 additional pins. +#define CORE_PIN64_BITMASK (1<<(CORE_PIN64_BIT)) // PTC12 +#define CORE_PIN65_BITMASK (1<<(CORE_PIN65_BIT)) // PTC13 +#define CORE_PIN66_BITMASK (1<<(CORE_PIN66_BIT)) // PTC14 +#define CORE_PIN67_BITMASK (1<<(CORE_PIN67_BIT)) // PTC15 +#define CORE_PIN68_BITMASK (1<<(CORE_PIN68_BIT)) // PTC16 +#define CORE_PIN69_BITMASK (1<<(CORE_PIN69_BIT)) // PTC17 +#define CORE_PIN70_BITMASK (1<<(CORE_PIN70_BIT)) // PTC18 +#define CORE_PIN71_BITMASK (1<<(CORE_PIN71_BIT)) // PTB9 -#define CORE_PIN0_PORTSET GPIOB_PSOR -#define CORE_PIN1_PORTSET GPIOB_PSOR -#define CORE_PIN2_PORTSET GPIOD_PSOR -#define CORE_PIN3_PORTSET GPIOA_PSOR -#define CORE_PIN4_PORTSET GPIOA_PSOR -#define CORE_PIN5_PORTSET GPIOD_PSOR -#define CORE_PIN6_PORTSET GPIOD_PSOR -#define CORE_PIN7_PORTSET GPIOD_PSOR -#define CORE_PIN8_PORTSET GPIOD_PSOR -#define CORE_PIN9_PORTSET GPIOC_PSOR -#define CORE_PIN10_PORTSET GPIOC_PSOR -#define CORE_PIN11_PORTSET GPIOC_PSOR -#define CORE_PIN12_PORTSET GPIOC_PSOR -#define CORE_PIN13_PORTSET GPIOC_PSOR -#define CORE_PIN14_PORTSET GPIOD_PSOR -#define CORE_PIN15_PORTSET GPIOC_PSOR -#define CORE_PIN16_PORTSET GPIOB_PSOR -#define CORE_PIN17_PORTSET GPIOB_PSOR -#define CORE_PIN18_PORTSET GPIOB_PSOR -#define CORE_PIN19_PORTSET GPIOB_PSOR -#define CORE_PIN20_PORTSET GPIOD_PSOR -#define CORE_PIN21_PORTSET GPIOD_PSOR -#define CORE_PIN22_PORTSET GPIOC_PSOR -#define CORE_PIN23_PORTSET GPIOC_PSOR -#define CORE_PIN24_PORTSET GPIOE_PSOR -#define CORE_PIN25_PORTSET GPIOA_PSOR -#define CORE_PIN26_PORTSET GPIOA_PSOR -#define CORE_PIN27_PORTSET GPIOA_PSOR -#define CORE_PIN28_PORTSET GPIOA_PSOR -#define CORE_PIN29_PORTSET GPIOB_PSOR -#define CORE_PIN30_PORTSET GPIOB_PSOR -#define CORE_PIN31_PORTSET GPIOB_PSOR -#define CORE_PIN32_PORTSET GPIOB_PSOR -#define CORE_PIN33_PORTSET GPIOE_PSOR -#define CORE_PIN34_PORTSET GPIOE_PSOR -#define CORE_PIN35_PORTSET GPIOC_PSOR -#define CORE_PIN36_PORTSET GPIOC_PSOR -#define CORE_PIN37_PORTSET GPIOC_PSOR -#define CORE_PIN38_PORTSET GPIOC_PSOR -#define CORE_PIN39_PORTSET GPIOA_PSOR -#define CORE_PIN40_PORTSET GPIOA_PSOR -#define CORE_PIN41_PORTSET GPIOA_PSOR -#define CORE_PIN42_PORTSET GPIOA_PSOR -#define CORE_PIN43_PORTSET GPIOB_PSOR -#define CORE_PIN44_PORTSET GPIOB_PSOR -#define CORE_PIN45_PORTSET GPIOB_PSOR -#define CORE_PIN46_PORTSET GPIOB_PSOR -#define CORE_PIN47_PORTSET GPIOD_PSOR -#define CORE_PIN48_PORTSET GPIOD_PSOR -#define CORE_PIN49_PORTSET GPIOB_PSOR -#define CORE_PIN50_PORTSET GPIOB_PSOR -#define CORE_PIN51_PORTSET GPIOD_PSOR -#define CORE_PIN52_PORTSET GPIOD_PSOR -#define CORE_PIN53_PORTSET GPIOD_PSOR -#define CORE_PIN54_PORTSET GPIOD_PSOR -#define CORE_PIN55_PORTSET GPIOD_PSOR -#define CORE_PIN56_PORTSET GPIOE_PSOR -#define CORE_PIN57_PORTSET GPIOE_PSOR -#define CORE_PIN58_PORTSET GPIOE_PSOR -#define CORE_PIN59_PORTSET GPIOE_PSOR -#define CORE_PIN60_PORTSET GPIOE_PSOR -#define CORE_PIN61_PORTSET GPIOE_PSOR -#define CORE_PIN62_PORTSET GPIOE_PSOR -#define CORE_PIN63_PORTSET GPIOE_PSOR -#define CORE_PIN0_PORTCLEAR GPIOB_PCOR -#define CORE_PIN1_PORTCLEAR GPIOB_PCOR -#define CORE_PIN2_PORTCLEAR GPIOD_PCOR -#define CORE_PIN3_PORTCLEAR GPIOA_PCOR -#define CORE_PIN4_PORTCLEAR GPIOA_PCOR -#define CORE_PIN5_PORTCLEAR GPIOD_PCOR -#define CORE_PIN6_PORTCLEAR GPIOD_PCOR -#define CORE_PIN7_PORTCLEAR GPIOD_PCOR -#define CORE_PIN8_PORTCLEAR GPIOD_PCOR -#define CORE_PIN9_PORTCLEAR GPIOC_PCOR -#define CORE_PIN10_PORTCLEAR GPIOC_PCOR -#define CORE_PIN11_PORTCLEAR GPIOC_PCOR -#define CORE_PIN12_PORTCLEAR GPIOC_PCOR -#define CORE_PIN13_PORTCLEAR GPIOC_PCOR -#define CORE_PIN14_PORTCLEAR GPIOD_PCOR -#define CORE_PIN15_PORTCLEAR GPIOC_PCOR -#define CORE_PIN16_PORTCLEAR GPIOB_PCOR -#define CORE_PIN17_PORTCLEAR GPIOB_PCOR -#define CORE_PIN18_PORTCLEAR GPIOB_PCOR -#define CORE_PIN19_PORTCLEAR GPIOB_PCOR -#define CORE_PIN20_PORTCLEAR GPIOD_PCOR -#define CORE_PIN21_PORTCLEAR GPIOD_PCOR -#define CORE_PIN22_PORTCLEAR GPIOC_PCOR -#define CORE_PIN23_PORTCLEAR GPIOC_PCOR -#define CORE_PIN24_PORTCLEAR GPIOE_PCOR -#define CORE_PIN25_PORTCLEAR GPIOA_PCOR -#define CORE_PIN26_PORTCLEAR GPIOA_PCOR -#define CORE_PIN27_PORTCLEAR GPIOA_PCOR -#define CORE_PIN28_PORTCLEAR GPIOA_PCOR -#define CORE_PIN29_PORTCLEAR GPIOB_PCOR -#define CORE_PIN30_PORTCLEAR GPIOB_PCOR -#define CORE_PIN31_PORTCLEAR GPIOB_PCOR -#define CORE_PIN32_PORTCLEAR GPIOB_PCOR -#define CORE_PIN33_PORTCLEAR GPIOE_PCOR -#define CORE_PIN34_PORTCLEAR GPIOE_PCOR -#define CORE_PIN35_PORTCLEAR GPIOC_PCOR -#define CORE_PIN36_PORTCLEAR GPIOC_PCOR -#define CORE_PIN37_PORTCLEAR GPIOC_PCOR -#define CORE_PIN38_PORTCLEAR GPIOC_PCOR -#define CORE_PIN39_PORTCLEAR GPIOA_PCOR -#define CORE_PIN40_PORTCLEAR GPIOA_PCOR -#define CORE_PIN41_PORTCLEAR GPIOA_PCOR -#define CORE_PIN42_PORTCLEAR GPIOA_PCOR -#define CORE_PIN43_PORTCLEAR GPIOB_PCOR -#define CORE_PIN44_PORTCLEAR GPIOB_PCOR -#define CORE_PIN45_PORTCLEAR GPIOB_PCOR -#define CORE_PIN46_PORTCLEAR GPIOB_PCOR -#define CORE_PIN47_PORTCLEAR GPIOD_PCOR -#define CORE_PIN48_PORTCLEAR GPIOD_PCOR -#define CORE_PIN49_PORTCLEAR GPIOB_PCOR -#define CORE_PIN50_PORTCLEAR GPIOB_PCOR -#define CORE_PIN51_PORTCLEAR GPIOD_PCOR -#define CORE_PIN52_PORTCLEAR GPIOD_PCOR -#define CORE_PIN53_PORTCLEAR GPIOD_PCOR -#define CORE_PIN54_PORTCLEAR GPIOD_PCOR -#define CORE_PIN55_PORTCLEAR GPIOD_PCOR -#define CORE_PIN56_PORTCLEAR GPIOE_PCOR -#define CORE_PIN57_PORTCLEAR GPIOE_PCOR -#define CORE_PIN58_PORTCLEAR GPIOE_PCOR -#define CORE_PIN59_PORTCLEAR GPIOE_PCOR -#define CORE_PIN60_PORTCLEAR GPIOE_PCOR -#define CORE_PIN61_PORTCLEAR GPIOE_PCOR -#define CORE_PIN62_PORTCLEAR GPIOE_PCOR -#define CORE_PIN63_PORTCLEAR GPIOE_PCOR +#define CORE_PIN0_PORTREG GPIOB_PDOR +#define CORE_PIN1_PORTREG GPIOB_PDOR +#define CORE_PIN2_PORTREG GPIOD_PDOR +#define CORE_PIN3_PORTREG GPIOA_PDOR +#define CORE_PIN4_PORTREG GPIOA_PDOR +#define CORE_PIN5_PORTREG GPIOD_PDOR +#define CORE_PIN6_PORTREG GPIOD_PDOR +#define CORE_PIN7_PORTREG GPIOD_PDOR +#define CORE_PIN8_PORTREG GPIOD_PDOR +#define CORE_PIN9_PORTREG GPIOC_PDOR +#define CORE_PIN10_PORTREG GPIOC_PDOR +#define CORE_PIN11_PORTREG GPIOC_PDOR +#define CORE_PIN12_PORTREG GPIOC_PDOR +#define CORE_PIN13_PORTREG GPIOC_PDOR +#define CORE_PIN14_PORTREG GPIOD_PDOR +#define CORE_PIN15_PORTREG GPIOC_PDOR +#define CORE_PIN16_PORTREG GPIOB_PDOR +#define CORE_PIN17_PORTREG GPIOB_PDOR +#define CORE_PIN18_PORTREG GPIOB_PDOR +#define CORE_PIN19_PORTREG GPIOB_PDOR +#define CORE_PIN20_PORTREG GPIOD_PDOR +#define CORE_PIN21_PORTREG GPIOD_PDOR +#define CORE_PIN22_PORTREG GPIOC_PDOR +#define CORE_PIN23_PORTREG GPIOC_PDOR +#define CORE_PIN24_PORTREG GPIOE_PDOR +#define CORE_PIN25_PORTREG GPIOA_PDOR +#define CORE_PIN26_PORTREG GPIOA_PDOR +#define CORE_PIN27_PORTREG GPIOA_PDOR +#define CORE_PIN28_PORTREG GPIOA_PDOR +#define CORE_PIN29_PORTREG GPIOB_PDOR +#define CORE_PIN30_PORTREG GPIOB_PDOR +#define CORE_PIN31_PORTREG GPIOB_PDOR +#define CORE_PIN32_PORTREG GPIOB_PDOR +#define CORE_PIN33_PORTREG GPIOE_PDOR +#define CORE_PIN34_PORTREG GPIOE_PDOR +#define CORE_PIN35_PORTREG GPIOC_PDOR +#define CORE_PIN36_PORTREG GPIOC_PDOR +#define CORE_PIN37_PORTREG GPIOC_PDOR +#define CORE_PIN38_PORTREG GPIOC_PDOR +#define CORE_PIN39_PORTREG GPIOA_PDOR +#define CORE_PIN40_PORTREG GPIOA_PDOR +#define CORE_PIN41_PORTREG GPIOA_PDOR +#define CORE_PIN42_PORTREG GPIOA_PDOR +#define CORE_PIN43_PORTREG GPIOB_PDOR +#define CORE_PIN44_PORTREG GPIOB_PDOR +#define CORE_PIN45_PORTREG GPIOB_PDOR +#define CORE_PIN46_PORTREG GPIOB_PDOR +#define CORE_PIN47_PORTREG GPIOD_PDOR +#define CORE_PIN48_PORTREG GPIOD_PDOR +#define CORE_PIN49_PORTREG GPIOB_PDOR +#define CORE_PIN50_PORTREG GPIOB_PDOR +#define CORE_PIN51_PORTREG GPIOD_PDOR +#define CORE_PIN52_PORTREG GPIOD_PDOR +#define CORE_PIN53_PORTREG GPIOD_PDOR +#define CORE_PIN54_PORTREG GPIOD_PDOR +#define CORE_PIN55_PORTREG GPIOD_PDOR +#define CORE_PIN56_PORTREG GPIOE_PDOR +#define CORE_PIN57_PORTREG GPIOE_PDOR +#define CORE_PIN58_PORTREG GPIOE_PDOR +#define CORE_PIN59_PORTREG GPIOE_PDOR +#define CORE_PIN60_PORTREG GPIOE_PDOR +#define CORE_PIN61_PORTREG GPIOE_PDOR +#define CORE_PIN62_PORTREG GPIOE_PDOR +#define CORE_PIN63_PORTREG GPIOE_PDOR +// tranZPUter v2.2 additional pins. +#define CORE_PIN64_PORTREG GPIOC_PDOR // PTC12 +#define CORE_PIN65_PORTREG GPIOC_PDOR // PTC13 +#define CORE_PIN66_PORTREG GPIOC_PDOR // PTC14 +#define CORE_PIN67_PORTREG GPIOC_PDOR // PTC15 +#define CORE_PIN68_PORTREG GPIOC_PDOR // PTC16 +#define CORE_PIN69_PORTREG GPIOC_PDOR // PTC17 +#define CORE_PIN70_PORTREG GPIOC_PDOR // PTC18 +#define CORE_PIN71_PORTREG GPIOB_PDOR // PTB9 -#define CORE_PIN0_DDRREG GPIOB_PDDR -#define CORE_PIN1_DDRREG GPIOB_PDDR -#define CORE_PIN2_DDRREG GPIOD_PDDR -#define CORE_PIN3_DDRREG GPIOA_PDDR -#define CORE_PIN4_DDRREG GPIOA_PDDR -#define CORE_PIN5_DDRREG GPIOD_PDDR -#define CORE_PIN6_DDRREG GPIOD_PDDR -#define CORE_PIN7_DDRREG GPIOD_PDDR -#define CORE_PIN8_DDRREG GPIOD_PDDR -#define CORE_PIN9_DDRREG GPIOC_PDDR -#define CORE_PIN10_DDRREG GPIOC_PDDR -#define CORE_PIN11_DDRREG GPIOC_PDDR -#define CORE_PIN12_DDRREG GPIOC_PDDR -#define CORE_PIN13_DDRREG GPIOC_PDDR -#define CORE_PIN14_DDRREG GPIOD_PDDR -#define CORE_PIN15_DDRREG GPIOC_PDDR -#define CORE_PIN16_DDRREG GPIOB_PDDR -#define CORE_PIN17_DDRREG GPIOB_PDDR -#define CORE_PIN18_DDRREG GPIOB_PDDR -#define CORE_PIN19_DDRREG GPIOB_PDDR -#define CORE_PIN20_DDRREG GPIOD_PDDR -#define CORE_PIN21_DDRREG GPIOD_PDDR -#define CORE_PIN22_DDRREG GPIOC_PDDR -#define CORE_PIN23_DDRREG GPIOC_PDDR -#define CORE_PIN24_DDRREG GPIOE_PDDR -#define CORE_PIN25_DDRREG GPIOA_PDDR -#define CORE_PIN26_DDRREG GPIOA_PDDR -#define CORE_PIN27_DDRREG GPIOA_PDDR -#define CORE_PIN28_DDRREG GPIOA_PDDR -#define CORE_PIN29_DDRREG GPIOB_PDDR -#define CORE_PIN30_DDRREG GPIOB_PDDR -#define CORE_PIN31_DDRREG GPIOB_PDDR -#define CORE_PIN32_DDRREG GPIOB_PDDR -#define CORE_PIN33_DDRREG GPIOE_PDDR -#define CORE_PIN34_DDRREG GPIOE_PDDR -#define CORE_PIN35_DDRREG GPIOC_PDDR -#define CORE_PIN36_DDRREG GPIOC_PDDR -#define CORE_PIN37_DDRREG GPIOC_PDDR -#define CORE_PIN38_DDRREG GPIOC_PDDR -#define CORE_PIN39_DDRREG GPIOA_PDDR -#define CORE_PIN40_DDRREG GPIOA_PDDR -#define CORE_PIN41_DDRREG GPIOA_PDDR -#define CORE_PIN42_DDRREG GPIOA_PDDR -#define CORE_PIN43_DDRREG GPIOB_PDDR -#define CORE_PIN44_DDRREG GPIOB_PDDR -#define CORE_PIN45_DDRREG GPIOB_PDDR -#define CORE_PIN46_DDRREG GPIOB_PDDR -#define CORE_PIN47_DDRREG GPIOD_PDDR -#define CORE_PIN48_DDRREG GPIOD_PDDR -#define CORE_PIN49_DDRREG GPIOB_PDDR -#define CORE_PIN50_DDRREG GPIOB_PDDR -#define CORE_PIN51_DDRREG GPIOD_PDDR -#define CORE_PIN52_DDRREG GPIOD_PDDR -#define CORE_PIN53_DDRREG GPIOD_PDDR -#define CORE_PIN54_DDRREG GPIOD_PDDR -#define CORE_PIN55_DDRREG GPIOD_PDDR -#define CORE_PIN56_DDRREG GPIOE_PDDR -#define CORE_PIN57_DDRREG GPIOE_PDDR -#define CORE_PIN58_DDRREG GPIOE_PDDR -#define CORE_PIN59_DDRREG GPIOE_PDDR -#define CORE_PIN60_DDRREG GPIOE_PDDR -#define CORE_PIN61_DDRREG GPIOE_PDDR -#define CORE_PIN62_DDRREG GPIOE_PDDR -#define CORE_PIN63_DDRREG GPIOE_PDDR +#define CORE_PIN0_PORTSET GPIOB_PSOR +#define CORE_PIN1_PORTSET GPIOB_PSOR +#define CORE_PIN2_PORTSET GPIOD_PSOR +#define CORE_PIN3_PORTSET GPIOA_PSOR +#define CORE_PIN4_PORTSET GPIOA_PSOR +#define CORE_PIN5_PORTSET GPIOD_PSOR +#define CORE_PIN6_PORTSET GPIOD_PSOR +#define CORE_PIN7_PORTSET GPIOD_PSOR +#define CORE_PIN8_PORTSET GPIOD_PSOR +#define CORE_PIN9_PORTSET GPIOC_PSOR +#define CORE_PIN10_PORTSET GPIOC_PSOR +#define CORE_PIN11_PORTSET GPIOC_PSOR +#define CORE_PIN12_PORTSET GPIOC_PSOR +#define CORE_PIN13_PORTSET GPIOC_PSOR +#define CORE_PIN14_PORTSET GPIOD_PSOR +#define CORE_PIN15_PORTSET GPIOC_PSOR +#define CORE_PIN16_PORTSET GPIOB_PSOR +#define CORE_PIN17_PORTSET GPIOB_PSOR +#define CORE_PIN18_PORTSET GPIOB_PSOR +#define CORE_PIN19_PORTSET GPIOB_PSOR +#define CORE_PIN20_PORTSET GPIOD_PSOR +#define CORE_PIN21_PORTSET GPIOD_PSOR +#define CORE_PIN22_PORTSET GPIOC_PSOR +#define CORE_PIN23_PORTSET GPIOC_PSOR +#define CORE_PIN24_PORTSET GPIOE_PSOR +#define CORE_PIN25_PORTSET GPIOA_PSOR +#define CORE_PIN26_PORTSET GPIOA_PSOR +#define CORE_PIN27_PORTSET GPIOA_PSOR +#define CORE_PIN28_PORTSET GPIOA_PSOR +#define CORE_PIN29_PORTSET GPIOB_PSOR +#define CORE_PIN30_PORTSET GPIOB_PSOR +#define CORE_PIN31_PORTSET GPIOB_PSOR +#define CORE_PIN32_PORTSET GPIOB_PSOR +#define CORE_PIN33_PORTSET GPIOE_PSOR +#define CORE_PIN34_PORTSET GPIOE_PSOR +#define CORE_PIN35_PORTSET GPIOC_PSOR +#define CORE_PIN36_PORTSET GPIOC_PSOR +#define CORE_PIN37_PORTSET GPIOC_PSOR +#define CORE_PIN38_PORTSET GPIOC_PSOR +#define CORE_PIN39_PORTSET GPIOA_PSOR +#define CORE_PIN40_PORTSET GPIOA_PSOR +#define CORE_PIN41_PORTSET GPIOA_PSOR +#define CORE_PIN42_PORTSET GPIOA_PSOR +#define CORE_PIN43_PORTSET GPIOB_PSOR +#define CORE_PIN44_PORTSET GPIOB_PSOR +#define CORE_PIN45_PORTSET GPIOB_PSOR +#define CORE_PIN46_PORTSET GPIOB_PSOR +#define CORE_PIN47_PORTSET GPIOD_PSOR +#define CORE_PIN48_PORTSET GPIOD_PSOR +#define CORE_PIN49_PORTSET GPIOB_PSOR +#define CORE_PIN50_PORTSET GPIOB_PSOR +#define CORE_PIN51_PORTSET GPIOD_PSOR +#define CORE_PIN52_PORTSET GPIOD_PSOR +#define CORE_PIN53_PORTSET GPIOD_PSOR +#define CORE_PIN54_PORTSET GPIOD_PSOR +#define CORE_PIN55_PORTSET GPIOD_PSOR +#define CORE_PIN56_PORTSET GPIOE_PSOR +#define CORE_PIN57_PORTSET GPIOE_PSOR +#define CORE_PIN58_PORTSET GPIOE_PSOR +#define CORE_PIN59_PORTSET GPIOE_PSOR +#define CORE_PIN60_PORTSET GPIOE_PSOR +#define CORE_PIN61_PORTSET GPIOE_PSOR +#define CORE_PIN62_PORTSET GPIOE_PSOR +#define CORE_PIN63_PORTSET GPIOE_PSOR +// tranZPUter v2.2 additional pins. +#define CORE_PIN64_PORTSET GPIOC_PSOR // PTC12 +#define CORE_PIN65_PORTSET GPIOC_PSOR // PTC13 +#define CORE_PIN66_PORTSET GPIOC_PSOR // PTC14 +#define CORE_PIN67_PORTSET GPIOC_PSOR // PTC15 +#define CORE_PIN68_PORTSET GPIOC_PSOR // PTC16 +#define CORE_PIN69_PORTSET GPIOC_PSOR // PTC17 +#define CORE_PIN70_PORTSET GPIOC_PSOR // PTC18 +#define CORE_PIN71_PORTSET GPIOB_PSOR // PTB9 -#define CORE_PIN0_PINREG GPIOB_PDIR -#define CORE_PIN1_PINREG GPIOB_PDIR -#define CORE_PIN2_PINREG GPIOD_PDIR -#define CORE_PIN3_PINREG GPIOA_PDIR -#define CORE_PIN4_PINREG GPIOA_PDIR -#define CORE_PIN5_PINREG GPIOD_PDIR -#define CORE_PIN6_PINREG GPIOD_PDIR -#define CORE_PIN7_PINREG GPIOD_PDIR -#define CORE_PIN8_PINREG GPIOD_PDIR -#define CORE_PIN9_PINREG GPIOC_PDIR -#define CORE_PIN10_PINREG GPIOC_PDIR -#define CORE_PIN11_PINREG GPIOC_PDIR -#define CORE_PIN12_PINREG GPIOC_PDIR -#define CORE_PIN13_PINREG GPIOC_PDIR -#define CORE_PIN14_PINREG GPIOD_PDIR -#define CORE_PIN15_PINREG GPIOC_PDIR -#define CORE_PIN16_PINREG GPIOB_PDIR -#define CORE_PIN17_PINREG GPIOB_PDIR -#define CORE_PIN18_PINREG GPIOB_PDIR -#define CORE_PIN19_PINREG GPIOB_PDIR -#define CORE_PIN20_PINREG GPIOD_PDIR -#define CORE_PIN21_PINREG GPIOD_PDIR -#define CORE_PIN22_PINREG GPIOC_PDIR -#define CORE_PIN23_PINREG GPIOC_PDIR -#define CORE_PIN24_PINREG GPIOE_PDIR -#define CORE_PIN25_PINREG GPIOA_PDIR -#define CORE_PIN26_PINREG GPIOA_PDIR -#define CORE_PIN27_PINREG GPIOA_PDIR -#define CORE_PIN28_PINREG GPIOA_PDIR -#define CORE_PIN29_PINREG GPIOB_PDIR -#define CORE_PIN30_PINREG GPIOB_PDIR -#define CORE_PIN31_PINREG GPIOB_PDIR -#define CORE_PIN32_PINREG GPIOB_PDIR -#define CORE_PIN33_PINREG GPIOE_PDIR -#define CORE_PIN34_PINREG GPIOE_PDIR -#define CORE_PIN35_PINREG GPIOC_PDIR -#define CORE_PIN36_PINREG GPIOC_PDIR -#define CORE_PIN37_PINREG GPIOC_PDIR -#define CORE_PIN38_PINREG GPIOC_PDIR -#define CORE_PIN39_PINREG GPIOA_PDIR -#define CORE_PIN40_PINREG GPIOA_PDIR -#define CORE_PIN41_PINREG GPIOA_PDIR -#define CORE_PIN42_PINREG GPIOA_PDIR -#define CORE_PIN43_PINREG GPIOB_PDIR -#define CORE_PIN44_PINREG GPIOB_PDIR -#define CORE_PIN45_PINREG GPIOB_PDIR -#define CORE_PIN46_PINREG GPIOB_PDIR -#define CORE_PIN47_PINREG GPIOD_PDIR -#define CORE_PIN48_PINREG GPIOD_PDIR -#define CORE_PIN49_PINREG GPIOB_PDIR -#define CORE_PIN50_PINREG GPIOB_PDIR -#define CORE_PIN51_PINREG GPIOD_PDIR -#define CORE_PIN52_PINREG GPIOD_PDIR -#define CORE_PIN53_PINREG GPIOD_PDIR -#define CORE_PIN54_PINREG GPIOD_PDIR -#define CORE_PIN55_PINREG GPIOD_PDIR -#define CORE_PIN56_PINREG GPIOE_PDIR -#define CORE_PIN57_PINREG GPIOE_PDIR -#define CORE_PIN58_PINREG GPIOE_PDIR -#define CORE_PIN59_PINREG GPIOE_PDIR -#define CORE_PIN60_PINREG GPIOE_PDIR -#define CORE_PIN61_PINREG GPIOE_PDIR -#define CORE_PIN62_PINREG GPIOE_PDIR -#define CORE_PIN63_PINREG GPIOE_PDIR +#define CORE_PIN0_PORTCLEAR GPIOB_PCOR +#define CORE_PIN1_PORTCLEAR GPIOB_PCOR +#define CORE_PIN2_PORTCLEAR GPIOD_PCOR +#define CORE_PIN3_PORTCLEAR GPIOA_PCOR +#define CORE_PIN4_PORTCLEAR GPIOA_PCOR +#define CORE_PIN5_PORTCLEAR GPIOD_PCOR +#define CORE_PIN6_PORTCLEAR GPIOD_PCOR +#define CORE_PIN7_PORTCLEAR GPIOD_PCOR +#define CORE_PIN8_PORTCLEAR GPIOD_PCOR +#define CORE_PIN9_PORTCLEAR GPIOC_PCOR +#define CORE_PIN10_PORTCLEAR GPIOC_PCOR +#define CORE_PIN11_PORTCLEAR GPIOC_PCOR +#define CORE_PIN12_PORTCLEAR GPIOC_PCOR +#define CORE_PIN13_PORTCLEAR GPIOC_PCOR +#define CORE_PIN14_PORTCLEAR GPIOD_PCOR +#define CORE_PIN15_PORTCLEAR GPIOC_PCOR +#define CORE_PIN16_PORTCLEAR GPIOB_PCOR +#define CORE_PIN17_PORTCLEAR GPIOB_PCOR +#define CORE_PIN18_PORTCLEAR GPIOB_PCOR +#define CORE_PIN19_PORTCLEAR GPIOB_PCOR +#define CORE_PIN20_PORTCLEAR GPIOD_PCOR +#define CORE_PIN21_PORTCLEAR GPIOD_PCOR +#define CORE_PIN22_PORTCLEAR GPIOC_PCOR +#define CORE_PIN23_PORTCLEAR GPIOC_PCOR +#define CORE_PIN24_PORTCLEAR GPIOE_PCOR +#define CORE_PIN25_PORTCLEAR GPIOA_PCOR +#define CORE_PIN26_PORTCLEAR GPIOA_PCOR +#define CORE_PIN27_PORTCLEAR GPIOA_PCOR +#define CORE_PIN28_PORTCLEAR GPIOA_PCOR +#define CORE_PIN29_PORTCLEAR GPIOB_PCOR +#define CORE_PIN30_PORTCLEAR GPIOB_PCOR +#define CORE_PIN31_PORTCLEAR GPIOB_PCOR +#define CORE_PIN32_PORTCLEAR GPIOB_PCOR +#define CORE_PIN33_PORTCLEAR GPIOE_PCOR +#define CORE_PIN34_PORTCLEAR GPIOE_PCOR +#define CORE_PIN35_PORTCLEAR GPIOC_PCOR +#define CORE_PIN36_PORTCLEAR GPIOC_PCOR +#define CORE_PIN37_PORTCLEAR GPIOC_PCOR +#define CORE_PIN38_PORTCLEAR GPIOC_PCOR +#define CORE_PIN39_PORTCLEAR GPIOA_PCOR +#define CORE_PIN40_PORTCLEAR GPIOA_PCOR +#define CORE_PIN41_PORTCLEAR GPIOA_PCOR +#define CORE_PIN42_PORTCLEAR GPIOA_PCOR +#define CORE_PIN43_PORTCLEAR GPIOB_PCOR +#define CORE_PIN44_PORTCLEAR GPIOB_PCOR +#define CORE_PIN45_PORTCLEAR GPIOB_PCOR +#define CORE_PIN46_PORTCLEAR GPIOB_PCOR +#define CORE_PIN47_PORTCLEAR GPIOD_PCOR +#define CORE_PIN48_PORTCLEAR GPIOD_PCOR +#define CORE_PIN49_PORTCLEAR GPIOB_PCOR +#define CORE_PIN50_PORTCLEAR GPIOB_PCOR +#define CORE_PIN51_PORTCLEAR GPIOD_PCOR +#define CORE_PIN52_PORTCLEAR GPIOD_PCOR +#define CORE_PIN53_PORTCLEAR GPIOD_PCOR +#define CORE_PIN54_PORTCLEAR GPIOD_PCOR +#define CORE_PIN55_PORTCLEAR GPIOD_PCOR +#define CORE_PIN56_PORTCLEAR GPIOE_PCOR +#define CORE_PIN57_PORTCLEAR GPIOE_PCOR +#define CORE_PIN58_PORTCLEAR GPIOE_PCOR +#define CORE_PIN59_PORTCLEAR GPIOE_PCOR +#define CORE_PIN60_PORTCLEAR GPIOE_PCOR +#define CORE_PIN61_PORTCLEAR GPIOE_PCOR +#define CORE_PIN62_PORTCLEAR GPIOE_PCOR +#define CORE_PIN63_PORTCLEAR GPIOE_PCOR +// tranZPUter v2.2 additional pins. +#define CORE_PIN64_PORTCLEAR GPIOC_PCOR // PTC12 +#define CORE_PIN65_PORTCLEAR GPIOC_PCOR // PTC13 +#define CORE_PIN66_PORTCLEAR GPIOC_PCOR // PTC14 +#define CORE_PIN67_PORTCLEAR GPIOC_PCOR // PTC15 +#define CORE_PIN68_PORTCLEAR GPIOC_PCOR // PTC16 +#define CORE_PIN69_PORTCLEAR GPIOC_PCOR // PTC17 +#define CORE_PIN70_PORTCLEAR GPIOC_PCOR // PTC18 +#define CORE_PIN71_PORTCLEAR GPIOB_PCOR // PTB9 -#define CORE_PIN0_CONFIG PORTB_PCR16 -#define CORE_PIN1_CONFIG PORTB_PCR17 -#define CORE_PIN2_CONFIG PORTD_PCR0 -#define CORE_PIN3_CONFIG PORTA_PCR12 -#define CORE_PIN4_CONFIG PORTA_PCR13 -#define CORE_PIN5_CONFIG PORTD_PCR7 -#define CORE_PIN6_CONFIG PORTD_PCR4 -#define CORE_PIN7_CONFIG PORTD_PCR2 -#define CORE_PIN8_CONFIG PORTD_PCR3 -#define CORE_PIN9_CONFIG PORTC_PCR3 -#define CORE_PIN10_CONFIG PORTC_PCR4 -#define CORE_PIN11_CONFIG PORTC_PCR6 -#define CORE_PIN12_CONFIG PORTC_PCR7 -#define CORE_PIN13_CONFIG PORTC_PCR5 -#define CORE_PIN14_CONFIG PORTD_PCR1 -#define CORE_PIN15_CONFIG PORTC_PCR0 -#define CORE_PIN16_CONFIG PORTB_PCR0 -#define CORE_PIN17_CONFIG PORTB_PCR1 -#define CORE_PIN18_CONFIG PORTB_PCR3 -#define CORE_PIN19_CONFIG PORTB_PCR2 -#define CORE_PIN20_CONFIG PORTD_PCR5 -#define CORE_PIN21_CONFIG PORTD_PCR6 -#define CORE_PIN22_CONFIG PORTC_PCR1 -#define CORE_PIN23_CONFIG PORTC_PCR2 -#define CORE_PIN24_CONFIG PORTE_PCR26 -#define CORE_PIN25_CONFIG PORTA_PCR5 -#define CORE_PIN26_CONFIG PORTA_PCR14 -#define CORE_PIN27_CONFIG PORTA_PCR15 -#define CORE_PIN28_CONFIG PORTA_PCR16 -#define CORE_PIN29_CONFIG PORTB_PCR18 -#define CORE_PIN30_CONFIG PORTB_PCR19 -#define CORE_PIN31_CONFIG PORTB_PCR10 -#define CORE_PIN32_CONFIG PORTB_PCR11 -#define CORE_PIN33_CONFIG PORTE_PCR24 -#define CORE_PIN34_CONFIG PORTE_PCR25 -#define CORE_PIN35_CONFIG PORTC_PCR8 -#define CORE_PIN36_CONFIG PORTC_PCR9 -#define CORE_PIN37_CONFIG PORTC_PCR10 -#define CORE_PIN38_CONFIG PORTC_PCR11 -#define CORE_PIN39_CONFIG PORTA_PCR17 -#define CORE_PIN40_CONFIG PORTA_PCR28 -#define CORE_PIN41_CONFIG PORTA_PCR29 -#define CORE_PIN42_CONFIG PORTA_PCR26 -#define CORE_PIN43_CONFIG PORTB_PCR20 -#define CORE_PIN44_CONFIG PORTB_PCR22 -#define CORE_PIN45_CONFIG PORTB_PCR23 -#define CORE_PIN46_CONFIG PORTB_PCR21 -#define CORE_PIN47_CONFIG PORTD_PCR8 -#define CORE_PIN48_CONFIG PORTD_PCR9 -#define CORE_PIN49_CONFIG PORTB_PCR4 -#define CORE_PIN50_CONFIG PORTB_PCR5 -#define CORE_PIN51_CONFIG PORTD_PCR14 -#define CORE_PIN52_CONFIG PORTD_PCR13 -#define CORE_PIN53_CONFIG PORTD_PCR12 -#define CORE_PIN54_CONFIG PORTD_PCR15 -#define CORE_PIN55_CONFIG PORTD_PCR11 -#define CORE_PIN56_CONFIG PORTE_PCR10 -#define CORE_PIN57_CONFIG PORTE_PCR11 -#define CORE_PIN58_CONFIG PORTE_PCR0 -#define CORE_PIN59_CONFIG PORTE_PCR1 -#define CORE_PIN60_CONFIG PORTE_PCR2 -#define CORE_PIN61_CONFIG PORTE_PCR3 -#define CORE_PIN62_CONFIG PORTE_PCR4 -#define CORE_PIN63_CONFIG PORTE_PCR5 +#define CORE_PIN0_DDRREG GPIOB_PDDR +#define CORE_PIN1_DDRREG GPIOB_PDDR +#define CORE_PIN2_DDRREG GPIOD_PDDR +#define CORE_PIN3_DDRREG GPIOA_PDDR +#define CORE_PIN4_DDRREG GPIOA_PDDR +#define CORE_PIN5_DDRREG GPIOD_PDDR +#define CORE_PIN6_DDRREG GPIOD_PDDR +#define CORE_PIN7_DDRREG GPIOD_PDDR +#define CORE_PIN8_DDRREG GPIOD_PDDR +#define CORE_PIN9_DDRREG GPIOC_PDDR +#define CORE_PIN10_DDRREG GPIOC_PDDR +#define CORE_PIN11_DDRREG GPIOC_PDDR +#define CORE_PIN12_DDRREG GPIOC_PDDR +#define CORE_PIN13_DDRREG GPIOC_PDDR +#define CORE_PIN14_DDRREG GPIOD_PDDR +#define CORE_PIN15_DDRREG GPIOC_PDDR +#define CORE_PIN16_DDRREG GPIOB_PDDR +#define CORE_PIN17_DDRREG GPIOB_PDDR +#define CORE_PIN18_DDRREG GPIOB_PDDR +#define CORE_PIN19_DDRREG GPIOB_PDDR +#define CORE_PIN20_DDRREG GPIOD_PDDR +#define CORE_PIN21_DDRREG GPIOD_PDDR +#define CORE_PIN22_DDRREG GPIOC_PDDR +#define CORE_PIN23_DDRREG GPIOC_PDDR +#define CORE_PIN24_DDRREG GPIOE_PDDR +#define CORE_PIN25_DDRREG GPIOA_PDDR +#define CORE_PIN26_DDRREG GPIOA_PDDR +#define CORE_PIN27_DDRREG GPIOA_PDDR +#define CORE_PIN28_DDRREG GPIOA_PDDR +#define CORE_PIN29_DDRREG GPIOB_PDDR +#define CORE_PIN30_DDRREG GPIOB_PDDR +#define CORE_PIN31_DDRREG GPIOB_PDDR +#define CORE_PIN32_DDRREG GPIOB_PDDR +#define CORE_PIN33_DDRREG GPIOE_PDDR +#define CORE_PIN34_DDRREG GPIOE_PDDR +#define CORE_PIN35_DDRREG GPIOC_PDDR +#define CORE_PIN36_DDRREG GPIOC_PDDR +#define CORE_PIN37_DDRREG GPIOC_PDDR +#define CORE_PIN38_DDRREG GPIOC_PDDR +#define CORE_PIN39_DDRREG GPIOA_PDDR +#define CORE_PIN40_DDRREG GPIOA_PDDR +#define CORE_PIN41_DDRREG GPIOA_PDDR +#define CORE_PIN42_DDRREG GPIOA_PDDR +#define CORE_PIN43_DDRREG GPIOB_PDDR +#define CORE_PIN44_DDRREG GPIOB_PDDR +#define CORE_PIN45_DDRREG GPIOB_PDDR +#define CORE_PIN46_DDRREG GPIOB_PDDR +#define CORE_PIN47_DDRREG GPIOD_PDDR +#define CORE_PIN48_DDRREG GPIOD_PDDR +#define CORE_PIN49_DDRREG GPIOB_PDDR +#define CORE_PIN50_DDRREG GPIOB_PDDR +#define CORE_PIN51_DDRREG GPIOD_PDDR +#define CORE_PIN52_DDRREG GPIOD_PDDR +#define CORE_PIN53_DDRREG GPIOD_PDDR +#define CORE_PIN54_DDRREG GPIOD_PDDR +#define CORE_PIN55_DDRREG GPIOD_PDDR +#define CORE_PIN56_DDRREG GPIOE_PDDR +#define CORE_PIN57_DDRREG GPIOE_PDDR +#define CORE_PIN58_DDRREG GPIOE_PDDR +#define CORE_PIN59_DDRREG GPIOE_PDDR +#define CORE_PIN60_DDRREG GPIOE_PDDR +#define CORE_PIN61_DDRREG GPIOE_PDDR +#define CORE_PIN62_DDRREG GPIOE_PDDR +#define CORE_PIN63_DDRREG GPIOE_PDDR +// tranZPUter v2.2 additional pins. +#define CORE_PIN64_DDRREG GPIOC_PDDR // PTC12 +#define CORE_PIN65_DDRREG GPIOC_PDDR // PTC13 +#define CORE_PIN66_DDRREG GPIOC_PDDR // PTC14 +#define CORE_PIN67_DDRREG GPIOC_PDDR // PTC15 +#define CORE_PIN68_DDRREG GPIOC_PDDR // PTC16 +#define CORE_PIN69_DDRREG GPIOC_PDDR // PTC17 +#define CORE_PIN70_DDRREG GPIOC_PDDR // PTC18 +#define CORE_PIN71_DDRREG GPIOB_PDDR // PTB9 -#define CORE_ADC0_PIN 14 -#define CORE_ADC1_PIN 15 -#define CORE_ADC2_PIN 16 -#define CORE_ADC3_PIN 17 -#define CORE_ADC4_PIN 18 -#define CORE_ADC5_PIN 19 -#define CORE_ADC6_PIN 20 -#define CORE_ADC7_PIN 21 -#define CORE_ADC8_PIN 22 -#define CORE_ADC9_PIN 23 -#define CORE_ADC10_PIN 64 -#define CORE_ADC11_PIN 65 -#define CORE_ADC12_PIN 31 -#define CORE_ADC13_PIN 32 -#define CORE_ADC14_PIN 33 -#define CORE_ADC15_PIN 34 -#define CORE_ADC16_PIN 35 -#define CORE_ADC17_PIN 36 -#define CORE_ADC18_PIN 37 -#define CORE_ADC19_PIN 38 -#define CORE_ADC20_PIN 39 -#define CORE_ADC21_PIN 66 -#define CORE_ADC22_PIN 67 -#define CORE_ADC23_PIN 49 -#define CORE_ADC24_PIN 50 -#define CORE_ADC25_PIN 68 -#define CORE_ADC26_PIN 69 +#define CORE_PIN0_PINREG GPIOB_PDIR +#define CORE_PIN1_PINREG GPIOB_PDIR +#define CORE_PIN2_PINREG GPIOD_PDIR +#define CORE_PIN3_PINREG GPIOA_PDIR +#define CORE_PIN4_PINREG GPIOA_PDIR +#define CORE_PIN5_PINREG GPIOD_PDIR +#define CORE_PIN6_PINREG GPIOD_PDIR +#define CORE_PIN7_PINREG GPIOD_PDIR +#define CORE_PIN8_PINREG GPIOD_PDIR +#define CORE_PIN9_PINREG GPIOC_PDIR +#define CORE_PIN10_PINREG GPIOC_PDIR +#define CORE_PIN11_PINREG GPIOC_PDIR +#define CORE_PIN12_PINREG GPIOC_PDIR +#define CORE_PIN13_PINREG GPIOC_PDIR +#define CORE_PIN14_PINREG GPIOD_PDIR +#define CORE_PIN15_PINREG GPIOC_PDIR +#define CORE_PIN16_PINREG GPIOB_PDIR +#define CORE_PIN17_PINREG GPIOB_PDIR +#define CORE_PIN18_PINREG GPIOB_PDIR +#define CORE_PIN19_PINREG GPIOB_PDIR +#define CORE_PIN20_PINREG GPIOD_PDIR +#define CORE_PIN21_PINREG GPIOD_PDIR +#define CORE_PIN22_PINREG GPIOC_PDIR +#define CORE_PIN23_PINREG GPIOC_PDIR +#define CORE_PIN24_PINREG GPIOE_PDIR +#define CORE_PIN25_PINREG GPIOA_PDIR +#define CORE_PIN26_PINREG GPIOA_PDIR +#define CORE_PIN27_PINREG GPIOA_PDIR +#define CORE_PIN28_PINREG GPIOA_PDIR +#define CORE_PIN29_PINREG GPIOB_PDIR +#define CORE_PIN30_PINREG GPIOB_PDIR +#define CORE_PIN31_PINREG GPIOB_PDIR +#define CORE_PIN32_PINREG GPIOB_PDIR +#define CORE_PIN33_PINREG GPIOE_PDIR +#define CORE_PIN34_PINREG GPIOE_PDIR +#define CORE_PIN35_PINREG GPIOC_PDIR +#define CORE_PIN36_PINREG GPIOC_PDIR +#define CORE_PIN37_PINREG GPIOC_PDIR +#define CORE_PIN38_PINREG GPIOC_PDIR +#define CORE_PIN39_PINREG GPIOA_PDIR +#define CORE_PIN40_PINREG GPIOA_PDIR +#define CORE_PIN41_PINREG GPIOA_PDIR +#define CORE_PIN42_PINREG GPIOA_PDIR +#define CORE_PIN43_PINREG GPIOB_PDIR +#define CORE_PIN44_PINREG GPIOB_PDIR +#define CORE_PIN45_PINREG GPIOB_PDIR +#define CORE_PIN46_PINREG GPIOB_PDIR +#define CORE_PIN47_PINREG GPIOD_PDIR +#define CORE_PIN48_PINREG GPIOD_PDIR +#define CORE_PIN49_PINREG GPIOB_PDIR +#define CORE_PIN50_PINREG GPIOB_PDIR +#define CORE_PIN51_PINREG GPIOD_PDIR +#define CORE_PIN52_PINREG GPIOD_PDIR +#define CORE_PIN53_PINREG GPIOD_PDIR +#define CORE_PIN54_PINREG GPIOD_PDIR +#define CORE_PIN55_PINREG GPIOD_PDIR +#define CORE_PIN56_PINREG GPIOE_PDIR +#define CORE_PIN57_PINREG GPIOE_PDIR +#define CORE_PIN58_PINREG GPIOE_PDIR +#define CORE_PIN59_PINREG GPIOE_PDIR +#define CORE_PIN60_PINREG GPIOE_PDIR +#define CORE_PIN61_PINREG GPIOE_PDIR +#define CORE_PIN62_PINREG GPIOE_PDIR +#define CORE_PIN63_PINREG GPIOE_PDIR +// tranZPUter v2.2 additional pins. +#define CORE_PIN64_PINREG GPIOC_PDIR // PTC12 +#define CORE_PIN65_PINREG GPIOC_PDIR // PTC13 +#define CORE_PIN66_PINREG GPIOC_PDIR // PTC14 +#define CORE_PIN67_PINREG GPIOC_PDIR // PTC15 +#define CORE_PIN68_PINREG GPIOC_PDIR // PTC16 +#define CORE_PIN69_PINREG GPIOC_PDIR // PTC17 +#define CORE_PIN70_PINREG GPIOC_PDIR // PTC18 +#define CORE_PIN71_PINREG GPIOB_PDIR // PTB9 -#define CORE_RXD0_PIN 0 -#define CORE_TXD0_PIN 1 -#define CORE_RXD1_PIN 9 -#define CORE_TXD1_PIN 10 -#define CORE_RXD2_PIN 7 -#define CORE_TXD2_PIN 8 -#define CORE_RXD3_PIN 31 -#define CORE_TXD3_PIN 32 -#define CORE_RXD4_PIN 34 -#define CORE_TXD4_PIN 33 +#define CORE_PIN0_CONFIG PORTB_PCR16 +#define CORE_PIN1_CONFIG PORTB_PCR17 +#define CORE_PIN2_CONFIG PORTD_PCR0 +#define CORE_PIN3_CONFIG PORTA_PCR12 +#define CORE_PIN4_CONFIG PORTA_PCR13 +#define CORE_PIN5_CONFIG PORTD_PCR7 +#define CORE_PIN6_CONFIG PORTD_PCR4 +#define CORE_PIN7_CONFIG PORTD_PCR2 +#define CORE_PIN8_CONFIG PORTD_PCR3 +#define CORE_PIN9_CONFIG PORTC_PCR3 +#define CORE_PIN10_CONFIG PORTC_PCR4 +#define CORE_PIN11_CONFIG PORTC_PCR6 +#define CORE_PIN12_CONFIG PORTC_PCR7 +#define CORE_PIN13_CONFIG PORTC_PCR5 +#define CORE_PIN14_CONFIG PORTD_PCR1 +#define CORE_PIN15_CONFIG PORTC_PCR0 +#define CORE_PIN16_CONFIG PORTB_PCR0 +#define CORE_PIN17_CONFIG PORTB_PCR1 +#define CORE_PIN18_CONFIG PORTB_PCR3 +#define CORE_PIN19_CONFIG PORTB_PCR2 +#define CORE_PIN20_CONFIG PORTD_PCR5 +#define CORE_PIN21_CONFIG PORTD_PCR6 +#define CORE_PIN22_CONFIG PORTC_PCR1 +#define CORE_PIN23_CONFIG PORTC_PCR2 +#define CORE_PIN24_CONFIG PORTE_PCR26 +#define CORE_PIN25_CONFIG PORTA_PCR5 +#define CORE_PIN26_CONFIG PORTA_PCR14 +#define CORE_PIN27_CONFIG PORTA_PCR15 +#define CORE_PIN28_CONFIG PORTA_PCR16 +#define CORE_PIN29_CONFIG PORTB_PCR18 +#define CORE_PIN30_CONFIG PORTB_PCR19 +#define CORE_PIN31_CONFIG PORTB_PCR10 +#define CORE_PIN32_CONFIG PORTB_PCR11 +#define CORE_PIN33_CONFIG PORTE_PCR24 +#define CORE_PIN34_CONFIG PORTE_PCR25 +#define CORE_PIN35_CONFIG PORTC_PCR8 +#define CORE_PIN36_CONFIG PORTC_PCR9 +#define CORE_PIN37_CONFIG PORTC_PCR10 +#define CORE_PIN38_CONFIG PORTC_PCR11 +#define CORE_PIN39_CONFIG PORTA_PCR17 +#define CORE_PIN40_CONFIG PORTA_PCR28 +#define CORE_PIN41_CONFIG PORTA_PCR29 +#define CORE_PIN42_CONFIG PORTA_PCR26 +#define CORE_PIN43_CONFIG PORTB_PCR20 +#define CORE_PIN44_CONFIG PORTB_PCR22 +#define CORE_PIN45_CONFIG PORTB_PCR23 +#define CORE_PIN46_CONFIG PORTB_PCR21 +#define CORE_PIN47_CONFIG PORTD_PCR8 +#define CORE_PIN48_CONFIG PORTD_PCR9 +#define CORE_PIN49_CONFIG PORTB_PCR4 +#define CORE_PIN50_CONFIG PORTB_PCR5 +#define CORE_PIN51_CONFIG PORTD_PCR14 +#define CORE_PIN52_CONFIG PORTD_PCR13 +#define CORE_PIN53_CONFIG PORTD_PCR12 +#define CORE_PIN54_CONFIG PORTD_PCR15 +#define CORE_PIN55_CONFIG PORTD_PCR11 +#define CORE_PIN56_CONFIG PORTE_PCR10 +#define CORE_PIN57_CONFIG PORTE_PCR11 +#define CORE_PIN58_CONFIG PORTE_PCR0 +#define CORE_PIN59_CONFIG PORTE_PCR1 +#define CORE_PIN60_CONFIG PORTE_PCR2 +#define CORE_PIN61_CONFIG PORTE_PCR3 +#define CORE_PIN62_CONFIG PORTE_PCR4 +#define CORE_PIN63_CONFIG PORTE_PCR5 +// tranZPUter v2.2 additional pins. +#define CORE_PIN64_CONFIG PORTC_PCR12 // PTC12 +#define CORE_PIN65_CONFIG PORTC_PCR13 // PTC13 +#define CORE_PIN66_CONFIG PORTC_PCR14 // PTC14 +#define CORE_PIN67_CONFIG PORTC_PCR15 // PTC15 +#define CORE_PIN68_CONFIG PORTC_PCR16 // PTC16 +#define CORE_PIN69_CONFIG PORTC_PCR17 // PTC17 +#define CORE_PIN70_CONFIG PORTC_PCR18 // PTC18 +#define CORE_PIN71_CONFIG PORTB_PCR9 // PTB9 -#define CORE_INT0_PIN 0 -#define CORE_INT1_PIN 1 -#define CORE_INT2_PIN 2 -#define CORE_INT3_PIN 3 -#define CORE_INT4_PIN 4 -#define CORE_INT5_PIN 5 -#define CORE_INT6_PIN 6 -#define CORE_INT7_PIN 7 -#define CORE_INT8_PIN 8 -#define CORE_INT9_PIN 9 -#define CORE_INT10_PIN 10 -#define CORE_INT11_PIN 11 -#define CORE_INT12_PIN 12 -#define CORE_INT13_PIN 13 -#define CORE_INT14_PIN 14 -#define CORE_INT15_PIN 15 -#define CORE_INT16_PIN 16 -#define CORE_INT17_PIN 17 -#define CORE_INT18_PIN 18 -#define CORE_INT19_PIN 19 -#define CORE_INT20_PIN 20 -#define CORE_INT21_PIN 21 -#define CORE_INT22_PIN 22 -#define CORE_INT23_PIN 23 -#define CORE_INT24_PIN 24 -#define CORE_INT25_PIN 25 -#define CORE_INT26_PIN 26 -#define CORE_INT27_PIN 27 -#define CORE_INT28_PIN 28 -#define CORE_INT29_PIN 29 -#define CORE_INT30_PIN 30 -#define CORE_INT31_PIN 31 -#define CORE_INT32_PIN 32 -#define CORE_INT33_PIN 33 -#define CORE_INT34_PIN 34 -#define CORE_INT35_PIN 35 -#define CORE_INT36_PIN 36 -#define CORE_INT37_PIN 37 -#define CORE_INT38_PIN 38 -#define CORE_INT39_PIN 39 -#define CORE_INT40_PIN 40 -#define CORE_INT41_PIN 41 -#define CORE_INT42_PIN 42 -#define CORE_INT43_PIN 43 -#define CORE_INT44_PIN 44 -#define CORE_INT45_PIN 45 -#define CORE_INT46_PIN 46 -#define CORE_INT47_PIN 47 -#define CORE_INT48_PIN 48 -#define CORE_INT49_PIN 49 -#define CORE_INT50_PIN 50 -#define CORE_INT51_PIN 51 -#define CORE_INT52_PIN 52 -#define CORE_INT53_PIN 53 -#define CORE_INT54_PIN 54 -#define CORE_INT55_PIN 55 -#define CORE_INT56_PIN 56 -#define CORE_INT57_PIN 57 -#define CORE_INT58_PIN 58 -#define CORE_INT59_PIN 59 -#define CORE_INT60_PIN 60 -#define CORE_INT61_PIN 61 -#define CORE_INT62_PIN 62 -#define CORE_INT63_PIN 63 -#define CORE_INT_EVERY_PIN 1 +#define CORE_ADC0_PIN 14 +#define CORE_ADC1_PIN 15 +#define CORE_ADC2_PIN 16 +#define CORE_ADC3_PIN 17 +#define CORE_ADC4_PIN 18 +#define CORE_ADC5_PIN 19 +#define CORE_ADC6_PIN 20 +#define CORE_ADC7_PIN 21 +#define CORE_ADC8_PIN 22 +#define CORE_ADC9_PIN 23 +#define CORE_ADC10_PIN 64 +#define CORE_ADC11_PIN 65 +#define CORE_ADC12_PIN 31 +#define CORE_ADC13_PIN 32 +#define CORE_ADC14_PIN 33 +#define CORE_ADC15_PIN 34 +#define CORE_ADC16_PIN 35 +#define CORE_ADC17_PIN 36 +#define CORE_ADC18_PIN 37 +#define CORE_ADC19_PIN 38 +#define CORE_ADC20_PIN 39 +#define CORE_ADC21_PIN 66 +#define CORE_ADC22_PIN 67 +#define CORE_ADC23_PIN 49 +#define CORE_ADC24_PIN 50 +#define CORE_ADC25_PIN 68 +#define CORE_ADC26_PIN 69 + +#define CORE_RXD0_PIN 0 +#define CORE_TXD0_PIN 1 +#define CORE_RXD1_PIN 9 +#define CORE_TXD1_PIN 10 +#define CORE_RXD2_PIN 7 +#define CORE_TXD2_PIN 8 +#define CORE_RXD3_PIN 31 +#define CORE_TXD3_PIN 32 +#define CORE_RXD4_PIN 34 +#define CORE_TXD4_PIN 33 + +#define CORE_INT0_PIN 0 +#define CORE_INT1_PIN 1 +#define CORE_INT2_PIN 2 +#define CORE_INT3_PIN 3 +#define CORE_INT4_PIN 4 +#define CORE_INT5_PIN 5 +#define CORE_INT6_PIN 6 +#define CORE_INT7_PIN 7 +#define CORE_INT8_PIN 8 +#define CORE_INT9_PIN 9 +#define CORE_INT10_PIN 10 +#define CORE_INT11_PIN 11 +#define CORE_INT12_PIN 12 +#define CORE_INT13_PIN 13 +#define CORE_INT14_PIN 14 +#define CORE_INT15_PIN 15 +#define CORE_INT16_PIN 16 +#define CORE_INT17_PIN 17 +#define CORE_INT18_PIN 18 +#define CORE_INT19_PIN 19 +#define CORE_INT20_PIN 20 +#define CORE_INT21_PIN 21 +#define CORE_INT22_PIN 22 +#define CORE_INT23_PIN 23 +#define CORE_INT24_PIN 24 +#define CORE_INT25_PIN 25 +#define CORE_INT26_PIN 26 +#define CORE_INT27_PIN 27 +#define CORE_INT28_PIN 28 +#define CORE_INT29_PIN 29 +#define CORE_INT30_PIN 30 +#define CORE_INT31_PIN 31 +#define CORE_INT32_PIN 32 +#define CORE_INT33_PIN 33 +#define CORE_INT34_PIN 34 +#define CORE_INT35_PIN 35 +#define CORE_INT36_PIN 36 +#define CORE_INT37_PIN 37 +#define CORE_INT38_PIN 38 +#define CORE_INT39_PIN 39 +#define CORE_INT40_PIN 40 +#define CORE_INT41_PIN 41 +#define CORE_INT42_PIN 42 +#define CORE_INT43_PIN 43 +#define CORE_INT44_PIN 44 +#define CORE_INT45_PIN 45 +#define CORE_INT46_PIN 46 +#define CORE_INT47_PIN 47 +#define CORE_INT48_PIN 48 +#define CORE_INT49_PIN 49 +#define CORE_INT50_PIN 50 +#define CORE_INT51_PIN 51 +#define CORE_INT52_PIN 52 +#define CORE_INT53_PIN 53 +#define CORE_INT54_PIN 54 +#define CORE_INT55_PIN 55 +#define CORE_INT56_PIN 56 +#define CORE_INT57_PIN 57 +#define CORE_INT58_PIN 58 +#define CORE_INT59_PIN 59 +#define CORE_INT60_PIN 60 +#define CORE_INT61_PIN 61 +#define CORE_INT62_PIN 62 +#define CORE_INT63_PIN 63 +// tranZPUter v2.2 additional pins. +#define CORE_INT64_PIN 64 // PTC12 +#define CORE_INT65_PIN 65 // PTC13 +#define CORE_INT66_PIN 66 // PTC14 +#define CORE_INT67_PIN 67 // PTC15 +#define CORE_INT68_PIN 68 // PTC16 +#define CORE_INT69_PIN 69 // PTC17 +#define CORE_INT70_PIN 70 // PTC18 +#define CORE_INT71_PIN 71 // PTB9 +// +#define CORE_INT_EVERY_PIN 1 #endif #if defined(__MK20DX128__) -#define CORE_FTM0_CH0_PIN 22 -#define CORE_FTM0_CH1_PIN 23 -#define CORE_FTM0_CH2_PIN 9 -#define CORE_FTM0_CH3_PIN 10 -#define CORE_FTM0_CH4_PIN 6 -#define CORE_FTM0_CH5_PIN 20 -#define CORE_FTM0_CH6_PIN 21 -#define CORE_FTM0_CH7_PIN 5 -#define CORE_FTM1_CH0_PIN 3 -#define CORE_FTM1_CH1_PIN 4 +#define CORE_FTM0_CH0_PIN 22 +#define CORE_FTM0_CH1_PIN 23 +#define CORE_FTM0_CH2_PIN 9 +#define CORE_FTM0_CH3_PIN 10 +#define CORE_FTM0_CH4_PIN 6 +#define CORE_FTM0_CH5_PIN 20 +#define CORE_FTM0_CH6_PIN 21 +#define CORE_FTM0_CH7_PIN 5 +#define CORE_FTM1_CH0_PIN 3 +#define CORE_FTM1_CH1_PIN 4 #elif defined(__MK20DX256__) -#define CORE_FTM0_CH0_PIN 22 -#define CORE_FTM0_CH1_PIN 23 -#define CORE_FTM0_CH2_PIN 9 -#define CORE_FTM0_CH3_PIN 10 -#define CORE_FTM0_CH4_PIN 6 -#define CORE_FTM0_CH5_PIN 20 -#define CORE_FTM0_CH6_PIN 21 -#define CORE_FTM0_CH7_PIN 5 -#define CORE_FTM1_CH0_PIN 3 -#define CORE_FTM1_CH1_PIN 4 -#define CORE_FTM2_CH0_PIN 32 -#define CORE_FTM2_CH1_PIN 25 +#define CORE_FTM0_CH0_PIN 22 +#define CORE_FTM0_CH1_PIN 23 +#define CORE_FTM0_CH2_PIN 9 +#define CORE_FTM0_CH3_PIN 10 +#define CORE_FTM0_CH4_PIN 6 +#define CORE_FTM0_CH5_PIN 20 +#define CORE_FTM0_CH6_PIN 21 +#define CORE_FTM0_CH7_PIN 5 +#define CORE_FTM1_CH0_PIN 3 +#define CORE_FTM1_CH1_PIN 4 +#define CORE_FTM2_CH0_PIN 32 +#define CORE_FTM2_CH1_PIN 25 #elif defined(__MKL26Z64__) -#define CORE_TPM0_CH0_PIN 22 -#define CORE_TPM0_CH1_PIN 23 -#define CORE_TPM0_CH2_PIN 9 -#define CORE_TPM0_CH3_PIN 10 -#define CORE_TPM0_CH4_PIN 6 -#define CORE_TPM0_CH5_PIN 20 -#define CORE_TPM1_CH0_PIN 16 -#define CORE_TPM1_CH1_PIN 17 -#define CORE_TPM2_CH0_PIN 3 -#define CORE_TPM2_CH1_PIN 4 +#define CORE_TPM0_CH0_PIN 22 +#define CORE_TPM0_CH1_PIN 23 +#define CORE_TPM0_CH2_PIN 9 +#define CORE_TPM0_CH3_PIN 10 +#define CORE_TPM0_CH4_PIN 6 +#define CORE_TPM0_CH5_PIN 20 +#define CORE_TPM1_CH0_PIN 16 +#define CORE_TPM1_CH1_PIN 17 +#define CORE_TPM2_CH0_PIN 3 +#define CORE_TPM2_CH1_PIN 4 #elif defined(__MK64FX512__) -#define CORE_FTM0_CH0_PIN 22 -#define CORE_FTM0_CH1_PIN 23 -#define CORE_FTM0_CH2_PIN 9 -#define CORE_FTM0_CH3_PIN 10 -#define CORE_FTM0_CH4_PIN 6 -#define CORE_FTM0_CH5_PIN 20 -#define CORE_FTM0_CH6_PIN 21 -#define CORE_FTM0_CH7_PIN 5 -#define CORE_FTM1_CH0_PIN 3 -#define CORE_FTM1_CH1_PIN 4 -#define CORE_FTM2_CH0_PIN 29 -#define CORE_FTM2_CH1_PIN 30 -#define CORE_FTM3_CH0_PIN 2 -#define CORE_FTM3_CH1_PIN 14 -#define CORE_FTM3_CH2_PIN 7 -#define CORE_FTM3_CH3_PIN 8 -#define CORE_FTM3_CH4_PIN 35 -#define CORE_FTM3_CH5_PIN 36 -#define CORE_FTM3_CH6_PIN 37 -#define CORE_FTM3_CH7_PIN 38 +#define CORE_FTM0_CH0_PIN 22 +#define CORE_FTM0_CH1_PIN 23 +#define CORE_FTM0_CH2_PIN 9 +#define CORE_FTM0_CH3_PIN 10 +#define CORE_FTM0_CH4_PIN 6 +#define CORE_FTM0_CH5_PIN 20 +#define CORE_FTM0_CH6_PIN 21 +#define CORE_FTM0_CH7_PIN 5 +#define CORE_FTM1_CH0_PIN 3 +#define CORE_FTM1_CH1_PIN 4 +#define CORE_FTM2_CH0_PIN 29 +#define CORE_FTM2_CH1_PIN 30 +#define CORE_FTM3_CH0_PIN 2 +#define CORE_FTM3_CH1_PIN 14 +#define CORE_FTM3_CH2_PIN 7 +#define CORE_FTM3_CH3_PIN 8 +#define CORE_FTM3_CH4_PIN 35 +#define CORE_FTM3_CH5_PIN 36 +#define CORE_FTM3_CH6_PIN 37 +#define CORE_FTM3_CH7_PIN 38 #elif defined(__MK66FX1M0__) -#define CORE_FTM0_CH0_PIN 22 -#define CORE_FTM0_CH1_PIN 23 -#define CORE_FTM0_CH2_PIN 9 -#define CORE_FTM0_CH3_PIN 10 -#define CORE_FTM0_CH4_PIN 6 -#define CORE_FTM0_CH5_PIN 20 -#define CORE_FTM0_CH6_PIN 21 -#define CORE_FTM0_CH7_PIN 5 -#define CORE_FTM1_CH0_PIN 3 -#define CORE_FTM1_CH1_PIN 4 -#define CORE_FTM2_CH0_PIN 29 -#define CORE_FTM2_CH1_PIN 30 -#define CORE_FTM3_CH0_PIN 2 -#define CORE_FTM3_CH1_PIN 14 -#define CORE_FTM3_CH2_PIN 7 -#define CORE_FTM3_CH3_PIN 8 -#define CORE_FTM3_CH4_PIN 35 -#define CORE_FTM3_CH5_PIN 36 -#define CORE_FTM3_CH6_PIN 37 -#define CORE_FTM3_CH7_PIN 38 -#define CORE_TPM1_CH0_PIN 16 -#define CORE_TPM1_CH1_PIN 17 +#define CORE_FTM0_CH0_PIN 22 +#define CORE_FTM0_CH1_PIN 23 +#define CORE_FTM0_CH2_PIN 9 +#define CORE_FTM0_CH3_PIN 10 +#define CORE_FTM0_CH4_PIN 6 +#define CORE_FTM0_CH5_PIN 20 +#define CORE_FTM0_CH6_PIN 21 +#define CORE_FTM0_CH7_PIN 5 +#define CORE_FTM1_CH0_PIN 3 +#define CORE_FTM1_CH1_PIN 4 +#define CORE_FTM2_CH0_PIN 29 +#define CORE_FTM2_CH1_PIN 30 +#define CORE_FTM3_CH0_PIN 2 +#define CORE_FTM3_CH1_PIN 14 +#define CORE_FTM3_CH2_PIN 7 +#define CORE_FTM3_CH3_PIN 8 +#define CORE_FTM3_CH4_PIN 35 +#define CORE_FTM3_CH5_PIN 36 +#define CORE_FTM3_CH6_PIN 37 +#define CORE_FTM3_CH7_PIN 38 +#define CORE_TPM1_CH0_PIN 16 +#define CORE_TPM1_CH1_PIN 17 #endif @@ -1479,439 +1563,499 @@ void digitalWrite(uint8_t pin, uint8_t val); static inline void digitalWriteFast(uint8_t pin, uint8_t val) __attribute__((always_inline, unused)); static inline void digitalWriteFast(uint8_t pin, uint8_t val) { - if (__builtin_constant_p(pin)) { - if (val) { - if (pin == 0) { - CORE_PIN0_PORTSET = CORE_PIN0_BITMASK; - } else if (pin == 1) { - CORE_PIN1_PORTSET = CORE_PIN1_BITMASK; - } else if (pin == 2) { - CORE_PIN2_PORTSET = CORE_PIN2_BITMASK; - } else if (pin == 3) { - CORE_PIN3_PORTSET = CORE_PIN3_BITMASK; - } else if (pin == 4) { - CORE_PIN4_PORTSET = CORE_PIN4_BITMASK; - } else if (pin == 5) { - CORE_PIN5_PORTSET = CORE_PIN5_BITMASK; - } else if (pin == 6) { - CORE_PIN6_PORTSET = CORE_PIN6_BITMASK; - } else if (pin == 7) { - CORE_PIN7_PORTSET = CORE_PIN7_BITMASK; - } else if (pin == 8) { - CORE_PIN8_PORTSET = CORE_PIN8_BITMASK; - } else if (pin == 9) { - CORE_PIN9_PORTSET = CORE_PIN9_BITMASK; - } else if (pin == 10) { - CORE_PIN10_PORTSET = CORE_PIN10_BITMASK; - } else if (pin == 11) { - CORE_PIN11_PORTSET = CORE_PIN11_BITMASK; - } else if (pin == 12) { - CORE_PIN12_PORTSET = CORE_PIN12_BITMASK; - } else if (pin == 13) { - CORE_PIN13_PORTSET = CORE_PIN13_BITMASK; - } else if (pin == 14) { - CORE_PIN14_PORTSET = CORE_PIN14_BITMASK; - } else if (pin == 15) { - CORE_PIN15_PORTSET = CORE_PIN15_BITMASK; - } else if (pin == 16) { - CORE_PIN16_PORTSET = CORE_PIN16_BITMASK; - } else if (pin == 17) { - CORE_PIN17_PORTSET = CORE_PIN17_BITMASK; - } else if (pin == 18) { - CORE_PIN18_PORTSET = CORE_PIN18_BITMASK; - } else if (pin == 19) { - CORE_PIN19_PORTSET = CORE_PIN19_BITMASK; - } else if (pin == 20) { - CORE_PIN20_PORTSET = CORE_PIN20_BITMASK; - } else if (pin == 21) { - CORE_PIN21_PORTSET = CORE_PIN21_BITMASK; - } else if (pin == 22) { - CORE_PIN22_PORTSET = CORE_PIN22_BITMASK; - } else if (pin == 23) { - CORE_PIN23_PORTSET = CORE_PIN23_BITMASK; - } else if (pin == 24) { - CORE_PIN24_PORTSET = CORE_PIN24_BITMASK; - } else if (pin == 25) { - CORE_PIN25_PORTSET = CORE_PIN25_BITMASK; - } else if (pin == 26) { - CORE_PIN26_PORTSET = CORE_PIN26_BITMASK; - } - #if defined(CORE_PIN27_PORTSET) - else if (pin == 27) { - CORE_PIN27_PORTSET = CORE_PIN27_BITMASK; - } else if (pin == 28) { - CORE_PIN28_PORTSET = CORE_PIN28_BITMASK; - } else if (pin == 29) { - CORE_PIN29_PORTSET = CORE_PIN29_BITMASK; - } else if (pin == 30) { - CORE_PIN30_PORTSET = CORE_PIN30_BITMASK; - } else if (pin == 31) { - CORE_PIN31_PORTSET = CORE_PIN31_BITMASK; - } else if (pin == 32) { - CORE_PIN32_PORTSET = CORE_PIN32_BITMASK; - } else if (pin == 33) { - CORE_PIN33_PORTSET = CORE_PIN33_BITMASK; - } - #endif - #if defined(CORE_PIN34_PORTSET) - else if (pin == 34) { - CORE_PIN34_PORTSET = CORE_PIN34_BITMASK; - } else if (pin == 35) { - CORE_PIN35_PORTSET = CORE_PIN35_BITMASK; - } else if (pin == 36) { - CORE_PIN36_PORTSET = CORE_PIN36_BITMASK; - } else if (pin == 37) { - CORE_PIN37_PORTSET = CORE_PIN37_BITMASK; - } else if (pin == 38) { - CORE_PIN38_PORTSET = CORE_PIN38_BITMASK; - } else if (pin == 39) { - CORE_PIN39_PORTSET = CORE_PIN39_BITMASK; - } else if (pin == 40) { - CORE_PIN40_PORTSET = CORE_PIN40_BITMASK; - } else if (pin == 41) { - CORE_PIN41_PORTSET = CORE_PIN41_BITMASK; - } else if (pin == 42) { - CORE_PIN42_PORTSET = CORE_PIN42_BITMASK; - } else if (pin == 43) { - CORE_PIN43_PORTSET = CORE_PIN43_BITMASK; - } else if (pin == 44) { - CORE_PIN44_PORTSET = CORE_PIN44_BITMASK; - } else if (pin == 45) { - CORE_PIN45_PORTSET = CORE_PIN45_BITMASK; - } else if (pin == 46) { - CORE_PIN46_PORTSET = CORE_PIN46_BITMASK; - } else if (pin == 47) { - CORE_PIN47_PORTSET = CORE_PIN47_BITMASK; - } else if (pin == 48) { - CORE_PIN48_PORTSET = CORE_PIN48_BITMASK; - } else if (pin == 49) { - CORE_PIN49_PORTSET = CORE_PIN49_BITMASK; - } else if (pin == 50) { - CORE_PIN50_PORTSET = CORE_PIN50_BITMASK; - } else if (pin == 51) { - CORE_PIN51_PORTSET = CORE_PIN51_BITMASK; - } else if (pin == 52) { - CORE_PIN52_PORTSET = CORE_PIN52_BITMASK; - } else if (pin == 53) { - CORE_PIN53_PORTSET = CORE_PIN53_BITMASK; - } else if (pin == 54) { - CORE_PIN54_PORTSET = CORE_PIN54_BITMASK; - } else if (pin == 55) { - CORE_PIN55_PORTSET = CORE_PIN55_BITMASK; - } else if (pin == 56) { - CORE_PIN56_PORTSET = CORE_PIN56_BITMASK; - } else if (pin == 57) { - CORE_PIN57_PORTSET = CORE_PIN57_BITMASK; - } else if (pin == 58) { - CORE_PIN58_PORTSET = CORE_PIN58_BITMASK; - } else if (pin == 59) { - CORE_PIN59_PORTSET = CORE_PIN59_BITMASK; - } else if (pin == 60) { - CORE_PIN60_PORTSET = CORE_PIN60_BITMASK; - } else if (pin == 61) { - CORE_PIN61_PORTSET = CORE_PIN61_BITMASK; - } else if (pin == 62) { - CORE_PIN62_PORTSET = CORE_PIN62_BITMASK; - } else if (pin == 63) { - CORE_PIN63_PORTSET = CORE_PIN63_BITMASK; - } - #endif - } else { - if (pin == 0) { - CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK; - } else if (pin == 1) { - CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK; - } else if (pin == 2) { - CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK; - } else if (pin == 3) { - CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK; - } else if (pin == 4) { - CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK; - } else if (pin == 5) { - CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK; - } else if (pin == 6) { - CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK; - } else if (pin == 7) { - CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK; - } else if (pin == 8) { - CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK; - } else if (pin == 9) { - CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK; - } else if (pin == 10) { - CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK; - } else if (pin == 11) { - CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK; - } else if (pin == 12) { - CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK; - } else if (pin == 13) { - CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK; - } else if (pin == 14) { - CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK; - } else if (pin == 15) { - CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK; - } else if (pin == 16) { - CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK; - } else if (pin == 17) { - CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK; - } else if (pin == 18) { - CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK; - } else if (pin == 19) { - CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK; - } else if (pin == 20) { - CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK; - } else if (pin == 21) { - CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK; - } else if (pin == 22) { - CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK; - } else if (pin == 23) { - CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK; - } else if (pin == 24) { - CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK; - } else if (pin == 25) { - CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK; - } else if (pin == 26) { - CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK; - } - #if defined(CORE_PIN27_PORTCLEAR) - else if (pin == 27) { - CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK; - } else if (pin == 28) { - CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK; - } else if (pin == 29) { - CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK; - } else if (pin == 30) { - CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK; - } else if (pin == 31) { - CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK; - } else if (pin == 32) { - CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK; - } else if (pin == 33) { - CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK; - } - #endif - #if defined(CORE_PIN34_PORTCLEAR) - else if (pin == 34) { - CORE_PIN34_PORTCLEAR = CORE_PIN34_BITMASK; - } else if (pin == 35) { - CORE_PIN35_PORTCLEAR = CORE_PIN35_BITMASK; - } else if (pin == 36) { - CORE_PIN36_PORTCLEAR = CORE_PIN36_BITMASK; - } else if (pin == 37) { - CORE_PIN37_PORTCLEAR = CORE_PIN37_BITMASK; - } else if (pin == 38) { - CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK; - } else if (pin == 39) { - CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK; - } else if (pin == 40) { - CORE_PIN40_PORTCLEAR = CORE_PIN40_BITMASK; - } else if (pin == 41) { - CORE_PIN41_PORTCLEAR = CORE_PIN41_BITMASK; - } else if (pin == 42) { - CORE_PIN42_PORTCLEAR = CORE_PIN42_BITMASK; - } else if (pin == 43) { - CORE_PIN43_PORTCLEAR = CORE_PIN43_BITMASK; - } else if (pin == 44) { - CORE_PIN44_PORTCLEAR = CORE_PIN44_BITMASK; - } else if (pin == 45) { - CORE_PIN45_PORTCLEAR = CORE_PIN45_BITMASK; - } else if (pin == 46) { - CORE_PIN46_PORTCLEAR = CORE_PIN46_BITMASK; - } else if (pin == 47) { - CORE_PIN47_PORTCLEAR = CORE_PIN47_BITMASK; - } else if (pin == 48) { - CORE_PIN48_PORTCLEAR = CORE_PIN48_BITMASK; - } else if (pin == 49) { - CORE_PIN49_PORTCLEAR = CORE_PIN49_BITMASK; - } else if (pin == 50) { - CORE_PIN50_PORTCLEAR = CORE_PIN50_BITMASK; - } else if (pin == 51) { - CORE_PIN51_PORTCLEAR = CORE_PIN51_BITMASK; - } else if (pin == 52) { - CORE_PIN52_PORTCLEAR = CORE_PIN52_BITMASK; - } else if (pin == 53) { - CORE_PIN53_PORTCLEAR = CORE_PIN53_BITMASK; - } else if (pin == 54) { - CORE_PIN54_PORTCLEAR = CORE_PIN54_BITMASK; - } else if (pin == 55) { - CORE_PIN55_PORTCLEAR = CORE_PIN55_BITMASK; - } else if (pin == 56) { - CORE_PIN56_PORTCLEAR = CORE_PIN56_BITMASK; - } else if (pin == 57) { - CORE_PIN57_PORTCLEAR = CORE_PIN57_BITMASK; - } else if (pin == 58) { - CORE_PIN58_PORTCLEAR = CORE_PIN58_BITMASK; - } else if (pin == 59) { - CORE_PIN59_PORTCLEAR = CORE_PIN59_BITMASK; - } else if (pin == 60) { - CORE_PIN60_PORTCLEAR = CORE_PIN60_BITMASK; - } else if (pin == 61) { - CORE_PIN61_PORTCLEAR = CORE_PIN61_BITMASK; - } else if (pin == 62) { - CORE_PIN62_PORTCLEAR = CORE_PIN62_BITMASK; - } else if (pin == 63) { - CORE_PIN63_PORTCLEAR = CORE_PIN63_BITMASK; - } - #endif - } - } else { - if (val) { - *portSetRegister(pin) = digitalPinToBitMask(pin); - } else { - *portClearRegister(pin) = digitalPinToBitMask(pin); - } - } + if (__builtin_constant_p(pin)) { + if (val) { + if (pin == 0) { + CORE_PIN0_PORTSET = CORE_PIN0_BITMASK; + } else if (pin == 1) { + CORE_PIN1_PORTSET = CORE_PIN1_BITMASK; + } else if (pin == 2) { + CORE_PIN2_PORTSET = CORE_PIN2_BITMASK; + } else if (pin == 3) { + CORE_PIN3_PORTSET = CORE_PIN3_BITMASK; + } else if (pin == 4) { + CORE_PIN4_PORTSET = CORE_PIN4_BITMASK; + } else if (pin == 5) { + CORE_PIN5_PORTSET = CORE_PIN5_BITMASK; + } else if (pin == 6) { + CORE_PIN6_PORTSET = CORE_PIN6_BITMASK; + } else if (pin == 7) { + CORE_PIN7_PORTSET = CORE_PIN7_BITMASK; + } else if (pin == 8) { + CORE_PIN8_PORTSET = CORE_PIN8_BITMASK; + } else if (pin == 9) { + CORE_PIN9_PORTSET = CORE_PIN9_BITMASK; + } else if (pin == 10) { + CORE_PIN10_PORTSET = CORE_PIN10_BITMASK; + } else if (pin == 11) { + CORE_PIN11_PORTSET = CORE_PIN11_BITMASK; + } else if (pin == 12) { + CORE_PIN12_PORTSET = CORE_PIN12_BITMASK; + } else if (pin == 13) { + CORE_PIN13_PORTSET = CORE_PIN13_BITMASK; + } else if (pin == 14) { + CORE_PIN14_PORTSET = CORE_PIN14_BITMASK; + } else if (pin == 15) { + CORE_PIN15_PORTSET = CORE_PIN15_BITMASK; + } else if (pin == 16) { + CORE_PIN16_PORTSET = CORE_PIN16_BITMASK; + } else if (pin == 17) { + CORE_PIN17_PORTSET = CORE_PIN17_BITMASK; + } else if (pin == 18) { + CORE_PIN18_PORTSET = CORE_PIN18_BITMASK; + } else if (pin == 19) { + CORE_PIN19_PORTSET = CORE_PIN19_BITMASK; + } else if (pin == 20) { + CORE_PIN20_PORTSET = CORE_PIN20_BITMASK; + } else if (pin == 21) { + CORE_PIN21_PORTSET = CORE_PIN21_BITMASK; + } else if (pin == 22) { + CORE_PIN22_PORTSET = CORE_PIN22_BITMASK; + } else if (pin == 23) { + CORE_PIN23_PORTSET = CORE_PIN23_BITMASK; + } else if (pin == 24) { + CORE_PIN24_PORTSET = CORE_PIN24_BITMASK; + } else if (pin == 25) { + CORE_PIN25_PORTSET = CORE_PIN25_BITMASK; + } else if (pin == 26) { + CORE_PIN26_PORTSET = CORE_PIN26_BITMASK; + } + #if defined(CORE_PIN27_PORTSET) + else if (pin == 27) { + CORE_PIN27_PORTSET = CORE_PIN27_BITMASK; + } else if (pin == 28) { + CORE_PIN28_PORTSET = CORE_PIN28_BITMASK; + } else if (pin == 29) { + CORE_PIN29_PORTSET = CORE_PIN29_BITMASK; + } else if (pin == 30) { + CORE_PIN30_PORTSET = CORE_PIN30_BITMASK; + } else if (pin == 31) { + CORE_PIN31_PORTSET = CORE_PIN31_BITMASK; + } else if (pin == 32) { + CORE_PIN32_PORTSET = CORE_PIN32_BITMASK; + } else if (pin == 33) { + CORE_PIN33_PORTSET = CORE_PIN33_BITMASK; + } + #endif + #if defined(CORE_PIN34_PORTSET) + else if (pin == 34) { + CORE_PIN34_PORTSET = CORE_PIN34_BITMASK; + } else if (pin == 35) { + CORE_PIN35_PORTSET = CORE_PIN35_BITMASK; + } else if (pin == 36) { + CORE_PIN36_PORTSET = CORE_PIN36_BITMASK; + } else if (pin == 37) { + CORE_PIN37_PORTSET = CORE_PIN37_BITMASK; + } else if (pin == 38) { + CORE_PIN38_PORTSET = CORE_PIN38_BITMASK; + } else if (pin == 39) { + CORE_PIN39_PORTSET = CORE_PIN39_BITMASK; + } else if (pin == 40) { + CORE_PIN40_PORTSET = CORE_PIN40_BITMASK; + } else if (pin == 41) { + CORE_PIN41_PORTSET = CORE_PIN41_BITMASK; + } else if (pin == 42) { + CORE_PIN42_PORTSET = CORE_PIN42_BITMASK; + } else if (pin == 43) { + CORE_PIN43_PORTSET = CORE_PIN43_BITMASK; + } else if (pin == 44) { + CORE_PIN44_PORTSET = CORE_PIN44_BITMASK; + } else if (pin == 45) { + CORE_PIN45_PORTSET = CORE_PIN45_BITMASK; + } else if (pin == 46) { + CORE_PIN46_PORTSET = CORE_PIN46_BITMASK; + } else if (pin == 47) { + CORE_PIN47_PORTSET = CORE_PIN47_BITMASK; + } else if (pin == 48) { + CORE_PIN48_PORTSET = CORE_PIN48_BITMASK; + } else if (pin == 49) { + CORE_PIN49_PORTSET = CORE_PIN49_BITMASK; + } else if (pin == 50) { + CORE_PIN50_PORTSET = CORE_PIN50_BITMASK; + } else if (pin == 51) { + CORE_PIN51_PORTSET = CORE_PIN51_BITMASK; + } else if (pin == 52) { + CORE_PIN52_PORTSET = CORE_PIN52_BITMASK; + } else if (pin == 53) { + CORE_PIN53_PORTSET = CORE_PIN53_BITMASK; + } else if (pin == 54) { + CORE_PIN54_PORTSET = CORE_PIN54_BITMASK; + } else if (pin == 55) { + CORE_PIN55_PORTSET = CORE_PIN55_BITMASK; + } else if (pin == 56) { + CORE_PIN56_PORTSET = CORE_PIN56_BITMASK; + } else if (pin == 57) { + CORE_PIN57_PORTSET = CORE_PIN57_BITMASK; + } else if (pin == 58) { + CORE_PIN58_PORTSET = CORE_PIN58_BITMASK; + } else if (pin == 59) { + CORE_PIN59_PORTSET = CORE_PIN59_BITMASK; + } else if (pin == 60) { + CORE_PIN60_PORTSET = CORE_PIN60_BITMASK; + } else if (pin == 61) { + CORE_PIN61_PORTSET = CORE_PIN61_BITMASK; + } else if (pin == 62) { + CORE_PIN62_PORTSET = CORE_PIN62_BITMASK; + } else if (pin == 63) { + CORE_PIN63_PORTSET = CORE_PIN63_BITMASK; + } + #endif + // tranZPUter v2.2 additional pins. + #if defined(CORE_PIN64_PORTSET) + else if (pin == 64) { + CORE_PIN64_PORTSET = CORE_PIN64_BITMASK; + } else if (pin == 65) { + CORE_PIN65_PORTSET = CORE_PIN65_BITMASK; + } else if (pin == 66) { + CORE_PIN66_PORTSET = CORE_PIN66_BITMASK; + } else if (pin == 67) { + CORE_PIN67_PORTSET = CORE_PIN67_BITMASK; + } else if (pin == 68) { + CORE_PIN68_PORTSET = CORE_PIN68_BITMASK; + } else if (pin == 69) { + CORE_PIN69_PORTSET = CORE_PIN69_BITMASK; + } else if (pin == 70) { + CORE_PIN70_PORTSET = CORE_PIN70_BITMASK; + } else if (pin == 71) { + CORE_PIN71_PORTSET = CORE_PIN71_BITMASK; + } + #endif + } else { + if (pin == 0) { + CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK; + } else if (pin == 1) { + CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK; + } else if (pin == 2) { + CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK; + } else if (pin == 3) { + CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK; + } else if (pin == 4) { + CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK; + } else if (pin == 5) { + CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK; + } else if (pin == 6) { + CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK; + } else if (pin == 7) { + CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK; + } else if (pin == 8) { + CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK; + } else if (pin == 9) { + CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK; + } else if (pin == 10) { + CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK; + } else if (pin == 11) { + CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK; + } else if (pin == 12) { + CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK; + } else if (pin == 13) { + CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK; + } else if (pin == 14) { + CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK; + } else if (pin == 15) { + CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK; + } else if (pin == 16) { + CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK; + } else if (pin == 17) { + CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK; + } else if (pin == 18) { + CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK; + } else if (pin == 19) { + CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK; + } else if (pin == 20) { + CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK; + } else if (pin == 21) { + CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK; + } else if (pin == 22) { + CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK; + } else if (pin == 23) { + CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK; + } else if (pin == 24) { + CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK; + } else if (pin == 25) { + CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK; + } else if (pin == 26) { + CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK; + } + #if defined(CORE_PIN27_PORTCLEAR) + else if (pin == 27) { + CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK; + } else if (pin == 28) { + CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK; + } else if (pin == 29) { + CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK; + } else if (pin == 30) { + CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK; + } else if (pin == 31) { + CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK; + } else if (pin == 32) { + CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK; + } else if (pin == 33) { + CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK; + } + #endif + #if defined(CORE_PIN34_PORTCLEAR) + else if (pin == 34) { + CORE_PIN34_PORTCLEAR = CORE_PIN34_BITMASK; + } else if (pin == 35) { + CORE_PIN35_PORTCLEAR = CORE_PIN35_BITMASK; + } else if (pin == 36) { + CORE_PIN36_PORTCLEAR = CORE_PIN36_BITMASK; + } else if (pin == 37) { + CORE_PIN37_PORTCLEAR = CORE_PIN37_BITMASK; + } else if (pin == 38) { + CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK; + } else if (pin == 39) { + CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK; + } else if (pin == 40) { + CORE_PIN40_PORTCLEAR = CORE_PIN40_BITMASK; + } else if (pin == 41) { + CORE_PIN41_PORTCLEAR = CORE_PIN41_BITMASK; + } else if (pin == 42) { + CORE_PIN42_PORTCLEAR = CORE_PIN42_BITMASK; + } else if (pin == 43) { + CORE_PIN43_PORTCLEAR = CORE_PIN43_BITMASK; + } else if (pin == 44) { + CORE_PIN44_PORTCLEAR = CORE_PIN44_BITMASK; + } else if (pin == 45) { + CORE_PIN45_PORTCLEAR = CORE_PIN45_BITMASK; + } else if (pin == 46) { + CORE_PIN46_PORTCLEAR = CORE_PIN46_BITMASK; + } else if (pin == 47) { + CORE_PIN47_PORTCLEAR = CORE_PIN47_BITMASK; + } else if (pin == 48) { + CORE_PIN48_PORTCLEAR = CORE_PIN48_BITMASK; + } else if (pin == 49) { + CORE_PIN49_PORTCLEAR = CORE_PIN49_BITMASK; + } else if (pin == 50) { + CORE_PIN50_PORTCLEAR = CORE_PIN50_BITMASK; + } else if (pin == 51) { + CORE_PIN51_PORTCLEAR = CORE_PIN51_BITMASK; + } else if (pin == 52) { + CORE_PIN52_PORTCLEAR = CORE_PIN52_BITMASK; + } else if (pin == 53) { + CORE_PIN53_PORTCLEAR = CORE_PIN53_BITMASK; + } else if (pin == 54) { + CORE_PIN54_PORTCLEAR = CORE_PIN54_BITMASK; + } else if (pin == 55) { + CORE_PIN55_PORTCLEAR = CORE_PIN55_BITMASK; + } else if (pin == 56) { + CORE_PIN56_PORTCLEAR = CORE_PIN56_BITMASK; + } else if (pin == 57) { + CORE_PIN57_PORTCLEAR = CORE_PIN57_BITMASK; + } else if (pin == 58) { + CORE_PIN58_PORTCLEAR = CORE_PIN58_BITMASK; + } else if (pin == 59) { + CORE_PIN59_PORTCLEAR = CORE_PIN59_BITMASK; + } else if (pin == 60) { + CORE_PIN60_PORTCLEAR = CORE_PIN60_BITMASK; + } else if (pin == 61) { + CORE_PIN61_PORTCLEAR = CORE_PIN61_BITMASK; + } else if (pin == 62) { + CORE_PIN62_PORTCLEAR = CORE_PIN62_BITMASK; + } else if (pin == 63) { + CORE_PIN63_PORTCLEAR = CORE_PIN63_BITMASK; + } + #endif + // tranZPUter v2.2 additional pins. + #if defined(CORE_PIN64_PORTSET) + else if (pin == 64) { + CORE_PIN64_PORTCLEAR = CORE_PIN64_BITMASK; + } else if (pin == 65) { + CORE_PIN65_PORTCLEAR = CORE_PIN65_BITMASK; + } else if (pin == 66) { + CORE_PIN66_PORTCLEAR = CORE_PIN66_BITMASK; + } else if (pin == 67) { + CORE_PIN67_PORTCLEAR = CORE_PIN67_BITMASK; + } else if (pin == 68) { + CORE_PIN68_PORTCLEAR = CORE_PIN68_BITMASK; + } else if (pin == 69) { + CORE_PIN69_PORTCLEAR = CORE_PIN69_BITMASK; + } else if (pin == 70) { + CORE_PIN70_PORTCLEAR = CORE_PIN70_BITMASK; + } else if (pin == 71) { + CORE_PIN71_PORTCLEAR = CORE_PIN71_BITMASK; + } + #endif + } + } else { + if (val) { + *portSetRegister(pin) = digitalPinToBitMask(pin); + } else { + *portClearRegister(pin) = digitalPinToBitMask(pin); + } + } } uint8_t digitalRead(uint8_t pin); static inline uint8_t digitalReadFast(uint8_t pin) __attribute__((always_inline, unused)); static inline uint8_t digitalReadFast(uint8_t pin) { - if (__builtin_constant_p(pin)) { - if (pin == 0) { - return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0; - } else if (pin == 1) { - return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0; - } else if (pin == 2) { - return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0; - } else if (pin == 3) { - return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0; - } else if (pin == 4) { - return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0; - } else if (pin == 5) { - return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0; - } else if (pin == 6) { - return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0; - } else if (pin == 7) { - return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0; - } else if (pin == 8) { - return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0; - } else if (pin == 9) { - return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0; - } else if (pin == 10) { - return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0; - } else if (pin == 11) { - return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0; - } else if (pin == 12) { - return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0; - } else if (pin == 13) { - return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0; - } else if (pin == 14) { - return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0; - } else if (pin == 15) { - return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0; - } else if (pin == 16) { - return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0; - } else if (pin == 17) { - return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0; - } else if (pin == 18) { - return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0; - } else if (pin == 19) { - return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0; - } else if (pin == 20) { - return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0; - } else if (pin == 21) { - return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0; - } else if (pin == 22) { - return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0; - } else if (pin == 23) { - return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0; - } else if (pin == 24) { - return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0; - } else if (pin == 25) { - return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0; - } else if (pin == 26) { - return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0; - } - #if defined(CORE_PIN27_PINREG) - else if (pin == 27) { - return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0; - } else if (pin == 28) { - return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0; - } else if (pin == 29) { - return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0; - } else if (pin == 30) { - return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0; - } else if (pin == 31) { - return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0; - } else if (pin == 32) { - return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0; - } else if (pin == 33) { - return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0; - } - #endif - #if defined(CORE_PIN34_PINREG) - else if (pin == 34) { - return (CORE_PIN34_PINREG & CORE_PIN34_BITMASK) ? 1 : 0; - } else if (pin == 35) { - return (CORE_PIN35_PINREG & CORE_PIN35_BITMASK) ? 1 : 0; - } else if (pin == 36) { - return (CORE_PIN36_PINREG & CORE_PIN36_BITMASK) ? 1 : 0; - } else if (pin == 37) { - return (CORE_PIN37_PINREG & CORE_PIN37_BITMASK) ? 1 : 0; - } else if (pin == 38) { - return (CORE_PIN38_PINREG & CORE_PIN38_BITMASK) ? 1 : 0; - } else if (pin == 39) { - return (CORE_PIN39_PINREG & CORE_PIN39_BITMASK) ? 1 : 0; - } else if (pin == 40) { - return (CORE_PIN40_PINREG & CORE_PIN40_BITMASK) ? 1 : 0; - } else if (pin == 41) { - return (CORE_PIN41_PINREG & CORE_PIN41_BITMASK) ? 1 : 0; - } else if (pin == 42) { - return (CORE_PIN42_PINREG & CORE_PIN42_BITMASK) ? 1 : 0; - } else if (pin == 43) { - return (CORE_PIN43_PINREG & CORE_PIN43_BITMASK) ? 1 : 0; - } else if (pin == 44) { - return (CORE_PIN44_PINREG & CORE_PIN44_BITMASK) ? 1 : 0; - } else if (pin == 45) { - return (CORE_PIN45_PINREG & CORE_PIN45_BITMASK) ? 1 : 0; - } else if (pin == 46) { - return (CORE_PIN46_PINREG & CORE_PIN46_BITMASK) ? 1 : 0; - } else if (pin == 47) { - return (CORE_PIN47_PINREG & CORE_PIN47_BITMASK) ? 1 : 0; - } else if (pin == 48) { - return (CORE_PIN48_PINREG & CORE_PIN48_BITMASK) ? 1 : 0; - } else if (pin == 49) { - return (CORE_PIN49_PINREG & CORE_PIN49_BITMASK) ? 1 : 0; - } else if (pin == 50) { - return (CORE_PIN50_PINREG & CORE_PIN50_BITMASK) ? 1 : 0; - } else if (pin == 51) { - return (CORE_PIN51_PINREG & CORE_PIN51_BITMASK) ? 1 : 0; - } else if (pin == 52) { - return (CORE_PIN52_PINREG & CORE_PIN52_BITMASK) ? 1 : 0; - } else if (pin == 53) { - return (CORE_PIN53_PINREG & CORE_PIN53_BITMASK) ? 1 : 0; - } else if (pin == 54) { - return (CORE_PIN54_PINREG & CORE_PIN54_BITMASK) ? 1 : 0; - } else if (pin == 55) { - return (CORE_PIN55_PINREG & CORE_PIN55_BITMASK) ? 1 : 0; - } else if (pin == 56) { - return (CORE_PIN56_PINREG & CORE_PIN56_BITMASK) ? 1 : 0; - } else if (pin == 57) { - return (CORE_PIN57_PINREG & CORE_PIN57_BITMASK) ? 1 : 0; - } else if (pin == 58) { - return (CORE_PIN58_PINREG & CORE_PIN58_BITMASK) ? 1 : 0; - } else if (pin == 59) { - return (CORE_PIN59_PINREG & CORE_PIN59_BITMASK) ? 1 : 0; - } else if (pin == 60) { - return (CORE_PIN60_PINREG & CORE_PIN60_BITMASK) ? 1 : 0; - } else if (pin == 61) { - return (CORE_PIN61_PINREG & CORE_PIN61_BITMASK) ? 1 : 0; - } else if (pin == 62) { - return (CORE_PIN62_PINREG & CORE_PIN62_BITMASK) ? 1 : 0; - } else if (pin == 63) { - return (CORE_PIN63_PINREG & CORE_PIN63_BITMASK) ? 1 : 0; - } - #endif - else { - return 0; - } - } else { - #if defined(KINETISK) - return *portInputRegister(pin); - #else - return (*portInputRegister(pin) & digitalPinToBitMask(pin)) ? 1 : 0; - #endif - } + if (__builtin_constant_p(pin)) { + if (pin == 0) { + return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0; + } else if (pin == 1) { + return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0; + } else if (pin == 2) { + return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0; + } else if (pin == 3) { + return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0; + } else if (pin == 4) { + return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0; + } else if (pin == 5) { + return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0; + } else if (pin == 6) { + return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0; + } else if (pin == 7) { + return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0; + } else if (pin == 8) { + return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0; + } else if (pin == 9) { + return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0; + } else if (pin == 10) { + return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0; + } else if (pin == 11) { + return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0; + } else if (pin == 12) { + return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0; + } else if (pin == 13) { + return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0; + } else if (pin == 14) { + return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0; + } else if (pin == 15) { + return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0; + } else if (pin == 16) { + return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0; + } else if (pin == 17) { + return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0; + } else if (pin == 18) { + return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0; + } else if (pin == 19) { + return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0; + } else if (pin == 20) { + return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0; + } else if (pin == 21) { + return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0; + } else if (pin == 22) { + return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0; + } else if (pin == 23) { + return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0; + } else if (pin == 24) { + return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0; + } else if (pin == 25) { + return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0; + } else if (pin == 26) { + return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0; + } + #if defined(CORE_PIN27_PINREG) + else if (pin == 27) { + return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0; + } else if (pin == 28) { + return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0; + } else if (pin == 29) { + return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0; + } else if (pin == 30) { + return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0; + } else if (pin == 31) { + return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0; + } else if (pin == 32) { + return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0; + } else if (pin == 33) { + return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0; + } + #endif + #if defined(CORE_PIN34_PINREG) + else if (pin == 34) { + return (CORE_PIN34_PINREG & CORE_PIN34_BITMASK) ? 1 : 0; + } else if (pin == 35) { + return (CORE_PIN35_PINREG & CORE_PIN35_BITMASK) ? 1 : 0; + } else if (pin == 36) { + return (CORE_PIN36_PINREG & CORE_PIN36_BITMASK) ? 1 : 0; + } else if (pin == 37) { + return (CORE_PIN37_PINREG & CORE_PIN37_BITMASK) ? 1 : 0; + } else if (pin == 38) { + return (CORE_PIN38_PINREG & CORE_PIN38_BITMASK) ? 1 : 0; + } else if (pin == 39) { + return (CORE_PIN39_PINREG & CORE_PIN39_BITMASK) ? 1 : 0; + } else if (pin == 40) { + return (CORE_PIN40_PINREG & CORE_PIN40_BITMASK) ? 1 : 0; + } else if (pin == 41) { + return (CORE_PIN41_PINREG & CORE_PIN41_BITMASK) ? 1 : 0; + } else if (pin == 42) { + return (CORE_PIN42_PINREG & CORE_PIN42_BITMASK) ? 1 : 0; + } else if (pin == 43) { + return (CORE_PIN43_PINREG & CORE_PIN43_BITMASK) ? 1 : 0; + } else if (pin == 44) { + return (CORE_PIN44_PINREG & CORE_PIN44_BITMASK) ? 1 : 0; + } else if (pin == 45) { + return (CORE_PIN45_PINREG & CORE_PIN45_BITMASK) ? 1 : 0; + } else if (pin == 46) { + return (CORE_PIN46_PINREG & CORE_PIN46_BITMASK) ? 1 : 0; + } else if (pin == 47) { + return (CORE_PIN47_PINREG & CORE_PIN47_BITMASK) ? 1 : 0; + } else if (pin == 48) { + return (CORE_PIN48_PINREG & CORE_PIN48_BITMASK) ? 1 : 0; + } else if (pin == 49) { + return (CORE_PIN49_PINREG & CORE_PIN49_BITMASK) ? 1 : 0; + } else if (pin == 50) { + return (CORE_PIN50_PINREG & CORE_PIN50_BITMASK) ? 1 : 0; + } else if (pin == 51) { + return (CORE_PIN51_PINREG & CORE_PIN51_BITMASK) ? 1 : 0; + } else if (pin == 52) { + return (CORE_PIN52_PINREG & CORE_PIN52_BITMASK) ? 1 : 0; + } else if (pin == 53) { + return (CORE_PIN53_PINREG & CORE_PIN53_BITMASK) ? 1 : 0; + } else if (pin == 54) { + return (CORE_PIN54_PINREG & CORE_PIN54_BITMASK) ? 1 : 0; + } else if (pin == 55) { + return (CORE_PIN55_PINREG & CORE_PIN55_BITMASK) ? 1 : 0; + } else if (pin == 56) { + return (CORE_PIN56_PINREG & CORE_PIN56_BITMASK) ? 1 : 0; + } else if (pin == 57) { + return (CORE_PIN57_PINREG & CORE_PIN57_BITMASK) ? 1 : 0; + } else if (pin == 58) { + return (CORE_PIN58_PINREG & CORE_PIN58_BITMASK) ? 1 : 0; + } else if (pin == 59) { + return (CORE_PIN59_PINREG & CORE_PIN59_BITMASK) ? 1 : 0; + } else if (pin == 60) { + return (CORE_PIN60_PINREG & CORE_PIN60_BITMASK) ? 1 : 0; + } else if (pin == 61) { + return (CORE_PIN61_PINREG & CORE_PIN61_BITMASK) ? 1 : 0; + } else if (pin == 62) { + return (CORE_PIN62_PINREG & CORE_PIN62_BITMASK) ? 1 : 0; + } else if (pin == 63) { + return (CORE_PIN63_PINREG & CORE_PIN63_BITMASK) ? 1 : 0; + } + #endif + // tranZPUter v2.2 additional pins. + #if defined(CORE_PIN64_PORTSET) + else if (pin == 64) { + return (CORE_PIN64_PINREG & CORE_PIN64_BITMASK) ? 1 : 0; + } else if (pin == 65) { + return (CORE_PIN65_PINREG & CORE_PIN65_BITMASK) ? 1 : 0; + } else if (pin == 66) { + return (CORE_PIN66_PINREG & CORE_PIN66_BITMASK) ? 1 : 0; + } else if (pin == 67) { + return (CORE_PIN67_PINREG & CORE_PIN67_BITMASK) ? 1 : 0; + } else if (pin == 68) { + return (CORE_PIN68_PINREG & CORE_PIN68_BITMASK) ? 1 : 0; + } else if (pin == 69) { + return (CORE_PIN69_PINREG & CORE_PIN69_BITMASK) ? 1 : 0; + } else if (pin == 70) { + return (CORE_PIN70_PINREG & CORE_PIN70_BITMASK) ? 1 : 0; + } else if (pin == 71) { + return (CORE_PIN71_PINREG & CORE_PIN71_BITMASK) ? 1 : 0; + } + #endif + else { + return 0; + } + } else { + #if defined(KINETISK) + return *portInputRegister(pin); + #else + return (*portInputRegister(pin) & digitalPinToBitMask(pin)) ? 1 : 0; + #endif + } } @@ -2005,17 +2149,17 @@ extern volatile uint32_t systick_millis_count; static inline uint32_t millis(void) __attribute__((always_inline, unused)); static inline uint32_t millis(void) { - // Reading a volatile variable to another volatile - // seems redundant, but isn't for some cases. - // Eventually this should probably be replaced by a - // proper memory barrier or other technique. Please - // do not remove this "redundant" code without - // carefully verifying the case mentioned here: - // - // https://forum.pjrc.com/threads/17469-millis%28%29-on-teensy-3?p=104924&viewfull=1#post104924 - // - volatile uint32_t ret = systick_millis_count; // single aligned 32 bit is atomic - return ret; + // Reading a volatile variable to another volatile + // seems redundant, but isn't for some cases. + // Eventually this should probably be replaced by a + // proper memory barrier or other technique. Please + // do not remove this "redundant" code without + // carefully verifying the case mentioned here: + // + // https://forum.pjrc.com/threads/17469-millis%28%29-on-teensy-3?p=104924&viewfull=1#post104924 + // + volatile uint32_t ret = systick_millis_count; // single aligned 32 bit is atomic + return ret; } uint32_t micros(void); @@ -2024,55 +2168,55 @@ static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unu static inline void delayMicroseconds(uint32_t usec) { #if F_CPU == 256000000 - uint32_t n = usec * 85; + uint32_t n = usec * 85; #elif F_CPU == 240000000 - uint32_t n = usec * 80; + uint32_t n = usec * 80; #elif F_CPU == 216000000 - uint32_t n = usec * 72; + uint32_t n = usec * 72; #elif F_CPU == 192000000 - uint32_t n = usec * 64; + uint32_t n = usec * 64; #elif F_CPU == 180000000 - uint32_t n = usec * 60; + uint32_t n = usec * 60; #elif F_CPU == 168000000 - uint32_t n = usec * 56; + uint32_t n = usec * 56; #elif F_CPU == 144000000 - uint32_t n = usec * 48; + uint32_t n = usec * 48; #elif F_CPU == 120000000 - uint32_t n = usec * 40; + uint32_t n = usec * 40; #elif F_CPU == 96000000 - uint32_t n = usec << 5; + uint32_t n = usec << 5; #elif F_CPU == 72000000 - uint32_t n = usec * 24; + uint32_t n = usec * 24; #elif F_CPU == 48000000 - uint32_t n = usec << 4; + uint32_t n = usec << 4; #elif F_CPU == 24000000 - uint32_t n = usec << 3; + uint32_t n = usec << 3; #elif F_CPU == 16000000 - uint32_t n = usec << 2; + uint32_t n = usec << 2; #elif F_CPU == 8000000 - uint32_t n = usec << 1; + uint32_t n = usec << 1; #elif F_CPU == 4000000 - uint32_t n = usec; + uint32_t n = usec; #elif F_CPU == 2000000 - uint32_t n = usec >> 1; + uint32_t n = usec >> 1; #endif // changed because a delay of 1 micro Sec @ 2MHz will be 0 - if (n == 0) return; - __asm__ volatile( - "L_%=_delayMicroseconds:" "\n\t" + if (n == 0) return; + __asm__ volatile( + "L_%=_delayMicroseconds:" "\n\t" #if F_CPU < 24000000 - "nop" "\n\t" + "nop" "\n\t" #endif #ifdef KINETISL - "sub %0, #1" "\n\t" - "bne L_%=_delayMicroseconds" "\n" - : "+l" (n) : + "sub %0, #1" "\n\t" + "bne L_%=_delayMicroseconds" "\n" + : "+l" (n) : #else - "subs %0, #1" "\n\t" - "bne L_%=_delayMicroseconds" "\n" - : "+r" (n) : + "subs %0, #1" "\n\t" + "bne L_%=_delayMicroseconds" "\n" + : "+r" (n) : #endif - ); + ); } #ifdef __cplusplus @@ -2097,9 +2241,9 @@ void rtc_compensate(int adjust); class teensy3_clock_class { public: - static unsigned long get(void) __attribute__((always_inline)) { return rtc_get(); } - static void set(unsigned long t) __attribute__((always_inline)) { rtc_set(t); } - static void compensate(int adj) __attribute__((always_inline)) { rtc_compensate(adj); } + static unsigned long get(void) __attribute__((always_inline)) { return rtc_get(); } + static void set(unsigned long t) __attribute__((always_inline)) { rtc_set(t); } + static void compensate(int adj) __attribute__((always_inline)) { rtc_compensate(adj); } }; extern teensy3_clock_class Teensy3Clock; #endif diff --git a/teensy3/pins_teensy.c b/teensy3/pins_teensy.c index 5078977..09c91f6 100644 --- a/teensy3/pins_teensy.c +++ b/teensy3/pins_teensy.c @@ -1,6 +1,7 @@ /* Teensyduino Core Library * http://www.pjrc.com/teensy/ * Copyright (c) 2017 PJRC.COM, LLC. + * Copyright (c) 2020 P. D. Smart, tranZPUter SW updates. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the @@ -105,6 +106,17 @@ const struct digital_pin_bitband_and_config_table_struct digital_pin_to_info_PGM {GPIO_BITBAND_PTR(CORE_PIN62_PORTREG, CORE_PIN62_BIT), &CORE_PIN62_CONFIG}, {GPIO_BITBAND_PTR(CORE_PIN63_PORTREG, CORE_PIN63_BIT), &CORE_PIN63_CONFIG}, #endif +// tranZPUter v2.2 additional pins. +#ifdef CORE_PIN64_PORTREG + {GPIO_BITBAND_PTR(CORE_PIN64_PORTREG, CORE_PIN64_BIT), &CORE_PIN64_CONFIG}, + {GPIO_BITBAND_PTR(CORE_PIN65_PORTREG, CORE_PIN65_BIT), &CORE_PIN65_CONFIG}, + {GPIO_BITBAND_PTR(CORE_PIN66_PORTREG, CORE_PIN66_BIT), &CORE_PIN66_CONFIG}, + {GPIO_BITBAND_PTR(CORE_PIN67_PORTREG, CORE_PIN67_BIT), &CORE_PIN67_CONFIG}, + {GPIO_BITBAND_PTR(CORE_PIN68_PORTREG, CORE_PIN68_BIT), &CORE_PIN68_CONFIG}, + {GPIO_BITBAND_PTR(CORE_PIN69_PORTREG, CORE_PIN69_BIT), &CORE_PIN69_CONFIG}, + {GPIO_BITBAND_PTR(CORE_PIN70_PORTREG, CORE_PIN70_BIT), &CORE_PIN70_CONFIG}, + {GPIO_BITBAND_PTR(CORE_PIN71_PORTREG, CORE_PIN71_BIT), &CORE_PIN71_CONFIG}, +#endif }; #elif defined(KINETISL)