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Latest updates to the emulator code base

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This commit is contained in:
Philip Smart
2021-12-23 23:22:25 +00:00
parent a7c0f36b3a
commit a352cc4b92
17 changed files with 3586 additions and 1092 deletions
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23
buildall
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@@ -3,13 +3,9 @@
# Not used: Target machine, used to select the right software for the SD card.
# TARGET=MZ-700
# TARGET=MZ-80A
TARGET=MZ-2000
<<<<<<< HEAD
ZPU_SHARPMZ_BUILD=1
=======
TARGET=MZ-80A
ZPU_SHARPMZ_BUILD=0
>>>>>>> 5a59ff2f96064433b95b8489dbe7e9b175b0accc
#ZPU_SHARPMZ_APPADDR=0x100000
#ZPU_SHARPMZ_APPSIZE=0x70000
#ZPU_SHARPMZ_HEAPSIZE=0x8000
@@ -26,6 +22,8 @@ ZPU_E115_APPSIZE=0x8000
ZPU_E115_HEAPSIZE=0x4000
ZPU_E115_STACKSIZE=0x3D80
echo "Build target: ${TARGET}"
# NB: When setting this variable, see lower section creating the SD card image which uses a hard coded value and will need updating.
ROOT_DIR=/dvlp/Projects/dev/github/
# NB: This clean out is intentionally hard coded as -fr is dangerous, if a variable failed to be set if could see your source base wiped out.
@@ -64,13 +62,6 @@ if [ "${ZPU_E115_BUILD}x" != "x" -a ${ZPU_E115_BUILD} = 1 ]; then
cp -r build/SD/* SD/Dev/
fi
<<<<<<< HEAD
echo "Building for K64F"
./build.sh -C K64F -O zos -N 0x18000 -d -T
if [ $? != 0 ]; then
echo "Error building K64F Distribution..."
exit 1
=======
if [ "${TARGET}x" != "x" -a "${TARGET}" = "MZ-80A" ]; then
echo "Building for K64F on MZ-80A"
./build.sh -C K64F -O zos -N 0x10000 -d -T
@@ -78,6 +69,13 @@ if [ "${TARGET}x" != "x" -a "${TARGET}" = "MZ-80A" ]; then
echo "Error building K64F Distribution..."
exit 1
fi
elif [ "${TARGET}x" != "x" -a "${TARGET}" = "MZ-2000" ]; then
echo "Building for K64F on MZ-2000"
./build.sh -C K64F -O zos -N 0x10000 -d -T
if [ $? != 0 ]; then
echo "Error building K64F Distribution..."
exit 1
fi
else
echo "Building for K64F"
./build.sh -C K64F -O zos -N 0x18000 -d -T
@@ -85,7 +83,6 @@ else
echo "Error building K64F Distribution..."
exit 1
fi
>>>>>>> 5a59ff2f96064433b95b8489dbe7e9b175b0accc
fi
cp -r build/SD/* SD/K64F/

2104
common/emumz.c
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File diff suppressed because it is too large Load Diff

177
common/osd.c
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@@ -69,11 +69,23 @@ extern "C" {
#include <tranzputer.h>
#include <osd.h>
// Debug macros
#define debugf(a, ...) if(osdWindow.debug) { printf("\033[1;31mOSD: " a "\033[0m\n", ##__VA_ARGS__); }
#define debugfx(a, ...) if(osdWindow.debug) { printf("\033[1;32mOSD: " a "\033[0m\n", ##__VA_ARGS__); }
#ifndef __APP__ // Protected methods which should only reside in the kernel on zOS.
static t_OSDWindow osdWindow = {.mode=MENU, .params={ {.attr=0, .row=0, .col=0, .maxCol=0, .maxRow=0, .lineWrap=1, .maxX=VC_STATUS_MAX_X_PIXELS, .maxY=VC_STATUS_MAX_Y_PIXELS},
{.attr=0, .row=0, .col=0, .maxCol=0, .maxRow=0, .lineWrap=1, .maxX=VC_MENU_MAX_X_PIXELS, .maxY=VC_MENU_MAX_Y_PIXELS} },
static t_OSDWindow osdWindow = {.mode=MENU, .params={ {.attr=0, .row=0, .col=0, .maxCol=0, .maxRow=0, .lineWrap=1, .maxX=VC_STATUS_MAX_X_PIXELS, .maxY=VC_STATUS_MAX_Y_PIXELS,
.cursor={.flashing=0, .enabled=0}
},
{.attr=0, .row=0, .col=0, .maxCol=0, .maxRow=0, .lineWrap=1, .maxX=VC_MENU_MAX_X_PIXELS, .maxY=VC_MENU_MAX_Y_PIXELS,
.cursor={.flashing=0, .enabled=0}
}
},
.debug=0, .inDebug=0, .display=NULL};
// Real time millisecond counter, interrupt driven. Needs to be volatile in order to prevent the compiler optimising it away.
uint32_t volatile *msecs = &systick_millis_count;
// Method to get internal public member values. This module ideally should be written in C++ but with the limitations of the GNU C Compiler for the ZPU (v3.4.2) and the performance penalty on
// an embedded processor, it was decided to write it in C but the methodology and naming conventions (ie. OSDDrawLine = OSD.DrawLine, OSDInit = OSD::OSD constructor) are kept loosly
// associated with C++. Ideally for this getter method function overloading is required!
@@ -234,7 +246,7 @@ void OSDChangePixelColour(uint16_t x, uint16_t y, enum COLOUR fg, enum COLOUR bg
// Internal method to write a single character into the status/menu framebuffer. The X/Y location is specified in font units, also the orientation,
// colour and required font.
//
void _OSDwrite(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad, uint8_t ypad, enum ORIENTATION orientation, uint8_t chr, enum COLOUR fg, enum COLOUR bg, fontStruct *font)
void _OSDwrite(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad, uint8_t ypad, enum ORIENTATION orientation, uint8_t chr, uint16_t attr, enum COLOUR fg, enum COLOUR bg, fontStruct *font)
{
// Locals.
uint16_t startX;
@@ -254,8 +266,7 @@ void _OSDwrite(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad, uin
// Check bounds of character.
if(chr < font->start || chr > font->end)
{
// if(osdWindow.debug)
printf("Character out of bounds:%02x(%d,%d)\n", chr, font->start, font->end);
debugf("Character out of bounds:%02x(%d,%d)\n", chr, font->start, font->end);
return;
}
@@ -299,8 +310,7 @@ void _OSDwrite(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad, uin
// Cant write if out of bounds.
if(startX > osdWindow.params[osdWindow.mode].maxX || startY > osdWindow.params[osdWindow.mode].maxY || startX+width > osdWindow.params[osdWindow.mode].maxX || startY+height > osdWindow.params[osdWindow.mode].maxY)
{
// if(osdWindow.debug)
printf("Position out of bounds:%d,%d(%d,%d)\n", startX, startY, x, y);
debugf("Position out of bounds:%d,%d(%d,%d). Max:%d,%d\n", startX, startY, x, y, osdWindow.params[osdWindow.mode].maxX, osdWindow.params[osdWindow.mode].maxY);
return;
}
@@ -334,12 +344,13 @@ void _OSDwrite(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad, uin
// Test to see if a foreground or background pixel is set and update the framebuffer accordingly.
if(vChrRow & 0x80 >> bitPos)
{
if(fg & (1 << colourMode))
if(((attr & HILIGHT_FG_ACTIVE) && ((attr&~HILIGHT_FG_ACTIVE) & (1 << colourMode))) || (!(attr & HILIGHT_FG_ACTIVE) && (fg & (1 << colourMode))))
osdWindow.display[colourMode][addr] |= 0x80 >> bitOffset;
else
osdWindow.display[colourMode][addr] &= ~(0x80 >> bitOffset);
if(osdWindow.debug && colourMode == 0) { printf("*"); }
} else if(bg & (1 << colourMode))
}
else if(((attr & HILIGHT_BG_ACTIVE) && ((attr&~HILIGHT_BG_ACTIVE) & (1 << colourMode))) || (!(attr & HILIGHT_BG_ACTIVE) && (bg & (1 << colourMode))))
{
osdWindow.display[colourMode][addr] |= 0x80 >> bitOffset;
if(osdWindow.debug && colourMode == 0) { printf(" "); }
@@ -379,13 +390,13 @@ void _OSDwrite(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad, uin
if(vChrRow & 0x80 >> bitPos)
{
if(fg & (1 << colourMode))
if(((attr & HILIGHT_FG_ACTIVE) && ((attr&~HILIGHT_FG_ACTIVE) & (1 << colourMode))) || (!(attr & HILIGHT_FG_ACTIVE) && (fg & (1 << colourMode))))
osdWindow.display[colourMode][addr] |= 1 << bitOffset;
else
osdWindow.display[colourMode][addr] &= ~(1 << bitOffset);
if(osdWindow.debug && colourMode == 0) { printf("*"); }
}
else if(bg & (1 << colourMode))
else if(((attr & HILIGHT_BG_ACTIVE) && ((attr&~HILIGHT_BG_ACTIVE) & (1 << colourMode))) || (!(attr & HILIGHT_BG_ACTIVE) && (bg & (1 << colourMode))))
{
osdWindow.display[colourMode][addr] |= 1 << bitOffset;
if(osdWindow.debug && colourMode == 0) { printf(" "); }
@@ -428,13 +439,13 @@ void _OSDwrite(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad, uin
// Test to see if a pixel is set and update the framebuffer accordingly.
if(vChrRow & 1 << bitPos)
{
if(fg & (1 << colourMode))
if(((attr & HILIGHT_FG_ACTIVE) && ((attr&~HILIGHT_FG_ACTIVE) & (1 << colourMode))) || (!(attr & HILIGHT_FG_ACTIVE) && (fg & (1 << colourMode))))
osdWindow.display[colourMode][addr] |= 0x80 >> bitOffset;
else
osdWindow.display[colourMode][addr] &= ~(0x80 >> bitOffset);
if(osdWindow.debug && colourMode == 0) { printf("*"); }
}
else if(bg & (1 << colourMode))
else if(((attr & HILIGHT_BG_ACTIVE) && ((attr&~HILIGHT_BG_ACTIVE) & (1 << colourMode))) || (!(attr & HILIGHT_BG_ACTIVE) && (bg & (1 << colourMode))))
{
osdWindow.display[colourMode][addr] |= 0x80 >> bitOffset;
if(osdWindow.debug && colourMode == 0) { printf(" "); }
@@ -475,13 +486,13 @@ void _OSDwrite(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad, uin
if(vChrRow & (1 << (row % 8)))
{
if(fg & (1 << colourMode))
if(((attr & HILIGHT_FG_ACTIVE) && ((attr&~HILIGHT_FG_ACTIVE) & (1 << colourMode))) || (!(attr & HILIGHT_FG_ACTIVE) && (fg & (1 << colourMode))))
osdWindow.display[colourMode][addr] |= 0x80 >> bitOffset;
else
osdWindow.display[colourMode][addr] &= ~(0x80 >> bitOffset);
if(osdWindow.debug && colourMode == 0) { printf("*"); }
}
else if(bg & (1 << colourMode))
else if(((attr & HILIGHT_BG_ACTIVE) && ((attr&~HILIGHT_BG_ACTIVE) & (1 << colourMode))) || (!(attr & HILIGHT_BG_ACTIVE) && (bg & (1 << colourMode))))
{
osdWindow.display[colourMode][addr] |= 0x80 >> bitOffset;
if(osdWindow.debug && colourMode == 0) { printf(" "); }
@@ -517,8 +528,7 @@ void OSDWriteBitmap(uint16_t x, uint16_t y, enum BITMAPS bitmap, enum COLOUR fg,
// Check parameters.
if(x >= osdWindow.params[osdWindow.mode].maxX || y >= osdWindow.params[osdWindow.mode].maxY)
{
if(osdWindow.debug)
printf("Bitmap coordinates out of range:(%d,%d)\n", x, y);
debugf("Bitmap coordinates out of range:(%d,%d)\n", x, y);
return;
}
@@ -579,14 +589,14 @@ void OSDWriteChar(uint8_t x, uint8_t y, uint8_t xoff, uint8_t yoff, uint8_t xpad
// Locals.
//
_OSDwrite(x, y, xoff, yoff, xpad, ypad, orientation, chr, fg, bg, OSDGetFont(font));
_OSDwrite(x, y, xoff, yoff, xpad, ypad, orientation, chr, NOATTR, fg, bg, OSDGetFont(font));
return;
}
// Method to write a string to the required framebuffer. The X/Y co-ordinates are relative to the orientation, ie. start - NORMAL=0/0, DEG90 = maxX-font width/0,
// DEG180 = maxX-font width/maxY-font height, DEG270 = 0/maxY-font height.
//
void OSDWriteString(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad, uint8_t ypad, enum FONTS font, enum ORIENTATION orientation, char *str, enum COLOUR fg, enum COLOUR bg)
void OSDWriteString(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad, uint8_t ypad, enum FONTS font, enum ORIENTATION orientation, char *str, uint16_t *attr, enum COLOUR fg, enum COLOUR bg)
{
// Locals.
//
@@ -597,6 +607,8 @@ void OSDWriteString(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad
uint8_t maxY;
uint8_t xpos = x;
uint8_t ypos = y;
uint8_t *ptr;
uint16_t *aptr;
// Obtain the font structure based on the provided type.
fontptr = OSDGetFont(font);
@@ -635,9 +647,9 @@ void OSDWriteString(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad
}
// Output the string.
for(uint8_t *ptr=str; *ptr != 0x00; ptr++)
for(ptr=str,aptr=attr; *ptr != 0x00; ptr++, aptr++)
{
_OSDwrite(xpos++, ypos, xoff, yoff, xpad, ypad, orientation, (*ptr), fg, bg, fontptr);
_OSDwrite(xpos++, ypos, xoff, yoff, xpad, ypad, orientation, (*ptr), (attr != NULL ? (*aptr) : NOATTR), fg, bg, fontptr);
if(xpos > maxX)
{
@@ -654,6 +666,28 @@ void OSDWriteString(uint8_t x, uint8_t y, int8_t xoff, int8_t yoff, uint8_t xpad
return;
}
// Method to refresh the OSD size parameters from the hardware. This is required should the screen resolution change which may change
// OSD size.
void OSDUpdateScreenSize(void)
{
// Locals.
uint8_t result;
uint8_t osdInData[8];
// Read the OSD Size parameters. These represent the X and Y size once multiplied by 8 (8 being the minimum size, ie. block size).
//
result=readZ80Array(VCADDR_8BIT_OSDMNU_SZX, osdInData, 6, FPGA);
if(!result)
{
osdWindow.params[STATUS].maxX = (uint16_t)(osdInData[2] * 8);
osdWindow.params[STATUS].maxY = (uint16_t)(osdInData[3] * 8) + (uint16_t)(osdInData[5] * 8);
osdWindow.params[MENU].maxX = (uint16_t)(osdInData[0] * 8);
osdWindow.params[MENU].maxY = (uint16_t)(osdInData[1] * 8);
}
return;
}
// Method to refresh the active screen from the buffer contents.
void OSDRefreshScreen(void)
{
@@ -863,6 +897,101 @@ void OSDSetActiveWindow(enum WINDOWS window)
return;
}
// Method to setup the data structures and enable flashing of a cursor at a given point, in a given font wth necessary attributes.
// This mechanism is used for data entry where the next character typically appears at the flashing curspr.
void OSDSetCursorFlash(uint8_t col, uint8_t row, uint8_t offsetCol, uint8_t offsetRow, enum FONTS font, uint8_t dispChar, enum COLOUR fg, enum COLOUR bg, uint16_t attr, unsigned long speed)
{
// Disable any active cursor.
if(osdWindow.params[osdWindow.mode].cursor.enabled)
OSDClearCursorFlash();
// Store the given cursor data.
osdWindow.params[osdWindow.mode].cursor.row = row;
osdWindow.params[osdWindow.mode].cursor.col = col;
osdWindow.params[osdWindow.mode].cursor.ofrow = offsetRow;
osdWindow.params[osdWindow.mode].cursor.ofcol = offsetCol;
osdWindow.params[osdWindow.mode].cursor.font = font;
osdWindow.params[osdWindow.mode].cursor.dispChar = dispChar;
osdWindow.params[osdWindow.mode].cursor.attr = attr;
osdWindow.params[osdWindow.mode].cursor.fg = fg;
osdWindow.params[osdWindow.mode].cursor.bg = bg;
osdWindow.params[osdWindow.mode].cursor.speed = speed;
// Enable the cursor.
osdWindow.params[osdWindow.mode].cursor.enabled = 1;
osdWindow.params[osdWindow.mode].cursor.flashing = 0;
return;
}
// Method to clear any running cursor and restore the character under the cursor.
//
void OSDClearCursorFlash(void)
{
// Locals.
char lineBuf[2];
// Verify there is an active cursor.
if(osdWindow.params[osdWindow.mode].cursor.enabled)
{
// Restore the character under the cursor to original value.
lineBuf[0] = osdWindow.params[osdWindow.mode].cursor.dispChar;
lineBuf[1] = 0x00;
OSDWriteString(osdWindow.params[osdWindow.mode].cursor.col, osdWindow.params[osdWindow.mode].cursor.row, osdWindow.params[osdWindow.mode].cursor.ofcol, osdWindow.params[osdWindow.mode].cursor.ofrow, 0, 0, osdWindow.params[osdWindow.mode].cursor.font, NORMAL, lineBuf, NULL, osdWindow.params[osdWindow.mode].cursor.fg, osdWindow.params[osdWindow.mode].cursor.bg);
OSDRefreshScreen();
// Disable the cursor flashing.
osdWindow.params[osdWindow.mode].cursor.enabled = 0;
osdWindow.params[osdWindow.mode].cursor.flashing = 0;
}
return;
}
// Method to flash a cursor. This is based on a timer and using the hilight properties of text write, rewrites the character at the position where the cursor should
// appear in the correct format.
void OSDCursorFlash(void)
{
// Locals.
static unsigned long time = 0;
char lineBuf[2];
uint16_t attrBuf[2];
uint32_t timeElapsed;
// Get elapsed time since last service poll.
timeElapsed = *msecs - time;
// If the elapsed time is greater than the flash speed, toggle the flash state.
if(osdWindow.params[osdWindow.mode].cursor.enabled == 1 && timeElapsed > osdWindow.params[osdWindow.mode].cursor.speed)
{
lineBuf[0] = osdWindow.params[osdWindow.mode].cursor.dispChar;
lineBuf[1] = 0x00;
attrBuf[0] = osdWindow.params[osdWindow.mode].cursor.attr;
attrBuf[1] = 0x0000;
OSDWriteString(osdWindow.params[osdWindow.mode].cursor.col, osdWindow.params[osdWindow.mode].cursor.row, osdWindow.params[osdWindow.mode].cursor.ofcol, osdWindow.params[osdWindow.mode].cursor.ofrow, 0, 0, osdWindow.params[osdWindow.mode].cursor.font, NORMAL, lineBuf, osdWindow.params[osdWindow.mode].cursor.flashing == 0 ? NULL : attrBuf, osdWindow.params[osdWindow.mode].cursor.fg, osdWindow.params[osdWindow.mode].cursor.bg);
OSDRefreshScreen();
// Set to next flash state.
osdWindow.params[osdWindow.mode].cursor.flashing = osdWindow.params[osdWindow.mode].cursor.flashing == 0 ? 1 : 0;
// Reset the timer.
time = *msecs;
}
return;
}
// Method to allow for OSD periodic updates as needed.
//
void OSDService(void)
{
// Call the cursor flash routine to allow an interactive flashing cursor if enabled.
//
OSDCursorFlash();
return;
}
// Initialise the OSD subsystem. This method only needs to be called once, calling subsequent times will free and reallocate memory.
//
uint8_t OSDInit(enum WINDOWS window)
@@ -874,8 +1003,7 @@ uint8_t OSDInit(enum WINDOWS window)
// Allocate heap for the OSD display buffers. The size is set to the maximum required buffer.
if(osdWindow.display != NULL)
{
if(osdWindow.debug)
printf("Freeing OSD display framebuffer:%08lx\n", osdWindow.display);
debugf("Freeing OSD display framebuffer:%08lx\n", osdWindow.display);
free(osdWindow.display);
} else
{
@@ -888,8 +1016,7 @@ uint8_t OSDInit(enum WINDOWS window)
result = 1;
} else
{
if(osdWindow.debug)
printf("OSD window framebuffer allocated: %dBytes@%08lx\n", VC_MENU_RGB_BITS * VC_MENU_BUFFER_SIZE > VC_STATUS_RGB_BITS * VC_STATUS_BUFFER_SIZE ? VC_MENU_RGB_BITS * VC_MENU_BUFFER_SIZE : VC_STATUS_RGB_BITS * VC_STATUS_BUFFER_SIZE, osdWindow.display);
debugf("OSD window framebuffer allocated: %dBytes@%08lx\n", VC_MENU_RGB_BITS * VC_MENU_BUFFER_SIZE > VC_STATUS_RGB_BITS * VC_STATUS_BUFFER_SIZE ? VC_MENU_RGB_BITS * VC_MENU_BUFFER_SIZE : VC_STATUS_RGB_BITS * VC_STATUS_BUFFER_SIZE, osdWindow.display);
}
}

14
common/sharpmz.c
View File

@@ -952,14 +952,14 @@ void mzClearLine(int row, int colStart, int colEnd, uint8_t updPos)
uint8_t mzSetVGABorder(uint8_t vborder)
{
// Locals.
uint8_t mode = (uint8_t)*(volatile uint32_t *)(VCADDR_32BIT_VMBORDER) & VMBORDER_MASK;
uint8_t mode = (uint8_t)*(volatile uint32_t *)(VCADDR_32BIT_VMVGATTR) & VMBORDER_MASK;
// Sanity check parameters.
if(vborder != VMBORDER_BLACK && vborder != VMBORDER_BLUE && vborder != VMBORDER_RED && vborder != VMBORDER_PURPLE && vborder != VMBORDER_GREEN && vborder != VMBORDER_CYAN && vborder != VMBORDER_YELLOW && vborder != VMBORDER_WHITE)
return(1);
// Set the VGA Border.
*(volatile uint8_t *)(VCADDR_8BIT_VMBORDER) = mode | vborder;
*(volatile uint8_t *)(VCADDR_8BIT_VMVGATTR) = mode | vborder;
return(0);
}
@@ -968,27 +968,27 @@ uint8_t mzSetVGABorder(uint8_t vborder)
uint8_t mzSetVGAMode(uint8_t vgamode)
{
// Locals.
uint8_t mode = (uint8_t)*(volatile uint32_t *)(VCADDR_32BIT_VMCTRL) & VMMODE_VGA_MASK;
uint8_t mode = (uint8_t)*(volatile uint32_t *)(VCADDR_32BIT_VMVGAMODE) & VMMODE_VGA_MASK;
// Sanity check parameters.
if(vgamode != VMMODE_VGA_OFF && vgamode != VMMODE_VGA_640x480 && vgamode != VMMODE_VGA_1024x768 && vgamode != VMMODE_VGA_800x600)
if(vgamode != VMMODE_VGA_OFF && vgamode != VMMODE_VGA_640x480 && vgamode != VMMODE_VGA_800x600)
return(1);
// Set the VGA mode.
*(volatile uint8_t *)(VCADDR_8BIT_VMCTRL) = mode | vgamode;
*(volatile uint8_t *)(VCADDR_8BIT_VMVGAMODE) = mode | vgamode;
return(0);
}
// Method to set the screen mode, ie. machine video being emulated.
//
uint8_t mzSetMachineVideoMode(uint8_t hwmode)
uint8_t mzSetMachineVideoMode(uint8_t vmode)
{
// Locals.
uint8_t mode = (uint8_t)*(volatile uint32_t *)(VCADDR_32BIT_VMCTRL) & VMMODE_MASK;
// Sanity check parameters.
if(hwmode != VMMODE_MZ80K && hwmode != VMMODE_MZ80C && hwmode != VMMODE_MZ1200 && hwmode != VMMODE_MZ80A && hwmode != VMMODE_MZ700 && hwmode != VMMODE_MZ800 && hwmode != VMMODE_MZ80B && hwmode != VMMODE_MZ2000)
if(vmode != VMMODE_MZ80K && vmode != VMMODE_MZ80C && vmode != VMMODE_MZ1200 && vmode != VMMODE_MZ80A && vmode != VMMODE_MZ700 && vmode != VMMODE_MZ1500 && vmode != VMMODE_MZ800 && vmode != VMMODE_MZ80B && vmode != VMMODE_MZ2000 && vmode != VMMODE_MZ2200 && vmode != VMMODE_MZ2500)
return(1);
// Set the hardware video mode.

846
common/tranzputer.c
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File diff suppressed because it is too large Load Diff

361
include/emumz.h
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@@ -50,33 +50,31 @@
#define MAX_MACHINE_TITLE_LEN 15 // Maximum length of the side bar machine name title.
#define MAX_DIRENTRY 512 // Maximum number of read and stored directory entries from the SD card per directory.
#define MAX_DIR_DEPTH 4 // Maximum depth of sub-directories to enter.
#define MAX_FILENAME_LEN 256 // Maximum supported length of a filename.
#define MAX_FILENAME_LEN 64 // Maximum supported length of a filename.
#define MAX_FILTER_LEN 8 // Maximum length of a file filter.
#define TOPLEVEL_DIR "0:\\" // Top level directory for file list and select.
#define MAX_TAPE_QUEUE 5 // Maximum number of files which can be queued in the virtual tape drive.
#define CONFIG_FILENAME "0:\\EMZ.CFG" // Configuration file for persisting the configuration.
#define MAX_EMU_REGISTERS 16 // Number of programmable registers in the emulator.
#define MAX_KEY_INS_BUFFER 64 // Maximum number of key sequences in a FIFO which can be inserted into the emulation keyboard.
#define MAX_INJEDIT_ROWS 4 // Maximum number of rows in the key injection editor.
#define MAX_INJEDIT_COLS 8 // Maximum number of columns in the key injection editor.
// Keyboard key-injection constants.
#define KEY_INJEDIT_NIBBLES 8 // Number of nibbles in an injected key word.
#define KEY_INJEDIT_ROWS (MAX_KEY_INS_BUFFER/MAX_INJEDIT_COLS)
#define KEY_INJEDIT_NIBBLES_PER_ROW (MAX_INJEDIT_COLS*KEY_INJEDIT_NIBBLES)
// Maximum number of machines currently supported by the emulation.
//
#define MAX_MZMACHINES 8
// Numeric index of each machine.
//
#define MZ80K_IDX 0 // 000
#define MZ80C_IDX 1 // 001
#define MZ1200_IDX 2 // 010
#define MZ80A_IDX 3 // 011
#define MZ700_IDX 4 // 100
#define MZ800_IDX 5 // 101
#define MZ80B_IDX 6 // 110
#define MZ2000_IDX 7 // 111
#define MAX_MZMACHINES 11
// Keyboard control bits.
//
#define KEY_BREAK_BIT 0x80 // Break key is being pressed when set to 1
#define KEY_CTRL_BIT 0x40 // CTRL key is being pressed when set to 1
#define KEY_SHIFT_BIT 0x20 // SHIFT key is being pressed when set to 1
#define KEY_NOCTRL_BIT 0x00 // No key control overrides.
#define KEY_DOWN_BIT 0x02 // DATA key has been pressed when set to 1
#define KEY_UP_BIT 0x01 // DATA key has been released when set to 1
@@ -84,12 +82,21 @@
//
#define MZ_EMU_ROM_ADDR 0x100000 // Sharp MZ Series Emulation ROM address.
#define MZ_EMU_RAM_ADDR 0x120000 // Sharp MZ Series Emulation RAM address.
#define MZ_EMU_CGROM_ADDR 0x220000 // VideoController CGROM address.
#define MZ_EMU_USER_ROM_ADDR 0x12E800 // Sharp MZ Series Emulation USER ROM address.
#define MZ_EMU_FDC_ROM_ADDR 0x12F000 // Sharp MZ Series Emulation FDC ROM address.
#define MZ_EMU_REG_BASE_ADDR 0x300000 // Base address, in the FPGA address domain, of the emulator registers.
#define MZ_EMU_REG_INTR_ADDR 0x300020 // Base address of the interrupt generator.
#define MZ_EMU_REG_KEYB_ADDR 0x300200 // Base address of the keyboard register and map table.
#define MZ_EMU_REG_SND_ADDR 0x300200 // Base address of the sound generator.
#define MZ_EMU_REG_KEYB_ADDR 0x301000 // Base address of the keyboard register and map table.
#define MZ_EMU_CMT_HDR_ADDR 0x340000 // Header RAM - 128 bytes 0x340000:0x34FFFF
#define MZ_EMU_CMT_DATA_ADDR 0x350000 // Data RAM - 64KBytes. 0x350000:0x35FFFF
#define MZ_EMU_CMT_MAP_ADDR 0x360000 // ASCII MAP RAM - 512 bytes 0x360000:0x36FFFF
#define MZ_EMU_CMT_REG_ADDR 0x360200 // CMT Registers.
// Registers within the Machine Control module. Some of the data provided within these registers
// is also available directly from the hardware modules.
#define MZ_EMU_MAX_REGISTERS 16 // Maximum number of registers on the emulator.
#define MZ_EMU_REG_MODEL 0 // Machine MODEL configuration register.
#define MZ_EMU_REG_DISPLAY 1 // DISPLAY configuration register 1.
#define MZ_EMU_REG_DISPLAY2 2 // DISPLAY configuration register 2.
@@ -101,8 +108,11 @@
#define MZ_EMU_REG_CMT3 8 // CMT (tape drive) status register.
#define MZ_EMU_REG_USERROM 9 // USER ROM selection register (not currently used.)
#define MZ_EMU_REG_FDCROM 10 // Floppy Disk ROM selection register.
#define MZ_EMU_REG_SWITCHES 11 // Hardware switches, MZ800 = 3:0
#define MZ_EMU_REG_SETUP 13 // Emulator current setup (configuration) register.
#define MZ_EMU_MAX_REGISTERS 16 // Maximum number of registers on the emulator.
#define MZ_EMU_REG_CTRL 15 // Emulator control register.
// Physical address of the registers within the Machine Control module.
#define MZ_EMU_ADDR_REG_MODEL MZ_EMU_REG_BASE_ADDR + 0 // Address of the machine MODEL configuration register.
#define MZ_EMU_ADDR_REG_DISPLAY MZ_EMU_REG_BASE_ADDR + 1 // Address of the DISPLAY configuration register 1.
#define MZ_EMU_ADDR_REG_DISPLAY2 MZ_EMU_REG_BASE_ADDR + 2 // Address of the DISPLAY configuration register 2.
@@ -115,20 +125,44 @@
#define MZ_EMU_ADDR_REG_USERROM MZ_EMU_REG_BASE_ADDR + 9 // Address of the USER ROM selection register (not currently used.).
#define MZ_EMU_ADDR_REG_FDCROM MZ_EMU_REG_BASE_ADDR + 10 // Address of the Floppy Disk ROM selection register.
#define MZ_EMU_ADDR_REG_SETUP MZ_EMU_REG_BASE_ADDR + 13 // Address of the emulator current setup (configuration) register.
#define MZ_EMU_INTR_ISR 0x00 // Interupt service reason register, define what caused the interupt.
#define MZ_EMU_ADDR_REG_CTRL MZ_EMU_REG_BASE_ADDR + 15 // Address of the Control reigster.
// Interrupt generator control and status registers.
#define MZ_EMU_INTR_MAX_REGISTERS 1 // Maximum number of registers in the interrupt generator.
#define MZ_EMU_KEYB_MAX_REGISTERS 37 // Maximum number of registers in the keyboard interface.
#define MZ_EMU_KEYB_KEY_MATRIX 0x00 // Key matrix array current scan.
#define MZ_EMU_KEYB_KEY_MATRIX_LAST 0x10 // Key matrix array previous scan.
#define MZ_EMU_KEYB_CTRL_REG 0x20 // Keyboard control register.
#define MZ_EMU_KEYB_KEYD_REG 0x21 // Keyboard key data register.
#define MZ_EMU_KEYB_KEYC_REG 0x22 // Keyboard control data register.
#define MZ_EMU_KEYB_KEY_POS_REG 0x23 // Keyboard mapped character mapping position.
#define MZ_EMU_KEYB_KEY_POS_LAST_REG 0x24 // Keyboard mapped character previous mapping position.
#define MZ_EMU_KEYB_MAP_ADDR 0x100 // Address offset to the scan code:key map array.
#define MZ_EMU_INTR_REG_ISR 0x00 // Interupt service reason register, define what caused the interupt.
#define MZ_EMU_INTR_SRC_KEYB 0x01 // Interrupt source = Keyboard.
#define MZ_EMU_INTR_SRC_CMT 0x02 // Interrupt source = CMT.
// Cassette module control and status registers.
#define MZ_EMU_CMT_MAX_REGISTERS 0x04 // Maximum number of registers in the cmt interface.
#define MZ_EMU_CMT_STATUS_REG 0x00 // CMT status register.
#define MZ_EMU_CMT_STATUS2_REG 0x01 // CMT2 status register (APSS).
#define MZ_EMU_CMT_STATUS_INTR_REG 0x02 // CMT interrupt status trigger.
#define MZ_EMU_CMT_STATUS2_INTR_REG 0x03 // CMT2 interrupt status trigger.
// Keyboard control and status registers, mapping tables and cache.
#define MZ_EMU_KEYB_MAX_REGISTERS 8 // Maximum number of status and control registers in the keyboard interface, excludes debug registers.
#define MZ_EMU_KEYB_CTRL_REG 0x00 // Keyboard control register.
#define MZ_EMU_KEYB_FIFO_REG 0x01 // Key insertion FIFO control register.
#define MZ_EMU_KEYB_FIFO_WR_ADDR 0x02 // FIFO write pointer value.
#define MZ_EMU_KEYB_FIFO_RD_ADDR 0x03 // FIFO read pointer value.
#define MZ_EMU_KEYB_KEYC_REG 0x04 // Keyboard control data register.
#define MZ_EMU_KEYB_KEYD_REG 0x05 // Keyboard key data register.
#define MZ_EMU_KEYB_KEY_POS_REG 0x06 // Keyboard mapped character mapping position.
#define MZ_EMU_KEYB_KEY_POS_LAST_REG 0x07 // Keyboard mapped character previous mapping position.
#define MZ_EMU_KEYB_KEY_MATRIX 0x10 // Key matrix array current scan.
#define MZ_EMU_KEYB_KEY_MATRIX_LAST 0x20 // Key matrix array previous scan.
#define MZ_EMU_KEYB_FIFO_SIZE 0x40 // Size of the key insertion FIFO.
#define MZ_EMU_KEYB_FIFO_ADDR 0x0100 // Key insertion FIFO.
#define MZ_EMU_KEYB_MAP_ADDR 0x0800 // Address of the emulation keyboard mapping table.
#define MZ_EMU_KEYB_IOP_MAP_ADDR 0x0900 // Address offset to the scan code:key map array for the I/O processor keys.
#define MZ_EMU_KEYB_DISABLE_EMU 0x01 // Disable keyboard scan codes being sent to the emulation.
#define MZ_EMU_KEYB_ENABLE_INTR 0x02 // Enable interrupt on every key press.
#define MZ_EMU_KEYB_SEND_KEY_EVENTS 0x04 // Send keyboard up and down interrupt events.
#define MZ_EMU_KEYB_FIFO_FULL 0x01 // Bit in FIFO Status register to indicate the FIFO is full.
#define MZ_EMU_KEYB_FIFO_WORD_RST 0x80 // Reset keyboard key insertion word pointer, 4 bytes are needed per word and this resets to the 1st byte in the word.
// Display control values.
#define MZ_EMU_DISPLAY_MONO 0x00 // Monochrome display.
#define MZ_EMU_DISPLAY_MONO80 0x01 // Monochrome 80 column display.
#define MZ_EMU_DISPLAY_COLOUR 0x02 // Colour display.
@@ -146,12 +180,12 @@
#define MZ_EMU_B_CPU_SPEED_16M 0x02 // CPU Freq for the MZ80B group machines.
#define MZ_EMU_B_CPU_SPEED_32M 0x03 // CPU Freq for the MZ80B group machines.
#define MZ_EMU_B_CPU_SPEED_64M 0x04 // CPU Freq for the MZ80B group machines.
#define MZ_EMU_C_CPU_SPEED_2M 0x00 // CPU Freq for the MZ80C group machines.
#define MZ_EMU_C_CPU_SPEED_4M 0x01 // CPU Freq for the MZ80C group machines.
#define MZ_EMU_C_CPU_SPEED_8M 0x02 // CPU Freq for the MZ80C group machines.
#define MZ_EMU_C_CPU_SPEED_16M 0x03 // CPU Freq for the MZ80C group machines.
#define MZ_EMU_C_CPU_SPEED_32M 0x04 // CPU Freq for the MZ80C group machines.
#define MZ_EMU_C_CPU_SPEED_64M 0x05 // CPU Freq for the MZ80C group machines.
#define MZ_EMU_C_CPU_SPEED_2M 0x00 // CPU Freq for the MZ80K group machines.
#define MZ_EMU_C_CPU_SPEED_4M 0x01 // CPU Freq for the MZ80K group machines.
#define MZ_EMU_C_CPU_SPEED_8M 0x02 // CPU Freq for the MZ80K group machines.
#define MZ_EMU_C_CPU_SPEED_16M 0x03 // CPU Freq for the MZ80K group machines.
#define MZ_EMU_C_CPU_SPEED_32M 0x04 // CPU Freq for the MZ80K group machines.
#define MZ_EMU_C_CPU_SPEED_64M 0x05 // CPU Freq for the MZ80K group machines.
#define MZ_EMU_78_CPU_SPEED_3M5 0x00 // CPU Freq for the MZ80/700/800 group machines.
#define MZ_EMU_78_CPU_SPEED_7M 0x01 // CPU Freq for the MZ80/700/800 group machines.
#define MZ_EMU_78_CPU_SPEED_14M 0x02 // CPU Freq for the MZ80/700/800 group machines.
@@ -215,11 +249,14 @@ enum MENUMODE {
enum MENUACTIVE {
MENU_DISABLED = 0x00, // Menu is disabled and not being displayed.
MENU_MAIN = 0x01, // Main menu is active.
MENU_STORAGE = 0x02, // Storage menu is active.
MENU_MACHINE = 0x03, // Machine menu is active.
MENU_DISPLAY = 0x04, // Display menu is active.
MENU_SYSTEM = 0x05, // System menu is active.
MENU_ROMMANAGEMENT = 0x06 // Rom Management menu is active.
MENU_TAPE_STORAGE = 0x02, // Tape Storage menu is active.
MENU_FLOPPY_STORAGE = 0x03, // Floppy Storage menu is active.
MENU_MACHINE = 0x04, // Machine menu is active.
MENU_DISPLAY = 0x05, // Display menu is active.
MENU_AUDIO = 0x06, // Audio menu is active.
MENU_SYSTEM = 0x07, // System menu is active.
MENU_ROMMANAGEMENT = 0x08, // Rom Management menu is active.
MENU_AUTOSTART = 0x09 // Autostart Application menu is active.
};
enum MENUCALLBACK {
@@ -230,6 +267,7 @@ enum MENUCALLBACK {
enum DIALOGTYPE {
DIALOG_MENU = 0x00, // OSD is displaying the Menu system.
DIALOG_FILELIST = 0x01, // OSD is displaying a file list selection screen.
DIALOG_KEYENTRY = 0x02, // OSD is updating the key injection values.
};
enum ACTIONMODE {
@@ -245,17 +283,45 @@ typedef void (*t_menuCallback)(uint8_t);
// Declare the choice callback as a type. This callback is used when rendering the menu and the choice value needs to be realised from the config settings.
typedef const char * (*t_choiceCallback)(void);
// Declare the data view callback as a type. This callback is used when rendering the menu and non menu data requires rendering as read only.
typedef void (*t_viewCallback)(void);
// Ditto but for in function rendering.
typedef void (*t_renderCallback)(uint16_t);
// Declare the return from dialog callback which is required to process data from a non-menu dialog such as a file list.
typedef void (*t_dialogCallback)(char *param);
// Structure to map an ascii key into a row and column scan code.
typedef struct {
uint8_t scanRow; // Emulation scan row.
uint8_t scanCol; // Emulation scan column.
uint8_t scanCtrl; // Emulation control key overrides for the row/col combination.
} t_scanCode;
// Structure to map an ascii key into a row and column scan code.
typedef struct {
uint8_t key; // Ascii key for lookup.
t_scanCode code[MAX_MZMACHINES]; // Scan code per machine.
} t_scanMap;
// Type translation union.
typedef union {
uint32_t i;
uint8_t b[sizeof (float)];
float f;
} t_numCnv;
// Structure to contain a menu item and its properties.
//
typedef struct {
char text[MENU_ROW_WIDTH]; // Buffers to store menu item text.
char hotKey; // Shortcut key to activate selection, NULL = disabled.
enum MENUTYPES type; // Type of menu option, sub-menu select or choice.
enum MENUSTATE state; // State of the menu item, ie. hidden, greyed, active.
t_menuCallback menuCallback; // Function to call when a line is activated, by CR or toggle.
t_choiceCallback choiceCallback; // Function to call when a choice value is required.
t_viewCallback viewCallback; // Function to call when non-menu data requires rendering within the menu.
enum MENUCALLBACK cbAction; // Action to take after callback completed.
} t_menuItem;
@@ -317,6 +383,16 @@ typedef struct
uint32_t loadSize;
} romData_t;
// Structure to store the cold boot application details which gets loaded on machine instantiation.
//
typedef struct
{
char appFileName[MAX_FILENAME_LEN];
uint8_t appEnabled;
t_numCnv preKeyInsertion[MAX_KEY_INS_BUFFER];
t_numCnv postKeyInsertion[MAX_KEY_INS_BUFFER];
} appData_t;
// MZ Series Tape header structure - 128 bytes.
//
typedef struct
@@ -343,13 +419,55 @@ typedef struct
uint16_t elements;
} t_tapeQueue;
// Structure to store the parameters for key insertion editting.
//
typedef struct
{
// Pointer into the key buffer. This pointer points to the start of the buffer.
t_numCnv *bufptr;
// Pointer to the key being editted. This is nibble level, so 2 nibbles per byte.
uint16_t editptr;
// Cursor attribute for cursor highlighting.
uint16_t cursorAttr;
// Colour of the dislayed character,
enum COLOUR fg;
enum COLOUR bg;
// Location in the framebuffer where the character buffer commences.
uint8_t startRow;
uint8_t startCol;
// Screen offsets to adjust for mixed fonts.
uint8_t offsetRow;
uint8_t offsetCol;
// Flash speed of the cursor in ms.
unsigned long cursorFlashRate;
// Font used for the underlying character.
enum FONTS font;
// Current view portal. Key buffer greater than 12x4 needs to be scrolled to access the entire buffer.
uint16_t curView;
// Function to render the buffer for updates etc.
t_renderCallback render;
} t_keyInjectionEdit;
// Structure to maintain individual emulation configuration parameters.
typedef struct {
uint8_t cpuSpeed;
uint8_t audioSource;
uint8_t audioVolume;
uint8_t audioMute;
uint8_t cpuSpeed; // Select the CPU speed, original or multiples.
uint8_t memSize; // Select the memory size to match original machine.
uint8_t audioSource; // Select the audio source. Not used on the MZ-700
uint8_t audioHardware; // Select the audio hardware. Either driver the underlying host hardware directly or enable the FPGA sound hardware.
uint8_t audioVolume; // Set audio output volume.
uint8_t audioMute; // Mute audio output.
uint8_t audioMix; // Channel mix, blend left/right channel sound.
uint8_t displayType;
uint8_t displayOption;
uint8_t displayOutput;
uint8_t vramMode;
uint8_t gramMode;
@@ -364,6 +482,10 @@ typedef struct {
uint8_t tapeButtons;
uint8_t fastTapeLoad;
uint8_t cmtAsciiMapping; // Enable Sharp<->ASCII name conversion during Record/Play operations.
uint8_t mz800Mode; // MZ-800 Mode setting switch.
uint8_t mz800Printer; // MZ-800 Printer setting switch.
uint8_t mz800TapeIn; // MZ-800 Tape Input setting switch.
uint8_t autoStart; // Application autostart on machine instantiation.
char tapeSavePath[MAX_FILENAME_LEN]; // Path where saved files should be stored.
romData_t romMonitor40; // Details of 40x25 rom monitor image to upload.
romData_t romMonitor80; // Details of 80x25 rom monitor image to upload.
@@ -371,13 +493,15 @@ typedef struct {
romData_t romKeyMap; // Details of rom Key mapping images to upload.
romData_t romUser; // Details of User ROM images to upload.
romData_t romFDC; // Details of FDC ROM images to upload.
appData_t loadApp; // Details of an application to load on machine instantiation.
} t_emuMachineConfig;
// Structure to maintain the emulator configuration which is intended to mirror the physical hardware configuration.
typedef struct {
uint8_t machineModel; // Current emulated model.
enum MACHINE_TYPES machineModel; // Current emulated model.
enum MACHINE_GROUP machineGroup; // Group to which the current emulated model belongs.
uint8_t machineChanged; // Flag to indicate the base machine has changed.
t_emuMachineConfig *resetParams; // Copy of the default parameters.
// t_emuMachineConfig *resetParams; // Copy of the default parameters.
t_emuMachineConfig params[MAX_MZMACHINES]; // Working set of parameters.
uint8_t emuRegisters[MZ_EMU_MAX_REGISTERS]; // Mirror of the emulator register contents for local manipulation prior to sync.
} t_emuConfig;
@@ -405,8 +529,11 @@ typedef struct {
t_activeDir activeDir; // Active directory tree.
uint8_t debug; // Debug the emuMZ module by outputting log information if set.
t_menu menu; // Menu control and data.
enum MACHINE_HW_TYPES hostMachine; // Host hardware emulation being hosted on.
t_fileList fileList; // List of files for perusal and selection during OSD interaction.
t_tapeHeader tapeHeader; // Last processed tape details.
t_tapeQueue tapeQueue; // Linked list of files which together form a virtual tape.
t_keyInjectionEdit keyInjEdit; // Control structure for event callback editting of the key injection array.
} t_emuControl;
// Application execution constants.
@@ -414,57 +541,83 @@ typedef struct {
// Lookup tables for menu entries.
//
const char *MZMACHINES[MAX_MZMACHINES] = { "MZ-80K", "MZ-80C", "MZ1200", "MZ-80A", "MZ-700", "MZ-800", "MZ-80B", "MZ2000" };
const char *SHARPMZ_FAST_TAPE[] = { "Off", "2x", "4x", "8x", "16x", "32x", "Off", "Off",
"Off", "2x", "4x", "8x", "16x", "32x", "Off", "Off",
"Off", "2x", "4x", "8x", "16x", "Off", "Off", "Off"
const uint8_t MZ_ACTIVE[MAX_MZMACHINES] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 };
const char *MZMACHINES[MAX_MZMACHINES] = { "MZ-80K", "MZ-80C", "MZ1200", "MZ-80A", "MZ-700", "MZ-800", "MZ1500", "MZ-80B", "MZ2000", "MZ2200", "MZ2500" };
const char *SHARPMZ_FAST_TAPE[][6] = { { "Off", "2x", "4x", "8x", "16x", "32x" }, // Group MZ80K
{ "Off", "2x", "4x", "8x", "16x", "32x" }, // Group MZ700
{ "Off", "2x", "4x", "8x", "16x", NULL } // Group MZ80B
};
const char *SHARPMZ_CPU_SPEED[] = { "2MHz", "4MHz", "8MHz", "16MHz", "32MHz", "64MHz", "2MHz", "2MHz",
"3.5MHz", "7MHz", "14MHz", "28MHz", "56MHz", "3.5MHz", "3.5MHz", "3.5MHz",
"4MHz", "8MHz", "16MHz", "32MHz", "64MHz", "4MHz", "4MHz", "4MHz"
const char *SHARPMZ_CPU_SPEED[][7] = { { "2MHz", "4MHz", "8MHz", "16MHz", "32MHz", "64MHz", NULL }, // Group MZ80K
{ "3.5MHz", "7MHz", "14MHz", "28MHz", "56MHz", NULL, NULL }, // Group MZ700
{ "4MHz", "8MHz", "16MHz", "32MHz", "64MHz", NULL, NULL } // Group MZ80B
};
const char *SHARPMZ_TAPE_MODE[] = { "FPGA", "MZ-700" };
const char *SHARPMZ_MEM_SIZE[][3] = { { "32K", "48K", NULL }, // 80K
{ "32K", "48K", NULL }, // 80C
{ "32K", "48K", NULL }, // 1200
{ "32K", "48K", NULL }, // 80A
{ NULL, "64K", NULL }, // 700
{ NULL, "64K", NULL }, // 800
{ NULL, "64K", NULL }, // 1500
{ "32K", "64K", NULL }, // 80B
{ NULL, "64K", NULL }, // 2000
{ NULL, "64K", NULL }, // 2200
{ "64K", "128K", "256K" } // 2500
};
const char *SHARPMZ_TAPE_MODE[] = { "FPGA", "MZ CMT" };
const char *SHARPMZ_TAPE_BUTTONS[] = { "Off", "Play", "Record", "Auto" };
const char *SHARPMZ_ASCII_MAPPING[] = { "Off", "Record", "Play", "Both" };
const char *SHARPMZ_AUDIO_SOURCE[] = { "Sound", "Tape" };
const char *SHARPMZ_AUDIO_VOLUME[] = { "Max", "14", "13", "12", "11", "10", "9", "8", "7", "6", "5", "4", "3", "2", "1", "Min" };
const char *SHARPMZ_AUDIO_HARDWARE[] = { "Host", "FPGA" };
const char *SHARPMZ_AUDIO_VOLUME[] = { "Off", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "Max" };
const char *SHARPMZ_AUDIO_MUTE[] = { "Off", "Mute" };
const char *SHARPMZ_AUDIO_MIX [] = { "Off", "25%", "50%", "Mono" };
const char *SHARPMZ_USERROM_ENABLED[] = { "Disabled", "Enabled" };
const char *SHARPMZ_FDCROM_ENABLED[] = { "Disabled", "Enabled" };
const char *SHARPMZ_ROM_ENABLED[] = { "Disabled", "Enabled" };
const char *SHARPMZ_DISPLAY_TYPE[] = { "Mono 40x25", "Mono 80x25 ", "Colour 40x25", "Colour 80x25" };
const char *SHARPMZ_DISPLAY_OUTPUT[] = { "Original", "640x480@60Hz", "1024x768@60Hz", "800x600@60Hz" };
const char *SHARPMZ_DISPLAY_TYPE[][4] = {
{ "Mono 40x25", "Mono 80x25 ", NULL, NULL }, // 80K
{ "Mono 40x25", "Mono 80x25 ", NULL, NULL }, // 80C
{ "Mono 40x25", "Mono 80x25 ", NULL, NULL }, // 1200
{ "Mono 40x25", "Mono 80x25 ", "Colour 40x25", "Colour 80x25" }, // 80A
{ NULL, NULL, "Colour 40x25", "Colour 80x25" }, // 700
{ NULL, NULL, "Colour", NULL }, // 800
{ NULL, NULL, "Colour 40x25", "Colour 80x25" }, // 1500
{ NULL, NULL, NULL, NULL }, // 80B
{ NULL, NULL, NULL, NULL }, // 2000
{ NULL, NULL, NULL, NULL }, // 2200
{ NULL, NULL, NULL, NULL } // 2500
};
const char *SHARPMZ_DISPLAY_OPTION[][5] = { { "None", NULL, NULL, NULL, NULL }, // 80K
{ "None", NULL, NULL, NULL, NULL }, // 80C
{ "None", NULL, NULL, NULL, NULL }, // 1200
{ "None", "PCG", NULL, NULL, NULL }, // 80A
{ "None", "PCG", NULL, NULL, NULL }, // 700
{ "None", "MZ-1R25", NULL, NULL, NULL }, // 800
{ NULL, "PCG", NULL, NULL, NULL }, // 1500
{ "None", "GRAMI", "GRAMI/II", NULL, NULL }, // 80B
{ "None", "GRAMB", "GRAMB/R", " GRAMB/G", "GRAMB/R/G" }, // 2000
{ NULL, NULL, NULL, NULL, "GRAMB/R/G" }, // 2200
{ "None", NULL, NULL, NULL, NULL } // 2500
};
const char *SHARPMZ_DISPLAY_OUTPUT[] = { "Original", "Original 50Hz", "640x480@60Hz", "800x600@60Hz" };
const char *SHARPMZ_ASPECT_RATIO[] = { "4:3", "16:9" };
const char *SHARPMZ_SCANDOUBLER_FX[] = { "None", "HQ2x", "CRT 25%", "CRT 50%", "CRT 75%" };
const char *SHARPMZ_VRAMWAIT_MODE[] = { "Off", "On" };
const char *SHARPMZ_VRAMDISABLE_MODE[] = { "Enabled", "Disabled" };
const char *SHARPMZ_GRAMDISABLE_MODE[] = { "Enabled", "Disabled" };
const char *SHARPMZ_GRAM_BASEADDR[] = { "0x00", "0x08", "0x10", "0x18", "0x20", "0x28", "0x30", "0x38", "0x40", "0x48", "0x50", "0x58", "0x60", "0x68", "0x70", "0x78",
"0x80", "0x88", "0x90", "0x98", "0xA0", "0xA8", "0xB0", "0xB8", "0xC0", "0xC8", "0xD0", "0xD8", "0xE0", "0xE8", "0xF0", "0xF8" };
const char *SHARPMZ_PCG_MODE[] = { "Off", "ROM", "RAM" };
//const char *SHARPMZ_GRAM_BASEADDR[] = { "0x00", "0x08", "0x10", "0x18", "0x20", "0x28", "0x30", "0x38", "0x40", "0x48", "0x50", "0x58", "0x70", "0x78",
// "0x80", "0x88", "0x90", "0x98" };
const char *SHARPMZ_PCG_MODE[] = { "ROM", "RAM" };
const char *SHARPMZ_TAPE_AUTO_SAVE[] = { "Disabled", "Enabled" };
const char *SHARPMZ_DEBUG_ENABLE[] = { "Off", "On" };
const char *SHARPMZ_DEBUG_LEDS[] = { "Off", "On" };
const char *SHARPMZ_DEBUG_LEDS_BANK[] = { "T80", "I/O", "IOCTL", "Config", "MZ80C I", "MZ80C II", "MZ80B I", "MZ80B II" };
const char *SHARPMZ_DEBUG_LEDS_SUBBANK[] = { "Auto", "A7-0", "A15-8", "DI", "Signals", "", "", "",
"Auto", "Video", "PS2Key", "Signals", "CMT 1", "CMT 2", "CMT 3", "CMT 4",
"Auto", "A23-16", "A15-8", "A7-0", "Signals", "", "", "",
"Auto", "Config 1", "Config 2", "Config 3", "Config 4", "Config 5", "", "",
"Auto", "CS 1", "CS 2", "CS 3", "INT/RE", "Clk", "", "",
"Auto", "", "", "", "", "", "", "",
"Auto", "CS 1", "CS 2", "MEM EN", "INT", "KEYB", "PPIA", "PPIB",
"Auto", "PPIC", "", "", "", "", "", "",
};
const char *SHARPMZ_DEBUG_CPUFREQ[] = { "Normal", "1MHz", "100KHz", "10KHz", "5KHz", "1KHz", "500Hz", "100Hz", "50Hz", "10Hz", "5Hz", "2Hz", "1Hz", "0.5Hz", "0.2Hz", "0.1Hz" };
const char *SHARPMZ_DEBUG_LEDS_SMPFREQ[] = { "CPU", "1MHz", "100KHz", "10KHz", "5KHz", "1KHz", "500Hz", "100Hz", "50Hz", "10Hz", "5Hz", "2Hz", "1Hz", "0.5Hz", "0.2Hz", "0.1Hz" };
const char *SHARPMZ_AUTOSTART[] = { "Disabled", "Enabled" };
const char *SHARPMZ_MEMORY_BANK[] = { "SysROM", "SysRAM", "KeyMap", "VRAM", "CMTHDR", "CMTDATA", "CGROM", "CGRAM", "All" };
const char *SHARPMZ_MEMORY_BANK_FILE[] = { "sysrom.dump", "sysram.dump", "keymap.dump", "vram.dump", "cmt_hdr.dump", "cmt_data.dump", "cgrom.dump", "cgram.dump", "all_memory.dump" };
const char *SHARPMZ_TAPE_TYPE[] = { "N/A", "M/code", "MZ80 Basic", "MZ80 Data", "MZ700 Data", "MZ700 Basic", "N/A" };
const char *SHARPMZ_HELPTEXT[] = { "Welcome to the Sharp MZ Series! Use the cursor keys to navigate the menus. Use space bar or enter to select an item. Press Esc or F12 to exit the menus. ",
0
};
//const char *SHARPMZ_MEMORY_BANK_FILE[] = { "sysrom.dump", "sysram.dump", "keymap.dump", "vram.dump", "cmt_hdr.dump", "cmt_data.dump", "cgrom.dump", "cgram.dump", "all_memory.dump" };
const char *SHARPMZ_TAPE_TYPE[] = { "N/A", "M/code", "MZ80 Basic", "MZ80 Data", "MZ700 Data", "MZ700 Basic", "Unknown" };
const char *SHARPMZ_FILE_FILTERS[] = { "*.MZF", "*.MTI", "*.MZT", "*.*" };
const char *SHARPMZ_MZ800_MODE[] = { "MZ-800", "MZ-700" };
const char *SHARPMZ_MZ800_PRINTER[] = { "MZ", "Centronics" };
const char *SHARPMZ_MZ800_TAPEIN[] = { "External", "Internal" };
// Prototypes.
@@ -473,17 +626,26 @@ void EMZReleaseMenuMemory(void);
void EMZReleaseDirMemory(void);
void EMZSetupMenu(char *, char *, enum FONTS);
void EMZSetupDirList(char *, char *, enum FONTS);
void EMZAddToMenu(uint8_t, uint8_t, char *, enum MENUTYPES, enum MENUSTATE, t_menuCallback, enum MENUCALLBACK, t_choiceCallback);
void EMZAddToMenu(uint8_t, uint8_t, char *, char, enum MENUTYPES, enum MENUSTATE, t_menuCallback, enum MENUCALLBACK, t_choiceCallback, t_viewCallback);
int16_t EMZDrawMenu(int16_t, uint8_t, enum MENUMODE);
void EMZRefreshMenu(void);
void EMZRefreshFileList(void);
void EMZMainMenu(void);
void EMZTapeStorageMenu(enum ACTIONMODE);
void EMZFloppyStorageMenu(enum ACTIONMODE);
void EMZMachineMenu(enum ACTIONMODE);
void EMZDisplayMenu(enum ACTIONMODE);
void EMZAudioMenu(enum ACTIONMODE);
void EMZSystemMenu(enum ACTIONMODE);
void EMZAbout(enum ACTIONMODE);
void EMZRomManagementMenu(enum ACTIONMODE);
void EMZAutoStartApplicationMenu(enum ACTIONMODE);
void EMZRenderPreKeyViewTop(void);
void EMZRenderPreKeyView(uint16_t);
void EMZRenderPostKeyViewTop(void);
void EMZRenderPostKeyView(uint16_t);
void EMZPreKeyEntry(void);
void EMZPostKeyEntry(void);
void EMZSwitchToMenu(int8_t);
void EMZProcessMenuKey(uint8_t, uint8_t);
void EMZservice(uint8_t);
@@ -500,9 +662,9 @@ uint16_t EMZGetFileListColumnWidth(void);
int16_t EMZDrawFileList(int16_t, uint8_t);
uint8_t EMZReadDirectory(const char *, const char *);
void EMZGetFile(void);
void EMZReset(unsigned long, unsigned long);
uint8_t EMZInit(uint8_t);
void EMZReset(void);
void EMZPrintTapeDetails(short);
void EMZLoadDirectToRAM(enum ACTIONMODE);
void EMZLoadDirectToRAMSet(char *);
void EMZQueueTape(enum ACTIONMODE);
@@ -521,22 +683,29 @@ void EMZUserROM(enum ACTIONMODE);
void EMZUserROMSet(char *);
void EMZFloppyDiskROM(enum ACTIONMODE);
void EMZFloppyDiskROMSet(char *);
void EMZLoadApplication(enum ACTIONMODE);
void EMZLoadApplicationSet(char *);
void EMZChangeLoadApplication(enum ACTIONMODE);
void EMZTapeQueuePushFile(char *);
char *EMZTapeQueuePopFile(void);
char *EMZTapeQueueAPSSSearch(char);
char *EMZNextTapeQueueFilename(char);
void EMZClearTapeQueue(void);
uint16_t EMZClearTapeQueue(void);
void EMZChangeCMTMode(enum ACTIONMODE);
short EMZReadTapeDetails(const char *);
short EMZLoadTapeToRAM(const char *, unsigned char);
short EMZSaveTapeFromCMT(const char *);
// Menu choice helper functions, increment to next choice.
void EMZNextMachineModel(enum ACTIONMODE);
void EMZNextCPUSpeed(enum ACTIONMODE);
void EMZNextMemSize(enum ACTIONMODE mode);
void EMZNextAudioSource(enum ACTIONMODE);
void EMZNextAudioHardware(enum ACTIONMODE);
void EMZNextAudioVolume(enum ACTIONMODE);
void EMZNextAudioMute(enum ACTIONMODE);
void EMZNextAudioMix(enum ACTIONMODE);
// Getter/Setter methods!
void EMZSetMenuRowPadding(uint8_t);
@@ -548,13 +717,16 @@ uint16_t EMZGetMenuColumnWidth(void);
const char *EMZGetMachineModelChoice(void);
char *EMZGetMachineTitle(void);
short EMZGetMachineGroup(void);
const char *EMZGetMachineModelChoice(void);
const char *EMZGetCPUSpeedChoice(void);
const char *EMZGetMemSizeChoice(void);
const char *EMZGetAudioSourceChoice(void);
const char *EMZGetAudioHardwareChoice(void);
const char *EMZGetAudioVolumeChoice(void);
const char *EMZGetAudioMuteChoice(void);
const char *EMZGetAudioMixChoice(void);
const char *EMZGetCMTModeChoice(void);
const char *EMZGetDisplayTypeChoice(void);
const char *EMZGetDisplayOptionChoice(void);
const char *EMZGetDisplayOutputChoice(void);
const char *EMZGetVRAMModeChoice(void);
const char *EMZGetGRAMModeChoice(void);
@@ -572,9 +744,18 @@ const char *EMZGetCGROMChoice(void);
const char *EMZGetKeyMappingROMChoice(void);
const char *EMZGetUserROMChoice(void);
const char *EMZGetFloppyDiskROMChoice(void);
const char *EMZGetTapeType(void);
const char *EMZGetLoadApplicationChoice(void);
const char *EMZGetAutoStartChoice(void);
const char *EMZGetMZ800ModeChoice(void);
const char *EMZGetMZ800PrinterChoice(void);
const char *EMZGetMZ800TapeInChoice(void);
void EMZNextCMTMode(enum ACTIONMODE);
void EMZNextDisplayType(enum ACTIONMODE);
void EMZNextDisplayOption(enum ACTIONMODE);
uint8_t EMZGetDisplayOptionValue(void);
uint8_t EMZGetMemSizeValue(void);
void EMZNextDisplayOutput(enum ACTIONMODE);
void EMZNextVRAMMode(enum ACTIONMODE);
void EMZNextGRAMMode(enum ACTIONMODE);
@@ -591,11 +772,27 @@ void EMZNextCGROM(enum ACTIONMODE);
void EMZNextKeyMappingROM(enum ACTIONMODE);
void EMZNextUserROM(enum ACTIONMODE);
void EMZNextFloppyDiskROM(enum ACTIONMODE);
void EMZNextLoadApplication(enum ACTIONMODE);
void EMZNextMZ800Mode(enum ACTIONMODE mode);
void EMZNextMZ800Printer(enum ACTIONMODE mode);
void EMZNextMZ800TapeIn(enum ACTIONMODE mode);
#ifdef __cplusplus
}
#endif
#endif // EMUMZ_H
// Pseudo 'public' method prototypes.
#ifdef __cplusplus
extern "C" {
#endif
uint8_t EMZInit(enum MACHINE_HW_TYPES hostMachine);
void EMZRun(uint8_t);
const char *EMZGetVersion(void);
const char *EMZGetVersionDate(void);
#ifdef __cplusplus
}
#endif

209
include/osd.h
View File

@@ -68,31 +68,38 @@
#define VC_8BIT_BASE_ADDR VIDEO_BASE_ADDR + 0x000000
#define VC_32BIT_BASE_ADDR VIDEO_BASE_ADDR + 0x000000
// 8 Bit access addresses - used for writing, read can only be on a 32bit boundary with lower address lines set to 00. Writing can write upto 4 consecutive addresses if desired.
#define VCADDR_8BIT_PALSLCTOFF VC_8BIT_BASE_ADDR + 0xD3 // Set the palette slot Off position to be adjusted.
#define VCADDR_8BIT_PALSLCTON VC_8BIT_BASE_ADDR + 0xD4 // Set the palette slot On position to be adjusted.
#define VCADDR_8BIT_PALSETRED VC_8BIT_BASE_ADDR + 0xD5 // Set the red palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_8BIT_PALSETGREEN VC_8BIT_BASE_ADDR + 0xD6 // Set the green palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_8BIT_PALSETBLUE VC_8BIT_BASE_ADDR + 0xD7 // Set the blue palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_8BIT_PALSLCTOFF VC_8BIT_BASE_ADDR + 0xA3 // Set the palette slot Off position to be adjusted.
#define VCADDR_8BIT_PALSLCTON VC_8BIT_BASE_ADDR + 0xA4 // Set the palette slot On position to be adjusted.
#define VCADDR_8BIT_PALSETRED VC_8BIT_BASE_ADDR + 0xA5 // Set the red palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_8BIT_PALSETGREEN VC_8BIT_BASE_ADDR + 0xA6 // Set the green palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_8BIT_PALSETBLUE VC_8BIT_BASE_ADDR + 0xA7 // Set the blue palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_8BIT_OSDMNU_SZX VC_8BIT_BASE_ADDR + 0xA8 // Get OSD Menu Horizontal Size (X).
#define VCADDR_8BIT_OSDMNU_SZY VC_8BIT_BASE_ADDR + 0xA9 // Get OSD Menu Vertical Size (Y).
#define VCADDR_8BIT_OSDHDR_SZX VC_8BIT_BASE_ADDR + 0xAA // Get OSD Status Header Horizontal Size (X).
#define VCADDR_8BIT_OSDHDR_SZY VC_8BIT_BASE_ADDR + 0xAB // Get OSD Status Header Vertical Size (Y).
#define VCADDR_8BIT_OSDFTR_SZX VC_8BIT_BASE_ADDR + 0xAC // Get OSD Status Footer Horizontal Size (X).
#define VCADDR_8BIT_OSDFTR_SZY VC_8BIT_BASE_ADDR + 0xAD // Get OSD Status Footer Vertical Size (Y).
#define VCADDR_8BIT_VMPALETTE VC_8BIT_BASE_ADDR + 0xB0 // Sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output.
// Bits [7:0] defines the pallete number. This indexes a lookup table which contains the required 4bit output per 1bit input.
#define VCADDR_8BIT_GPUPARAM VC_8BIT_BASE_ADDR + 0xB2 // Set parameters. Store parameters in a long word to be used by the graphics command processor.
// The parameter word is 128 bit and each write to the parameter word shifts left by 8 bits and adds the new byte at bits 7:0.
#define VCADDR_8BIT_GPUCMD VC_8BIT_BASE_ADDR + 0xB3 // Set the graphics processor unit commands.
// Bits [5:0] - 0 = Reset parameters.
// 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter
#define VCADDR_8BIT_VMCTRL VC_8BIT_BASE_ADDR + 0xB8 // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define VCADDR_8BIT_VMGRMODE VC_8BIT_BASE_ADDR + 0xB9 // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define VCADDR_8BIT_VMREDMASK VC_8BIT_BASE_ADDR + 0xBA // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_8BIT_VMGREENMASK VC_8BIT_BASE_ADDR + 0xBB // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_8BIT_VMBLUEMASK VC_8BIT_BASE_ADDR + 0xBC // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_8BIT_VMPAGE VC_8BIT_BASE_ADDR + 0xBD // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
#define VCADDR_8BIT_VMVGATTR VC_8BIT_BASE_ADDR + 0xBE // Select VGA Border colour and attributes. Bit 2 = Red, 1 = Green, 0 = Blue, 4:3 = VGA Mode, 00 = Off, 01 = 640x480, 10 = 800x600, 11 = 50Hz Internal
#define VCADDR_8BIT_VMVGAMODE VC_8BIT_BASE_ADDR + 0xBF // Select VGA Output mode. [3:0] - required output resolution/frequency.
#define VCADDR_8BIT_SYSCTRL VC_8BIT_BASE_ADDR + 0xF0 // System board control register. [2:0] - 000 MZ80A Mode, 2MHz CPU/Bus, 001 MZ80B Mode, 4MHz CPU/Bus, 010 MZ700 Mode, 3.54MHz CPU/Bus.
#define VCADDR_8BIT_VMBORDER VC_8BIT_BASE_ADDR + 0xF3 // Select VGA Border colour attributes. Bit 2 = Red, 1 = Green, 0 = Blue.
#define VCADDR_8BIT_GRAMMODE VC_8BIT_BASE_ADDR + 0xF4 // MZ80B Graphics mode. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
#define VCADDR_8BIT_VMPALETTE VC_8BIT_BASE_ADDR + 0xF5 // Select Palette:
// 0xF5 sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output.
// Bits [7:0] defines the pallete number. This indexes a lookup table which contains the required 4bit output per 1bit input.
// GPU:
#define VCADDR_8BIT_GPUPARAM VC_8BIT_BASE_ADDR + 0xF6 // 0xF6 set parameters. Store parameters in a long word to be used by the graphics command processor.
// The parameter word is 128 bit and each write to the parameter word shifts left by 8 bits and adds the new byte at bits 7:0.
#define VCADDR_8BIT_GPUCMD VC_8BIT_BASE_ADDR + 0xF7 // 0xF7 set the graphics processor unit commands.
#define VCADDR_8BIT_GPUSTATUS VC_8BIT_BASE_ADDR + 0xF7 // [7;1] - FSM state, [0] - 1 = busy, 0 = idle
// Bits [5:0] - 0 = Reset parameters.
// 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter
//
#define VCADDR_8BIT_VMCTRL VC_8BIT_BASE_ADDR + 0xF8 // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define VCADDR_8BIT_VMGRMODE VC_8BIT_BASE_ADDR + 0xF9 // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define VCADDR_8BIT_VMREDMASK VC_8BIT_BASE_ADDR + 0xFA // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_8BIT_VMGREENMASK VC_8BIT_BASE_ADDR + 0xFB // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_8BIT_VMBLUEMASK VC_8BIT_BASE_ADDR + 0xFC // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_8BIT_VMPAGE VC_8BIT_BASE_ADDR + 0xFD // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
#define VCADDR_8BIT_KEYPA VC_8BIT_BASE_ADDR + 0xE000 // VideoModule 8255 Port A
#define VCADDR_8BIT_KEYPB VC_8BIT_BASE_ADDR + 0xE001 // VideoModule 8255 Port B
#define VCADDR_8BIT_KEYPC VC_8BIT_BASE_ADDR + 0xE002 // VideoModule 8255 Port C
@@ -205,20 +212,70 @@
#define IO_TZ_CLKSELRD 0x66 // Read the status of the clock select, ie. which clock is connected to the CPU.
#define IO_TZ_SVCREQ 0x68 // Service request from the Z80 to be provided by the K64F.
#define IO_TZ_SYSREQ 0x6A // System request from the Z80 to be provided by the K64F.
#define IO_TZ_CPLDSTATUS 0x6B // Version 2.1 CPLD status register.
#define IO_TZ_CPUCFG 0x6C // Version 2.2 CPU configuration register.
#define IO_TZ_CPUSTATUS 0x6C // Version 2.2 CPU runtime status register.
#define IO_TZ_CPUINFO 0x6D // Version 2.2 CPU information register.
#define IO_TZ_CPLDCFG 0x6E // Version 2.1 CPLD configuration register.
#define IO_TZ_CPLDSTATUS 0x6E // Version 2.1 CPLD status register.
#define IO_TZ_CPLDINFO 0x6F // Version 2.1 CPLD version information register.
#define IO_TZ_CPLDINFO 0x6F // Version 2.1 CPLD version information register.
#define IO_TZ_PALSLCTOFF 0xA3 // Set the palette slot (PALETTE_PARAM_SEL) Off position to be adjusted.
#define IO_TZ_PALSLCTON 0xA4 // Set the palette slot (PALETTE_PARAM_SEL) On position to be adjusted.
#define IO_TZ_PALSETRED 0xA5 // Set the red palette value according to the PALETTE_PARAM_SEL address.
#define IO_TZ_PALSETGREEN 0xA6 // Set the green palette value according to the PALETTE_PARAM_SEL address.
#define IO_TZ_PALSETBLUE 0xA7 // Set the blue palette value according to the PALETTE_PARAM_SEL address.
#define IO_TZ_OSDMNU_SZX 0xA8 // Get OSD Menu Horizontal Size (X).
#define IO_TZ_OSDMNU_SZY 0xA9 // Get OSD Menu Vertical Size (Y).
#define IO_TZ_OSDHDR_SZX 0xAA // Get OSD Status Header Horizontal Size (X).
#define IO_TZ_OSDHDR_SZY 0xAB // Get OSD Status Header Vertical Size (Y).
#define IO_TZ_OSDFTR_SZX 0xAC // Get OSD Status Footer Horizontal Size (X).
#define IO_TZ_OSDFTR_SZY 0xAD // Get OSD Status Footer Vertical Size (Y).
#define IO_TZ_PALETTE 0xB0 // Sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output.
// Bits [7:0] defines the pallete number. This indexes a lookup table which contains the required 4bit output per 1bit input.
#define IO_TZ_GPUPARAM 0xB2 // Set parameters. Store parameters in a long word to be used by the graphics command processor.
// The parameter word is 128 bit and each write to the parameter word shifts left by 8 bits and adds the new byte at bits 7:0.
#define IO_TZ_GPUCMD 0xB3 // Set the graphics processor unit commands.
// Bits [5:0] - 0 = Reset parameters.
// 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter
#define IO_TZ_VMCTRL 0xB8 // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define IO_TZ_VMGRMODE 0xB9 // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define IO_TZ_VMREDMASK 0xBA // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMGREENMASK 0xBB // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMBLUEMASK 0xBC // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMPAGE 0xBD // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
#define IO_TZ_VMVGATTR 0xBE // Select VGA Border colour and attributes. Bit 2 = Red, 1 = Green, 0 = Blue, 4:3 = VGA Mode, 00 = Off, 01 = 640x480, 10 = 800x600, 11 = 50Hz Internal
#define IO_TZ_VMVGAMODE 0xBF // Select VGA Output mode. [3:0] - required output resolution/frequency.
#define IO_TZ_GDGWF 0xCC // MZ-800 write format register
#define IO_TZ_GDGRF 0xCD // MZ-800 read format register
#define IO_TZ_GDCMD 0xCE // MZ-800 CRTC Mode register
#define IO_TZ_GDCMD 0xCF // MZ-800 CRTC control register
#define IO_TZ_MMIO0 0xE0 // MZ-700/MZ-800 Memory management selection ports.
#define IO_TZ_MMIO1 0xE1 // ""
#define IO_TZ_MMIO2 0xE2 // ""
#define IO_TZ_MMIO3 0xE3 // ""
#define IO_TZ_MMIO4 0xE4 // ""
#define IO_TZ_MMIO5 0xE5 // ""
#define IO_TZ_MMIO6 0xE6 // ""
#define IO_TZ_MMIO7 0xE7 // MZ-700/MZ-800 Memory management selection ports.
#define IO_TZ_PPIA 0xE0 // MZ80B/MZ2000 8255 PPI Port A
#define IO_TZ_PPIB 0xE1 // MZ80B/MZ2000 8255 PPI Port B
#define IO_TZ_PPIC 0xE2 // MZ80B/MZ2000 8255 PPI Port C
#define IO_TZ_PPICTL 0xE3 // MZ80B/MZ2000 8255 PPI Control Register
#define IO_TZ_PIT0 0xE4 // MZ80B/MZ2000 8253 PIT Timer 0
#define IO_TZ_PIT1 0xE5 // MZ80B/MZ2000 8253 PIT Timer 1
#define IO_TZ_PIT2 0xE6 // MZ80B/MZ2000 8253 PIT Timer 2
#define IO_TZ_PITCTL 0xE7 // MZ80B/MZ2000 8253 PIT Control Register
#define IO_TZ_PIOA 0xE8 // MZ80B/MZ2000 Z80 PIO Port A
#define IO_TZ_PIOCTLA 0xE9 // MZ80B/MZ2000 Z80 PIO Port A Control Register
#define IO_TZ_PIOB 0xEA // MZ80B/MZ2000 Z80 PIO Port B
#define IO_TZ_PIOCTLB 0xEB // MZ80B/MZ2000 Z80 PIO Port B Control Register
#define IO_TZ_SYSCTRL 0xF0 // System board control register. [2:0] - 000 MZ80A Mode, 2MHz CPU/Bus, 001 MZ80B Mode, 4MHz CPU/Bus, 010 MZ700 Mode, 3.54MHz CPU/Bus.
#define IO_TZ_GRAMMODE 0xF4 // MZ80B Graphics mode. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
#define IO_TZ_VMCTRL 0xF8 // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define IO_TZ_VMGRMODE 0xF9 // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define IO_TZ_VMREDMASK 0xFA // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMGREENMASK 0xFB // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMBLUEMASK 0xFC // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMPAGE 0xFD // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
//#define IO_TZ_GRAMOPT 0xF4 // MZ80B/MZ2000 GRAM configuration option.
#define IO_TZ_CRTGRPHPRIO 0xF5 // MZ2000 Graphics priority register, character or a graphics colour has front display priority.
#define IO_TZ_CRTGRPHSEL 0xF6 // MZ2000 Graphics output select on CRT or external CRT
#define IO_TZ_GRAMCOLRSEL 0xF7 // MZ2000 Graphics RAM colour bank select.
// IO register constants.
//
@@ -251,18 +308,22 @@
#define VMMODE_MZ80A 0x03 // Video mode = MZ80A
#define VMMODE_MZ700 0x04 // Video mode = MZ700
#define VMMODE_MZ800 0x05 // Video mode = MZ800
#define VMMODE_MZ80B 0x06 // Video mode = MZ80B
#define VMMODE_MZ2000 0x07 // Video mode = MZ2000
#define VMMODE_80CHAR 0x08 // Enable 80 character display.
#define VMMODE_80CHAR_MASK 0xF7 // Mask to filter out display width control bit.
#define VMMODE_COLOUR 0x10 // Enable colour display.
#define VMMODE_COLOUR_MASK 0xEF // Mask to filter out colour control bit.
#define VMMODE_PCGRAM 0x20 // Enable PCG RAM.
#define VMMODE_VGA_MASK 0x3F // Mask to filter out the VGA mode bits.
#define VMMODE_VGA_OFF 0x00 // Set VGA mode off, external monitor is driven by standard internal signals.
#define VMMODE_VGA_640x480 0x40 // Set external monitor to VGA 640x480 @ 60Hz mode.
#define VMMODE_VGA_1024x768 0x80 // Set external monitor to VGA 1024x768 @ 60Hz mode.
#define VMMODE_VGA_800x600 0xC0 // Set external monitor to VGA 800x600 @ 60Hz mode.
#define VMMODE_MZ1500 0x06 // Video mode = MZ1500
#define VMMODE_MZ80B 0x07 // Video mode = MZ80B
#define VMMODE_MZ2000 0x08 // Video mode = MZ2000
#define VMMODE_MZ2200 0x09 // Video mode = MZ2200
#define VMMODE_MZ2500 0x0A // Video mode = MZ2500
#define VMMODE_80CHAR 0x10 // Enable 80 character display.
#define VMMODE_80CHAR_MASK 0xEF // Mask to filter out display width control bit.
#define VMMODE_COLOUR 0x20 // Enable colour display.
#define VMMODE_COLOUR_MASK 0xDF // Mask to filter out colour control bit.
#define VMMODE_PCGRAM 0x40 // Enable PCG RAM.
#define VMMODE_VGA_MASK 0xF0 // Mask to filter out the VGA output mode bits.
#define VMMODE_VGA_OFF 0x00 // Set VGA mode off, external monitor is driven by standard internal 60Hz signals.
#define VMMODE_VGA_INT 0x00 // Set VGA mode off, external monitor is driven by standard internal 60Hz signals.
#define VMMODE_VGA_INT50 0x01 // Set VGA mode off, external monitor is driven by standard internal 50Hz signals.
#define VMMODE_VGA_640x480 0x02 // Set external monitor to VGA 640x480 @ 60Hz mode.
#define VMMODE_VGA_800x600 0x03 // Set external monitor to VGA 800x600 @ 60Hz mode.
// VGA mode border control constants.
//
@@ -464,12 +525,69 @@ enum COLOUR {
WHITE = 0x07 // Green, Red and Blue pixels active.
};
// Supported attriutes/
enum ATTRIBUTES {
NOATTR = 0x0000, // No attributes.
HILIGHT_FG_ACTIVE = 0x0008, // Highlight flag.
HILIGHT_FG_BLACK = 0x0008 + 0x00, // Highlight the character foreground in black.
HILIGHT_FG_BLUE = 0x0008 + 0x01, // Highlight "" "" "" "" blue.
HILIGHT_FG_RED = 0x0008 + 0x02, // Highlight "" "" "" "" red.
HILIGHT_FG_PURPLE = 0x0008 + 0x03, // Highlight "" "" "" "" purple.
HILIGHT_FG_GREEN = 0x0008 + 0x04, // Highlight "" "" "" "" green.
HILIGHT_FG_CYAN = 0x0008 + 0x05, // Highlight "" "" "" "" cyan.
HILIGHT_FG_YELLOW = 0x0008 + 0x06, // Highlight "" "" "" "" yellow.
HILIGHT_FG_WHITE = 0x0008 + 0x07, // Highlight "" "" "" "" white.
HILIGHT_BG_ACTIVE = 0x0010, // Highlight flag.
HILIGHT_BG_BLACK = 0x0010 + 0x00, // Highlight the character background in black.
HILIGHT_BG_BLUE = 0x0010 + 0x01, // Highlight "" "" "" "" blue.
HILIGHT_BG_RED = 0x0010 + 0x02, // Highlight "" "" "" "" red.
HILIGHT_BG_PURPLE = 0x0010 + 0x03, // Highlight "" "" "" "" purple.
HILIGHT_BG_GREEN = 0x0010 + 0x04, // Highlight "" "" "" "" green.
HILIGHT_BG_CYAN = 0x0010 + 0x05, // Highlight "" "" "" "" cyan.
HILIGHT_BG_YELLOW = 0x0010 + 0x06, // Highlight "" "" "" "" yellow.
HILIGHT_BG_WHITE = 0x0010 + 0x07 // Highlight "" "" "" "" white.
};
// Public settings, accessed via enumerated value.
enum OSDPARAMS {
ACTIVE_MAX_X = 0x00, // Width in pixels of the active framebuffer.
ACTIVE_MAX_Y = 0x01 // Depth in pixels of the active framebuffer.
};
// Structure to maintain data relevant to flashing a cursor at a given location.
//
typedef struct {
// Attributes to be used when cursor is showing.
uint16_t attr;
// Colour of the character,
enum COLOUR fg;
enum COLOUR bg;
// Location in the framebuffer where the character commences.
uint8_t row;
uint8_t col;
// Offset in pixels to the given row/col. Allows for finer placing within mixed fonts.
uint8_t ofrow;
uint8_t ofcol;
// Font used for the underlying character.
enum FONTS font;
// Flash speed of the cursor in ms.
unsigned long speed;
// Character being displayed.
uint8_t dispChar;
// Switch to enable/disable the cursor.
uint8_t enabled;
// Flash State.
uint8_t flashing;
} t_CursorFlash;
// Structure to maintain the OSD Menu and Status display output parameters and data.
//
typedef struct {
@@ -489,7 +607,11 @@ typedef struct {
uint16_t maxX; // Maximum X plane pixels.
uint16_t maxY; // Maximum Y plane pixels.
// Cursor data.
t_CursorFlash cursor; // Data for enabling a flashing cursor at a given screen coordinate.
} t_WindowParams;
// Structure to maintain the OSD window data.
typedef struct {
// Mode in which the OSD is operating.
enum WINDOWS mode;
@@ -517,10 +639,11 @@ bitmapStruct *OSDGetBitmap(enum BITMAPS);
void OSDSetPixel(uint16_t, uint16_t, enum COLOUR);
void OSDClearPixel(uint16_t, uint16_t, enum COLOUR);
void OSDChangePixelColour(uint16_t, uint16_t, enum COLOUR, enum COLOUR);
void _OSDwrite(uint8_t, uint8_t, int8_t, int8_t, uint8_t, uint8_t, enum ORIENTATION, uint8_t, enum COLOUR, enum COLOUR, fontStruct *);
void _OSDwrite(uint8_t, uint8_t, int8_t, int8_t, uint8_t, uint8_t, enum ORIENTATION, uint8_t, uint16_t, enum COLOUR, enum COLOUR, fontStruct *);
void OSDWriteBitmap(uint16_t, uint16_t, enum BITMAPS, enum COLOUR, enum COLOUR);
void OSDWriteChar(uint8_t, uint8_t, uint8_t, uint8_t, uint8_t, uint8_t, enum FONTS, enum ORIENTATION, char, enum COLOUR, enum COLOUR);
void OSDWriteString(uint8_t, uint8_t, int8_t, int8_t, uint8_t, uint8_t, enum FONTS, enum ORIENTATION, char *, enum COLOUR, enum COLOUR);
void OSDWriteString(uint8_t, uint8_t, int8_t, int8_t, uint8_t, uint8_t, enum FONTS, enum ORIENTATION, char *, uint16_t *, enum COLOUR, enum COLOUR);
void OSDUpdateScreenSize(void);
void OSDRefreshScreen(void);
void OSDClearScreen(enum COLOUR);
void OSDClearArea(int16_t, int16_t, int16_t, int16_t, enum COLOUR);
@@ -529,6 +652,10 @@ void OSDDrawCircle(int16_t, int16_t, int16_t, enum COLOUR);
void OSDDrawFilledCircle(int16_t, int16_t, int16_t, enum COLOUR);
void OSDDrawEllipse(int16_t, int16_t, int16_t, int16_t, enum COLOUR);
void OSDSetActiveWindow(enum WINDOWS);
void OSDSetCursorFlash(uint8_t, uint8_t, uint8_t, uint8_t, enum FONTS, uint8_t, enum COLOUR, enum COLOUR, uint16_t, unsigned long);
void OSDClearCursorFlash(void);
void OSDCursorFlash(void);
void OSDService(void);
uint8_t OSDInit(enum WINDOWS);
// Getter/Setter methods!

328
include/sharpmz.h
View File

@@ -98,69 +98,88 @@
// ------------------------
//
// Address A23 -A16
// Y+0x080000 00001000 - Memory and I/O ports mapped into direct addressable memory location.
// Y+0x000000 00001000 - Memory and I/O ports mapped into direct addressable memory location.
//
// A15 - A8 A7 - A0
// I/O registers are mapped to the bottom 256 bytes mirroring the I/O address.
// Y+0x0800D0 00000000 11010000 - 0xD0 - Set the parameter number to update.
// 00000000 11010001 - 0xD1 - Update the lower selected parameter byte.
// 00000000 11010010 - 0xD2 - Update the upper selected parameter byte.
// 00000000 11010011 - 0xD3 - set the palette slot Off position to be adjusted.
// 00000000 11010100 - 0xD4 - set the palette slot On position to be adjusted.
// 00000000 11010101 - 0xD5 - set the red palette value according to the PALETTE_PARAM_SEL address.
// 00000000 11010110 - 0xD6 - set the green palette value according to the PALETTE_PARAM_SEL address.
// Y+0x0800D7 00000000 11010111 - 0xD7 - set the blue palette value according to the PALETTE_PARAM_SEL address.
//
// Y+0x0800E0 00000000 11100000 - 0xE0 MZ80B PPI
// Y+0x0000A0 00000000 10100000 - 0xA0 -
// 00000000 10100001 - 0xA1 -
// 00000000 10100010 - 0xA2 -
// 00000000 10100011 - 0xA3 - set the palette slot Off position to be adjusted.
// 00000000 10100100 - 0xA4 - set the palette slot On position to be adjusted.
// 00000000 10100101 - 0xA5 - set the red palette value according to the PALETTE_PARAM_SEL address.
// 00000000 10100110 - 0xA6 - set the green palette value according to the PALETTE_PARAM_SEL address.
// Y+0x0000A7 00000000 10100111 - 0xA7 - set the blue palette value according to the PALETTE_PARAM_SEL address.
// 00000000 10101000 - 0xA8 - Get OSD Menu Horizontal Size (X).
// 00000000 10101001 - 0xA9 - Get OSD Menu Vertical Size (Y).
// 00000000 10101010 - 0xAA - Get OSD Status Header Horizontal Size (X).
// 00000000 10101011 - 0xAB - Get OSD Status Header Vertical Size (Y).
// 00000000 10101100 - 0xAC - Get OSD Status Footer Horizontal Size (X).
// 00000000 10101101 - 0xAD - Get OSD Status Footer Vertical Size (Y).
// Y+0x0000B0 00000000 10110000 - 0xB0 - sets the palette.
// 00000000 10110001 - 0xB1 -
// 00000000 10110010 - 0xB2 - set parameters.
// 00000000 10110011 - 0xB3 - set the graphics processor unit commands.
// 00000000 10111000 - 0xB8 - set the video mode.
// 00000000 10111001 - 0xB9 - set the graphics mode.
// 00000000 10111010 - 0xBA - set the Red bit mask
// 00000000 10111011 - 0xBB - set the Green bit mask
// 00000000 10111100 - 0xBC - set the Blue bit mask
// Y+0x0000BD 00000000 10111101 - 0xBD - set the Video memory page in block C000:FFFF
// Y+0x0000BE 00000000 10111110 - 0xBE - set the VGA border colour and attributes.
// Y+0x0000BF 00000000 10111111 - 0xBF - set the VGA output mode.
//
// Y+0x0000E0 00000000 11100000 - 0xE0 MZ80B PPI
// 00000000 11100100 - 0xE4 MZ80B PIT
// Y+0x0800E8 00000000 11101000 - 0xE8 MZ80B PIO
// Y+0x0000E8 00000000 11101000 - 0xE8 MZ80B PIO
//
// 00000000 11110000 -
// 00000000 11110001 -
// 00000000 11110010 -
// Y+0x0800F3 00000000 11110011 - 0xF3 set the VGA border colour.
// 00000000 11110100 - 0xF4 set the MZ80B video in/out mode.
// 00000000 11110101 - 0xF5 sets the palette.
// 00000000 11110110 - 0xF6 set parameters.
// 00000000 11110111 - 0xF7 set the graphics processor unit commands.
// 00000000 11111000 - 0xF6 set parameters.
// 00000000 11111001 - 0xF7 set the graphics processor unit commands.
// 00000000 11111010 - 0xF8 set the video mode.
// 00000000 11111011 - 0xF9 set the graphics mode.
// 00000000 11111100 - 0xFA set the Red bit mask
// 00000000 11111101 - 0xFB set the Green bit mask
// 00000000 11111110 - 0xFC set the Blue bit mask
// Y+0x0800FD 00000000 11111111 - 0xFD set the Video memory page in block C000:FFFF
// 00000000 11110000 - 0xF0
// 00000000 11110001 - 0xF1
// 00000000 11110010 - 0xF2
// Y+0x0000F3 00000000 11110011 - 0xF3
// 00000000 11110100 - 0xF4 set the MZ80B video in/out mode or MZ2000 Colour CRT Background Colour Selection.
// 00000000 11110101 - 0xF5 MZ2000 Priority, Bit 3 = 0, Character comes to foreground, = 1, Graphics comes to foreground. 2:0 = Colour
// 00000000 11110110 - 0xF6 MZ2000 Bit 4 Graphics Display on CRT (H), 2:0 colour VRAM enable to Colour CRT / CRT (if enabled).
// 00000000 11110111 - 0xF7 MZ2000 Selection of VRAM bank in memory map when enabled, 0 = None, 1 = Blue, 2 = Red, 3 = Green
//
// Memory registers are mapped to the E000 region as per base machines.
// Y+0x08E010 11100000 00010010 - Program Character Generator RAM. E010 - Write cycle (Read cycle = reset memory swap).
// Y+0x00E010 11100000 00010010 - Program Character Generator RAM. E010 - Write cycle (Read cycle = reset memory swap).
// 11100000 00010100 - Normal display select.
// 11100000 00010101 - Inverted display select.
// 11100010 00000000 - Scroll display register. E200 - E2FF
// Y+0x08E2FF 11111111
// Y+0x00E2FF 11111111
//
// Y+0x090000 00001001 - Video/Attribute RAM. 64K Window.
// Y+0x09D000 11010000 00000000 - Video RAM
// Y+0x09D7FF 11010111 11111111
// Y+0x09D800 11011000 00000000 - Attribute RAM
// Y+0x09DFFF 11011111 11111111
// Y+0x010000 00000001 - Video/Attribute RAM. 64K Window.
// Y+0x01D000 11010000 00000000 - Video RAM
// Y+0x01D7FF 11010111 11111111
// Y+0x01D800 11011000 00000000 - Attribute RAM
// Y+0x01DFFF 11011111 11111111
//
// Y+0x0A0000 00001010 - Character Generator RAM 64K Window.
// Y+0x0A0000 00000000 00000000 - CGROM
// Y+0x0A0FFF 00001111 11111111
// Y+0x0A1000 00010000 00000000 - CGRAM
// Y+0x0A1FFF 00011111 11111111
// Y+0x020000 00000010 - Character Generator RAM 64K Window.
// Y+0x020000 00000000 00000000 - CGROM
// Y+0x020FFF 00001111 11111111
// Y+0x021000 00010000 00000000 - CGRAM
// Y+0x021FFF 00011111 11111111
//
// Y+0x0C0000 00001100 - 128K Red framebuffer.
// Y+0x040000 00000100 - 128K Red framebuffer.
// 00000000 00000000 - Red pixel addressed framebuffer. Also MZ-80B GRAM I memory in lower 8K
// Y+0x0C3FFF 00111111 11111111
// Y+0x0D0000 00001101 - 128K Blue framebuffer.
// Y+0x043FFF 00111111 11111111
// Y+0x050000 00000101 - 128K Blue framebuffer.
// 00000000 00000000 - Blue pixel addressed framebuffer. Also MZ-80B GRAM II memory in lower 8K
// Y+0x0D3FFF 00111111 11111111
// Y+0x0E0000 00001110 - 128K Green framebuffer.
// Y+0x053FFF 00111111 11111111
// Y+0x060000 00000110 - 128K Green framebuffer.
// 00000000 00000000 - Green pixel addressed framebuffer.
// Y+0x0E3FFF 00111111 11111111
// Y+0x063FFF 00111111 11111111
//
// Y+0x070000 00000111 - Blue Menu/Status framebuffer.
// Y+0x071FFF 00011111 11111111
// Y+0x080000 00001000 - Red Menu/Status framebuffer.
// Y+0x081FFF 00011111 11111111
// Y+0x090000 00001001 - Green Menu/Status framebuffer.
// Y+0x091FFF 00011111 11111111
// Y+0x0A0000 00001010 - Red/Green/Blue Menu/Status framebuffer write only.
// Y+0x0A1FFF 00011111 11111111
// Base addresses and sizes within the FPGA/Video Controller.
#define VIDEO_BASE_ADDR 0xD00000 // Base address of the Video Controller.
@@ -176,31 +195,34 @@
#define VC_8BIT_BASE_ADDR VIDEO_BASE_ADDR + 0x000000
#define VC_32BIT_BASE_ADDR VIDEO_BASE_ADDR + 0x000000
// 8 Bit access addresses - used for writing, read can only be on a 32bit boundary with lower address lines set to 00. Writing can write upto 4 consecutive addresses if desired.
#define VCADDR_8BIT_PALSLCTOFF VC_8BIT_BASE_ADDR + 0xD3 // Set the palette slot Off position to be adjusted.
#define VCADDR_8BIT_PALSLCTON VC_8BIT_BASE_ADDR + 0xD4 // Set the palette slot On position to be adjusted.
#define VCADDR_8BIT_PALSETRED VC_8BIT_BASE_ADDR + 0xD5 // Set the red palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_8BIT_PALSETGREEN VC_8BIT_BASE_ADDR + 0xD6 // Set the green palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_8BIT_PALSETBLUE VC_8BIT_BASE_ADDR + 0xD7 // Set the blue palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_8BIT_SYSCTRL VC_8BIT_BASE_ADDR + 0xF0 // System board control register. [2:0] - 000 MZ80A Mode, 2MHz CPU/Bus, 001 MZ80B Mode, 4MHz CPU/Bus, 010 MZ700 Mode, 3.54MHz CPU/Bus.
#define VCADDR_8BIT_VMBORDER VC_8BIT_BASE_ADDR + 0xF3 // Select VGA Border colour attributes. Bit 2 = Red, 1 = Green, 0 = Blue.
#define VCADDR_8BIT_GRAMMODE VC_8BIT_BASE_ADDR + 0xF4 // MZ80B Graphics mode. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
#define VCADDR_8BIT_VMPALETTE VC_8BIT_BASE_ADDR + 0xF5 // Select Palette:
// 0xF5 sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output.
#define VCADDR_8BIT_PALSLCTOFF VC_8BIT_BASE_ADDR + 0xA3 // Set the palette slot Off position to be adjusted.
#define VCADDR_8BIT_PALSLCTON VC_8BIT_BASE_ADDR + 0xA4 // Set the palette slot On position to be adjusted.
#define VCADDR_8BIT_PALSETRED VC_8BIT_BASE_ADDR + 0xA5 // Set the red palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_8BIT_PALSETGREEN VC_8BIT_BASE_ADDR + 0xA6 // Set the green palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_8BIT_PALSETBLUE VC_8BIT_BASE_ADDR + 0xA7 // Set the blue palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_8BIT_OSDMNU_SZX VC_8BIT_BASE_ADDR + 0xA8 // Get OSD Menu Horizontal Size (X).
#define VCADDR_8BIT_OSDMNU_SZY VC_8BIT_BASE_ADDR + 0xA9 // Get OSD Menu Vertical Size (Y).
#define VCADDR_8BIT_OSDHDR_SZX VC_8BIT_BASE_ADDR + 0xAA // Get OSD Status Header Horizontal Size (X).
#define VCADDR_8BIT_OSDHDR_SZY VC_8BIT_BASE_ADDR + 0xAB // Get OSD Status Header Vertical Size (Y).
#define VCADDR_8BIT_OSDFTR_SZX VC_8BIT_BASE_ADDR + 0xAC // Get OSD Status Footer Horizontal Size (X).
#define VCADDR_8BIT_OSDFTR_SZY VC_8BIT_BASE_ADDR + 0xAD // Get OSD Status Footer Vertical Size (Y).
#define VCADDR_8BIT_VMPALETTE VC_8BIT_BASE_ADDR + 0xB0 // Sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output.
// Bits [7:0] defines the pallete number. This indexes a lookup table which contains the required 4bit output per 1bit input.
// GPU:
#define VCADDR_8BIT_GPUPARAM VC_8BIT_BASE_ADDR + 0xF6 // 0xF6 set parameters. Store parameters in a long word to be used by the graphics command processor.
#define VCADDR_8BIT_GPUPARAM VC_8BIT_BASE_ADDR + 0xB2 // Set parameters. Store parameters in a long word to be used by the graphics command processor.
// The parameter word is 128 bit and each write to the parameter word shifts left by 8 bits and adds the new byte at bits 7:0.
#define VCADDR_8BIT_GPUCMD VC_8BIT_BASE_ADDR + 0xF7 // 0xF7 set the graphics processor unit commands.
#define VCADDR_8BIT_GPUSTATUS VC_8BIT_BASE_ADDR + 0xF7 // [7;1] - FSM state, [0] - 1 = busy, 0 = idle
#define VCADDR_8BIT_GPUCMD VC_8BIT_BASE_ADDR + 0xB3 // Set the graphics processor unit commands.
// Bits [5:0] - 0 = Reset parameters.
// 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter
//
#define VCADDR_8BIT_VMCTRL VC_8BIT_BASE_ADDR + 0xF8 // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define VCADDR_8BIT_VMGRMODE VC_8BIT_BASE_ADDR + 0xF9 // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define VCADDR_8BIT_VMREDMASK VC_8BIT_BASE_ADDR + 0xFA // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_8BIT_VMGREENMASK VC_8BIT_BASE_ADDR + 0xFB // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_8BIT_VMBLUEMASK VC_8BIT_BASE_ADDR + 0xFC // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_8BIT_VMPAGE VC_8BIT_BASE_ADDR + 0xFD // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
#define VCADDR_8BIT_VMCTRL VC_8BIT_BASE_ADDR + 0xB8 // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define VCADDR_8BIT_VMGRMODE VC_8BIT_BASE_ADDR + 0xB9 // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define VCADDR_8BIT_VMREDMASK VC_8BIT_BASE_ADDR + 0xBA // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_8BIT_VMGREENMASK VC_8BIT_BASE_ADDR + 0xBB // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_8BIT_VMBLUEMASK VC_8BIT_BASE_ADDR + 0xBC // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_8BIT_VMPAGE VC_8BIT_BASE_ADDR + 0xBD // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
#define VCADDR_8BIT_VMVGATTR VC_8BIT_BASE_ADDR + 0xBE // Select VGA Border colour and attributes. Bit 2 = Red, 1 = Green, 0 = Blue, 4:3 = VGA Mode, 00 = Off, 01 = 640x480, 10 = 800x600, 11 = 50Hz Internal
#define VCADDR_8BIT_VMVGAMODE VC_8BIT_BASE_ADDR + 0xBF // Select VGA Output mode. [3:0] - required output resolution/frequency.
#define VCADDR_8BIT_SYSCTRL VC_8BIT_BASE_ADDR + 0xF0 // System board control register. [2:0] - 000 MZ80A Mode, 2MHz CPU/Bus, 001 MZ80B Mode, 4MHz CPU/Bus, 010 MZ700 Mode, 3.54MHz CPU/Bus.
#define VCADDR_8BIT_GRAMMODE VC_8BIT_BASE_ADDR + 0xF4 // MZ80B Graphics mode. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
#define VCADDR_8BIT_KEYPA VC_8BIT_BASE_ADDR + 0xE000 // VideoModule 8255 Port A
#define VCADDR_8BIT_KEYPB VC_8BIT_BASE_ADDR + 0xE001 // VideoModule 8255 Port B
#define VCADDR_8BIT_KEYPC VC_8BIT_BASE_ADDR + 0xE002 // VideoModule 8255 Port C
@@ -221,32 +243,34 @@
#define VCADDR_8BIT_SCLBASE VC_8BIT_BASE_ADDR + 0xE2 // High byte scroll base.
// 32 Bit access addresses for 8bit registers - used for reading, address is shifted right by 2 and the resulting byte read into bits 7:0, 31:8 are zero.
#define VCADDR_32BIT_PALSLCTOFF VC_32BIT_BASE_ADDR + (4*0xD3) // Set the palette slot Off position to be adjusted.
#define VCADDR_32BIT_PALSLCTON VC_32BIT_BASE_ADDR + (4*0xD4) // Set the palette slot On position to be adjusted.
#define VCADDR_32BIT_PALSETRED VC_32BIT_BASE_ADDR + (4*0xD5) // Set the red palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_32BIT_PALSETGREEN VC_32BIT_BASE_ADDR + (4*0xD6) // Set the green palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_32BIT_PALSETBLUE VC_32BIT_BASE_ADDR + (4*0xD7) // Set the blue palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_32BIT_SYSCTRL VC_32BIT_BASE_ADDR + (4*0xF0) // System board control register. [2:0] - 000 MZ80A Mode, 2MHz CPU/Bus, 001 MZ80B Mode, 4MHz CPU/Bus, 010 MZ700 Mode, 3.54MHz CPU/Bus.
#define VCADDR_32BIT_VMBORDER VC_32BIT_BASE_ADDR + (4*0xF3) // Select VGA Border colour attributes. Bit 2 = Red, 1 = Green, 0 = Blue.
#define VCADDR_32BIT_GRAMMODE VC_32BIT_BASE_ADDR + (4*0xF4) // MZ80B Graphics mode. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
#define VCADDR_32BIT_VMPALETTE VC_32BIT_BASE_ADDR + (4*0xF5) // Select Palette:
// 0xF5 sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output.
#define VCADDR_32BIT_PALSLCTOFF VC_32BIT_BASE_ADDR + (4*0xA3) // Set the palette slot Off position to be adjusted.
#define VCADDR_32BIT_PALSLCTON VC_32BIT_BASE_ADDR + (4*0xA4) // Set the palette slot On position to be adjusted.
#define VCADDR_32BIT_PALSETRED VC_32BIT_BASE_ADDR + (4*0xA5) // Set the red palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_32BIT_PALSETGREEN VC_32BIT_BASE_ADDR + (4*0xA6) // Set the green palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_32BIT_PALSETBLUE VC_32BIT_BASE_ADDR + (4*0xA7) // Set the blue palette value according to the PALETTE_PARAM_SEL address.
#define VCADDR_32BIT_OSDMNU_SZX VC_32BIT_BASE_ADDR + (4*0xA8) // Get OSD Menu Horizontal Size (X).
#define VCADDR_32BIT_OSDMNU_SZY VC_32BIT_BASE_ADDR + (4*0xA9) // Get OSD Menu Vertical Size (Y).
#define VCADDR_32BIT_OSDHDR_SZX VC_32BIT_BASE_ADDR + (4*0xAA) // Get OSD Status Header Horizontal Size (X).
#define VCADDR_32BIT_OSDHDR_SZY VC_32BIT_BASE_ADDR + (4*0xAB) // Get OSD Status Header Vertical Size (Y).
#define VCADDR_32BIT_OSDFTR_SZX VC_32BIT_BASE_ADDR + (4*0xAC) // Get OSD Status Footer Horizontal Size (X).
#define VCADDR_32BIT_OSDFTR_SZY VC_32BIT_BASE_ADDR + (4*0xAD) // Get OSD Status Footer Vertical Size (Y).
#define VCADDR_32BIT_VMPALETTE VC_32BIT_BASE_ADDR + (4*0xB0) // Sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output.
// Bits [7:0] defines the pallete number. This indexes a lookup table which contains the required 4bit output per 1bit input.
// GPU:
#define VCADDR_32BIT_GPUPARAM VC_32BIT_BASE_ADDR + (4*0xF6) // 0xF6 set parameters. Store parameters in a long word to be used by the graphics command processor.
#define VCADDR_32BIT_GPUPARAM VC_32BIT_BASE_ADDR + (4*0xB2) // Set parameters. Store parameters in a long word to be used by the graphics command processor.
// The parameter word is 128 bit and each write to the parameter word shifts left by 8 bits and adds the new byte at bits 7:0.
#define VCADDR_32BIT_GPUCMD VC_32BIT_BASE_ADDR + (4*0xF7) // 0xF7 set the graphics processor unit commands.
#define VCADDR_32BIT_GPUSTATUS VC_32BIT_BASE_ADDR + (4*0xF7) // [7;1] - FSM state, [0] - 1 = busy, 0 = idle
#define VCADDR_32BIT_GPUCMD VC_32BIT_BASE_ADDR + (4*0xB3) // Set the graphics processor unit commands.
// Bits [5:0] - 0 = Reset parameters.
// 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter
//
#define VCADDR_32BIT_VMCTRL VC_32BIT_BASE_ADDR + (4*0xF8) // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
// [4] defines the colour mode, 0 = mono, 1 = colour - ignored on certain modes. [5] defines wether PCGRAM is enabled, 0 = disabled, 1 = enabled. [7:6] define the VGA mode.
#define VCADDR_32BIT_VMGRMODE VC_32BIT_BASE_ADDR + (4*0xF9) // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define VCADDR_32BIT_VMREDMASK VC_32BIT_BASE_ADDR + (4*0xFA) // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_32BIT_VMGREENMASK VC_32BIT_BASE_ADDR + (4*0xFB) // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_32BIT_VMBLUEMASK VC_32BIT_BASE_ADDR + (4*0xFC) // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_32BIT_VMPAGE VC_32BIT_BASE_ADDR + (4*0xFD) // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
#define VCADDR_32BIT_VMCTRL VC_32BIT_BASE_ADDR + (4*0xB8) // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define VCADDR_32BIT_VMGRMODE VC_32BIT_BASE_ADDR + (4*0xB9) // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define VCADDR_32BIT_VMREDMASK VC_32BIT_BASE_ADDR + (4*0xBA) // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_32BIT_VMGREENMASK VC_32BIT_BASE_ADDR + (4*0xBB) // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_32BIT_VMBLUEMASK VC_32BIT_BASE_ADDR + (4*0xBC) // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define VCADDR_32BIT_VMPAGE VC_32BIT_BASE_ADDR + (4*0xBD) // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
#define VCADDR_32BIT_VMVGATTR VC_32BIT_BASE_ADDR + (4*0xBE) // Select VGA Border colour and attributes. Bit 2 = Red, 1 = Green, 0 = Blue, 4:3 = VGA Mode, 00 = Off, 01 = 640x480, 10 = 800x600, 11 = 50Hz Internal
#define VCADDR_32BIT_VMVGAMODE VC_32BIT_BASE_ADDR + (4*0xBF) // Select VGA Output mode. [3:0] - required output resolution/frequency.
#define VCADDR_32BIT_SYSCTRL VC_32BIT_BASE_ADDR + (4*0xF0) // System board control register. [2:0] - 000 MZ80A Mode, 2MHz CPU/Bus, 001 MZ80B Mode, 4MHz CPU/Bus, 010 MZ700 Mode, 3.54MHz CPU/Bus.
#define VCADDR_32BIT_GRAMMODE VC_32BIT_BASE_ADDR + (4*0xF4) // MZ80B Graphics mode. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
#define VCADDR_32BIT_KEYPA VC_32BIT_BASE_ADDR + (4*0xE000) // Video Module 8255 Port A
#define VCADDR_32BIT_KEYPB VC_32BIT_BASE_ADDR + (4*0xE001) // Video Module 8255 Port B
#define VCADDR_32BIT_KEYPC VC_32BIT_BASE_ADDR + (4*0xE002) // Video Module 8255 Port C
@@ -325,14 +349,24 @@
#define MBADDR_8BIT_IOW_CPLDCFG MB_32BIT_IO_ADDR + 0x6E // Version 2.1 CPLD configuration register.
#define MBADDR_8BIT_IOW_CPLDSTATUS MB_32BIT_IO_ADDR + 0x6E // Version 2.1 CPLD status register.
#define MBADDR_8BIT_IOW_CPLDINFO MB_32BIT_IO_ADDR + 0x6F // Version 2.1 CPLD version information register.
#define MBADDR_8BIT_IOW_VMPALETTE VC_32BIT_IO_ADDR + 0xB0 // Sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output.
// Bits [7:0] defines the pallete number. This indexes a lookup table which contains the required 4bit output per 1bit input.
#define MBADDR_8BIT_IOW_GPUPARAM VC_32BIT_IO_ADDR + 0xB2 // Set parameters. Store parameters in a long word to be used by the graphics command processor.
// The parameter word is 128 bit and each write to the parameter word shifts left by 8 bits and adds the new byte at bits 7:0.
#define MBADDR_8BIT_IOW_GPUCMD VC_32BIT_IO_ADDR + 0xB3 // Set the graphics processor unit commands.
// Bits [5:0] - 0 = Reset parameters.
// 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter
#define MBADDR_8BIT_IOW_VMCTRL MB_32BIT_IO_ADDR + 0xB8 // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define MBADDR_8BIT_IOW_VMGRMODE MB_32BIT_IO_ADDR + 0xB9 // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define MBADDR_8BIT_IOW_VMREDMASK MB_32BIT_IO_ADDR + 0xBA // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define MBADDR_8BIT_IOW_VMGREENMASK MB_32BIT_IO_ADDR + 0xBB // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define MBADDR_8BIT_IOW_VMBLUEMASK MB_32BIT_IO_ADDR + 0xBC // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define MBADDR_8BIT_IOW_VMPAGE MB_32BIT_IO_ADDR + 0xBD // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
#define MBADDR_8BIT_IOW_VMVGATTR MB_32BIT_IO_ADDR + 0xBE // Select VGA Border colour and attributes. Bit 2 = Red, 1 = Green, 0 = Blue, 4:3 = VGA Mode, 00 = Off, 01 = 640x480, 10 = 800x600, 11 = 50Hz Internal
#define MBADDR_8BIT_IOW_VMVGAMODE MB_32BIT_IO_ADDR + 0xBF // Select VGA Output mode. [3:0] - required output resolution/frequency.
#define MBADDR_8BIT_IOW_SYSCTRL MB_32BIT_IO_ADDR + 0xF0 // System board control register. [2:0] - 000 MZ80A Mode, 2MHz CPU/Bus, 001 MZ80B Mode, 4MHz CPU/Bus, 010 MZ700 Mode, 3.54MHz CPU/Bus.
#define MBADDR_8BIT_IOW_GRAMMODE MB_32BIT_IO_ADDR + 0xF4 // MZ80B Graphics mode. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
#define MBADDR_8BIT_IOW_VMCTRL MB_32BIT_IO_ADDR + 0xF8 // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define MBADDR_8BIT_IOW_VMGRMODE MB_32BIT_IO_ADDR + 0xF9 // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define MBADDR_8BIT_IOW_VMREDMASK MB_32BIT_IO_ADDR + 0xFA // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define MBADDR_8BIT_IOW_VMGREENMASK MB_32BIT_IO_ADDR + 0xFB // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define MBADDR_8BIT_IOW_VMBLUEMASK MB_32BIT_IO_ADDR + 0xFC // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define MBADDR_8BIT_IOW_VMPAGE MB_32BIT_IO_ADDR + 0xFD // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
#define MBADDR_32BIT_IOR_CTRLLATCH MB_32BIT_IO_ADDR + (4*0x60) // Control latch which specifies the Memory Model/mode.
#define MBADDR_32BIT_IOR_SETXMHZ MB_32BIT_IO_ADDR + (4*0x62) // Switch to alternate CPU frequency provided by K64F.
@@ -346,17 +380,14 @@
#define MBADDR_32BIT_IOR_CPLDCFG MB_32BIT_IO_ADDR + (4*0x6E) // Version 2.1 CPLD configuration register.
#define MBADDR_32BIT_IOR_CPLDSTATUS MB_32BIT_IO_ADDR + (4*0x6E) // Version 2.1 CPLD status register.
#define MBADDR_32BIT_IOR_CPLDINFO MB_32BIT_IO_ADDR + (4*0x6F) // Version 2.1 CPLD version information register.
#define MBADDR_32BIT_IOR_VMCTRL MB_32BIT_IO_ADDR + (4*0xB8) // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define MBADDR_32BIT_IOR_VMGRMODE MB_32BIT_IO_ADDR + (4*0xB9) // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define MBADDR_32BIT_IOR_VMREDMASK MB_32BIT_IO_ADDR + (4*0xBA) // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define MBADDR_32BIT_IOR_VMGREENMASK MB_32BIT_IO_ADDR + (4*0xBB) // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define MBADDR_32BIT_IOR_VMBLUEMASK MB_32BIT_IO_ADDR + (4*0xBC) // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define MBADDR_32BIT_IOR_VMPAGE MB_32BIT_IO_ADDR + (4*0xBD) // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
#define MBADDR_32BIT_IOR_SYSCTRL MB_32BIT_IO_ADDR + (4*0xF0) // System board control register. [2:0] - 000 MZ80A Mode, 2MHz CPU/Bus, 001 MZ80B Mode, 4MHz CPU/Bus, 010 MZ700 Mode, 3.54MHz CPU/Bus.
#define MBADDR_32BIT_IOR_GRAMMODE MB_32BIT_IO_ADDR + (4*0xF4) // MZ80B Graphics mode. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
#define MBADDR_32BIT_IOR_VMCTRL MB_32BIT_IO_ADDR + (4*0xF8) // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define MBADDR_32BIT_IOR_VMGRMODE MB_32BIT_IO_ADDR + (4*0xF9) // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define MBADDR_32BIT_IOR_VMREDMASK MB_32BIT_IO_ADDR + (4*0xFA) // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define MBADDR_32BIT_IOR_VMGREENMASK MB_32BIT_IO_ADDR + (4*0xFB) // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define MBADDR_32BIT_IOR_VMBLUEMASK MB_32BIT_IO_ADDR + (4*0xFC) // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define MBADDR_32BIT_IOR_VMPAGE MB_32BIT_IO_ADDR + (4*0xFD) // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
// tranZPUter Memory Modes - select one of the 32 possible memory models using these constants.
//
@@ -392,20 +423,69 @@
#define IO_TZ_CLKSELRD 0x66 // Read the status of the clock select, ie. which clock is connected to the CPU.
#define IO_TZ_SVCREQ 0x68 // Service request from the Z80 to be provided by the K64F.
#define IO_TZ_SYSREQ 0x6A // System request from the Z80 to be provided by the K64F.
#define IO_TZ_CPLDSTATUS 0x6B // Version 2.1 CPLD status register.
#define IO_TZ_CPUCFG 0x6C // Version 2.2 CPU configuration register.
#define IO_TZ_CPUSTATUS 0x6C // Version 2.2 CPU runtime status register.
#define IO_TZ_CPUINFO 0x6D // Version 2.2 CPU information register.
#define IO_TZ_CPLDCFG 0x6E // Version 2.1 CPLD configuration register.
#define IO_TZ_CPLDSTATUS 0x6E // Version 2.1 CPLD status register.
#define IO_TZ_CPLDINFO 0x6F // Version 2.1 CPLD version information register.
#define IO_TZ_PALSLCTOFF 0xA3 // Set the palette slot (PALETTE_PARAM_SEL) Off position to be adjusted.
#define IO_TZ_PALSLCTON 0xA4 // Set the palette slot (PALETTE_PARAM_SEL) On position to be adjusted.
#define IO_TZ_PALSETRED 0xA5 // Set the red palette value according to the PALETTE_PARAM_SEL address.
#define IO_TZ_PALSETGREEN 0xA6 // Set the green palette value according to the PALETTE_PARAM_SEL address.
#define IO_TZ_PALSETBLUE 0xA7 // Set the blue palette value according to the PALETTE_PARAM_SEL address.
#define IO_TZ_OSDMNU_SZX 0xA8 // Get OSD Menu Horizontal Size (X).
#define IO_TZ_OSDMNU_SZY 0xA9 // Get OSD Menu Vertical Size (Y).
#define IO_TZ_OSDHDR_SZX 0xAA // Get OSD Status Header Horizontal Size (X).
#define IO_TZ_OSDHDR_SZY 0xAB // Get OSD Status Header Vertical Size (Y).
#define IO_TZ_OSDFTR_SZX 0xAC // Get OSD Status Footer Horizontal Size (X).
#define IO_TZ_OSDFTR_SZY 0xAD // Get OSD Status Footer Vertical Size (Y).
#define IO_TZ_PALETTE 0xB0 // Sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output.
// Bits [7:0] defines the pallete number. This indexes a lookup table which contains the required 4bit output per 1bit input.
#define IO_TZ_GPUPARAM 0xB2 // Set parameters. Store parameters in a long word to be used by the graphics command processor.
// The parameter word is 128 bit and each write to the parameter word shifts left by 8 bits and adds the new byte at bits 7:0.
#define IO_TZ_GPUCMD 0xB3 // Set the graphics processor unit commands.
// Bits [5:0] - 0 = Reset parameters.
// 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter
#define IO_TZ_VMCTRL 0xB8 // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define IO_TZ_VMGRMODE 0xB9 // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define IO_TZ_VMREDMASK 0xBA // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMGREENMASK 0xBB // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMBLUEMASK 0xBC // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMPAGE 0xBD // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
#define IO_TZ_VMVGATTR 0xBE // Select VGA Border colour and attributes. Bit 2 = Red, 1 = Green, 0 = Blue, 4:3 = VGA Mode, 00 = Off, 01 = 640x480, 10 = 800x600, 11 = 50Hz Internal
#define IO_TZ_VMVGAMODE 0xBF // Select VGA Output mode. [3:0] - required output resolution/frequency.
#define IO_TZ_GDGWF 0xCC // MZ-800 write format register
#define IO_TZ_GDGRF 0xCD // MZ-800 read format register
#define IO_TZ_GDCMD 0xCE // MZ-800 CRTC Mode register
#define IO_TZ_GDCMD 0xCF // MZ-800 CRTC control register
#define IO_TZ_MMIO0 0xE0 // MZ-700/MZ-800 Memory management selection ports.
#define IO_TZ_MMIO1 0xE1 // ""
#define IO_TZ_MMIO2 0xE2 // ""
#define IO_TZ_MMIO3 0xE3 // ""
#define IO_TZ_MMIO4 0xE4 // ""
#define IO_TZ_MMIO5 0xE5 // ""
#define IO_TZ_MMIO6 0xE6 // ""
#define IO_TZ_MMIO7 0xE7 // MZ-700/MZ-800 Memory management selection ports.
#define IO_TZ_PPIA 0xE0 // MZ80B/MZ2000 8255 PPI Port A
#define IO_TZ_PPIB 0xE1 // MZ80B/MZ2000 8255 PPI Port B
#define IO_TZ_PPIC 0xE2 // MZ80B/MZ2000 8255 PPI Port C
#define IO_TZ_PPICTL 0xE3 // MZ80B/MZ2000 8255 PPI Control Register
#define IO_TZ_PIT0 0xE4 // MZ80B/MZ2000 8253 PIT Timer 0
#define IO_TZ_PIT1 0xE5 // MZ80B/MZ2000 8253 PIT Timer 1
#define IO_TZ_PIT2 0xE6 // MZ80B/MZ2000 8253 PIT Timer 2
#define IO_TZ_PITCTL 0xE7 // MZ80B/MZ2000 8253 PIT Control Register
#define IO_TZ_PIOA 0xE8 // MZ80B/MZ2000 Z80 PIO Port A
#define IO_TZ_PIOCTLA 0xE9 // MZ80B/MZ2000 Z80 PIO Port A Control Register
#define IO_TZ_PIOB 0xEA // MZ80B/MZ2000 Z80 PIO Port B
#define IO_TZ_PIOCTLB 0xEB // MZ80B/MZ2000 Z80 PIO Port B Control Register
#define IO_TZ_SYSCTRL 0xF0 // System board control register. [2:0] - 000 MZ80A Mode, 2MHz CPU/Bus, 001 MZ80B Mode, 4MHz CPU/Bus, 010 MZ700 Mode, 3.54MHz CPU/Bus.
#define IO_TZ_GRAMMODE 0xF4 // MZ80B Graphics mode. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
#define IO_TZ_VMCTRL 0xF8 // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define IO_TZ_VMGRMODE 0xF9 // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define IO_TZ_VMREDMASK 0xFA // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMGREENMASK 0xFB // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMBLUEMASK 0xFC // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMPAGE 0xFD // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
//#define IO_TZ_GRAMOPT 0xF4 // MZ80B/MZ2000 GRAM configuration option.
#define IO_TZ_CRTGRPHPRIO 0xF5 // MZ2000 Graphics priority register, character or a graphics colour has front display priority.
#define IO_TZ_CRTGRPHSEL 0xF6 // MZ2000 Graphics output select on CRT or external CRT
#define IO_TZ_GRAMCOLRSEL 0xF7 // MZ2000 Graphics RAM colour bank select./
// IO register constants.
//
@@ -438,18 +518,22 @@
#define VMMODE_MZ80A 0x03 // Video mode = MZ80A
#define VMMODE_MZ700 0x04 // Video mode = MZ700
#define VMMODE_MZ800 0x05 // Video mode = MZ800
#define VMMODE_MZ80B 0x06 // Video mode = MZ80B
#define VMMODE_MZ2000 0x07 // Video mode = MZ2000
#define VMMODE_80CHAR 0x08 // Enable 80 character display.
#define VMMODE_80CHAR_MASK 0xF7 // Mask to filter out display width control bit.
#define VMMODE_COLOUR 0x10 // Enable colour display.
#define VMMODE_COLOUR_MASK 0xEF // Mask to filter out colour control bit.
#define VMMODE_PCGRAM 0x20 // Enable PCG RAM.
#define VMMODE_VGA_MASK 0x3F // Mask to filter out the VGA mode bits.
#define VMMODE_VGA_OFF 0x00 // Set VGA mode off, external monitor is driven by standard internal signals.
#define VMMODE_VGA_640x480 0x40 // Set external monitor to VGA 640x480 @ 60Hz mode.
#define VMMODE_VGA_1024x768 0x80 // Set external monitor to VGA 1024x768 @ 60Hz mode.
#define VMMODE_VGA_800x600 0xC0 // Set external monitor to VGA 800x600 @ 60Hz mode.
#define VMMODE_MZ1500 0x06 // Video mode = MZ1500
#define VMMODE_MZ80B 0x07 // Video mode = MZ80B
#define VMMODE_MZ2000 0x08 // Video mode = MZ2000
#define VMMODE_MZ2200 0x09 // Video mode = MZ2200
#define VMMODE_MZ2500 0x0A // Video mode = MZ2500
#define VMMODE_80CHAR 0x10 // Enable 80 character display.
#define VMMODE_80CHAR_MASK 0xEF // Mask to filter out display width control bit.
#define VMMODE_COLOUR 0x20 // Enable colour display.
#define VMMODE_COLOUR_MASK 0xDF // Mask to filter out colour control bit.
#define VMMODE_PCGRAM 0x40 // Enable PCG RAM.
#define VMMODE_VGA_MASK 0xF0 // Mask to filter out the VGA output mode bits.
#define VMMODE_VGA_OFF 0x00 // Set VGA mode off, external monitor is driven by standard internal 60Hz signals.
#define VMMODE_VGA_INT 0x00 // Set VGA mode off, external monitor is driven by standard internal 60Hz signals.
#define VMMODE_VGA_INT50 0x01 // Set VGA mode off, external monitor is driven by standard internal 50Hz signals.
#define VMMODE_VGA_640x480 0x02 // Set external monitor to VGA 640x480 @ 60Hz mode.
#define VMMODE_VGA_800x600 0x03 // Set external monitor to VGA 800x600 @ 60Hz mode.
// VGA mode border control constants.
//

206
include/tranzputer.h
View File

@@ -66,6 +66,7 @@
#define TZMM_MZ700_3 0x0d // MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 0, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
#define TZMM_MZ700_4 0x0e // MZ700 Mode - 0000:0FFF is on the tranZPUter board in block 6, 1000:CFFF is on the tranZPUter board in block 0, D000:FFFF is inaccessible.
#define TZMM_MZ800 0x0f // MZ800 Mode - Host is an MZ-800 and mode provides for MZ-700/MZ-800 decoding per original machine.
#define TZMM_MZ2000 0x10 // MZ2000 Mode - Running on MZ2000 hardware, configuration set according to runtime configuration registers.
#define TZMM_FPGA 0x15 // Open up access for the K64F to the FPGA resources such as memory. All other access to RAM or mainboard is blocked.
#define TZMM_TZPUM 0x16 // Everything is on mainboard, no access to tranZPUter memory.
#define TZMM_TZPU 0x17 // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory. K64F drives A18-A16 allowing full access to RAM.
@@ -86,12 +87,43 @@
#define IO_TZ_CLKSELRD 0x66 // Read the status of the clock select, ie. which clock is connected to the CPU.
#define IO_TZ_SVCREQ 0x68 // Service request from the Z80 to be provided by the K64F.
#define IO_TZ_SYSREQ 0x6A // System request from the Z80 to be provided by the K64F.
#define IO_TZ_CPLDCMD 0x6B // Version 2.1 CPLD command register.
#define IO_TZ_CPLDSTATUS 0x6B // Version 2.1 CPLD status register.
#define IO_TZ_CPUCFG 0x6C // Version 2.2 CPU configuration register.
#define IO_TZ_CPUSTATUS 0x6C // Version 2.2 CPU runtime status register.
#define IO_TZ_CPUINFO 0x6D // Version 2.2 CPU information register.
#define IO_TZ_CPLDCFG 0x6E // Version 2.1 CPLD configuration register.
#define IO_TZ_CPLDSTATUS 0x6E // Version 2.1 CPLD status register.
#define IO_TZ_CPLDINFO 0x6F // Version 2.1 CPLD version information register.
#define IO_TZ_PALSLCTOFF 0xA3 // set the palette slot Off position to be adjusted.
#define IO_TZ_PALSLCTON 0xA4 // set the palette slot On position to be adjusted.
#define IO_TZ_PALSETRED 0xA5 // set the red palette value according to the PALETTE_PARAM_SEL address.
#define IO_TZ_PALSETGREEN 0xA6 // set the green palette value according to the PALETTE_PARAM_SEL address.
#define IO_TZ_PALSETBLUE 0xA7 // set the blue palette value according to the PALETTE_PARAM_SEL address.
#define IO_TZ_OSDMNU_SZX 0xA8 // Get OSD Menu Horizontal Size (X).
#define IO_TZ_OSDMNU_SZY 0xA9 // Get OSD Menu Vertical Size (Y).
#define IO_TZ_OSDHDR_SZX 0xAA // Get OSD Status Header Horizontal Size (X).
#define IO_TZ_OSDHDR_SZY 0xAB // Get OSD Status Header Vertical Size (Y).
#define IO_TZ_OSDFTR_SZX 0xAC // Get OSD Status Footer Horizontal Size (X).
#define IO_TZ_OSDFTR_SZY 0xAD // Get OSD Status Footer Vertical Size (Y).
#define IO_TZ_PALETTE 0xB0 // Sets the palette. The Video Module supports 4 bit per colour output but there is only enough RAM for 1 bit per colour so the pallette is used to change the colours output.
// Bits [7:0] defines the pallete number. This indexes a lookup table which contains the required 4bit output per 1bit input.
#define IO_TZ_GPUPARAM 0xB2 // Set parameters. Store parameters in a long word to be used by the graphics command processor.
// The parameter word is 128 bit and each write to the parameter word shifts left by 8 bits and adds the new byte at bits 7:0.
#define IO_TZ_GPUCMD 0xB3 // Set the graphics processor unit commands.
// Bits [5:0] - 0 = Reset parameters.
// 1 = Clear to val. Start Location (16 bit), End Location (16 bit), Red Filter, Green Filter, Blue Filter
#define IO_TZ_VMCTRL 0xB8 // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define IO_TZ_VMGRMODE 0xB9 // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define IO_TZ_VMREDMASK 0xBA // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMGREENMASK 0xBB // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMBLUEMASK 0xBC // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMPAGE 0xBD // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
#define IO_TZ_VMVGATTR 0xBE // Select VGA Border colour and attributes. Bit 2 = Red, 1 = Green, 0 = Blue, 4:3 = VGA Mode, 00 = Off, 01 = 640x480, 10 = 800x600, 11 = 50Hz Internal
#define IO_TZ_VMVGAMODE 0xBF // Select VGA Output mode, ie. Internal, 640x480 etc. Bits [3:0] specify required mode. Undefined default to internal standard frequency.
#define IO_TZ_GDGWF 0xCC // MZ-800 write format register
#define IO_TZ_GDGRF 0xCD // MZ-800 read format register
#define IO_TZ_GDCMD 0xCE // MZ-800 CRTC Mode register
#define IO_TZ_GDCMD 0xCF // MZ-800 CRTC control register
#define IO_TZ_MMIO0 0xE0 // MZ-700/MZ-800 Memory management selection ports.
#define IO_TZ_MMIO1 0xE1 // ""
#define IO_TZ_MMIO2 0xE2 // ""
@@ -100,14 +132,24 @@
#define IO_TZ_MMIO5 0xE5 // ""
#define IO_TZ_MMIO6 0xE6 // ""
#define IO_TZ_MMIO7 0xE7 // MZ-700/MZ-800 Memory management selection ports.
#define IO_TZ_PPIA 0xE0 // MZ80B/MZ2000 8255 PPI Port A
#define IO_TZ_PPIB 0xE1 // MZ80B/MZ2000 8255 PPI Port B
#define IO_TZ_PPIC 0xE2 // MZ80B/MZ2000 8255 PPI Port C
#define IO_TZ_PPICTL 0xE3 // MZ80B/MZ2000 8255 PPI Control Register
#define IO_TZ_PIT0 0xE4 // MZ80B/MZ2000 8253 PIT Timer 0
#define IO_TZ_PIT1 0xE5 // MZ80B/MZ2000 8253 PIT Timer 1
#define IO_TZ_PIT2 0xE6 // MZ80B/MZ2000 8253 PIT Timer 2
#define IO_TZ_PITCTL 0xE7 // MZ80B/MZ2000 8253 PIT Control Register
#define IO_TZ_PIOA 0xE8 // MZ80B/MZ2000 Z80 PIO Port A
#define IO_TZ_PIOCTLA 0xE9 // MZ80B/MZ2000 Z80 PIO Port A Control Register
#define IO_TZ_PIOB 0xEA // MZ80B/MZ2000 Z80 PIO Port B
#define IO_TZ_PIOCTLB 0xEB // MZ80B/MZ2000 Z80 PIO Port B Control Register
#define IO_TZ_SYSCTRL 0xF0 // System board control register. [2:0] - 000 MZ80A Mode, 2MHz CPU/Bus, 001 MZ80B Mode, 4MHz CPU/Bus, 010 MZ700 Mode, 3.54MHz CPU/Bus.
#define IO_TZ_GRAMMODE 0xF4 // MZ80B Graphics mode. Bit 0 = 0, Write to Graphics RAM I, Bit 0 = 1, Write to Graphics RAM II. Bit 1 = 1, blend Graphics RAM I output on display, Bit 2 = 1, blend Graphics RAM II output on display.
#define IO_TZ_VMCTRL 0xF8 // Video Module control register. [2:0] - 000 (default) = MZ80A, 001 = MZ-700, 010 = MZ800, 011 = MZ80B, 100 = MZ80K, 101 = MZ80C, 110 = MZ1200, 111 = MZ2000. [3] = 0 - 40 col, 1 - 80 col.
#define IO_TZ_VMGRMODE 0xF9 // Video Module graphics mode. 7/6 = Operator (00=OR,01=AND,10=NAND,11=XOR), 5=GRAM Output Enable, 4 = VRAM Output Enable, 3/2 = Write mode (00=Page 1:Red, 01=Page 2:Green, 10=Page 3:Blue, 11=Indirect), 1/0=Read mode (00=Page 1:Red, 01=Page2:Green, 10=Page 3:Blue, 11=Not used).
#define IO_TZ_VMREDMASK 0xFA // Video Module Red bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMGREENMASK 0xFB // Video Module Green bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMBLUEMASK 0xFC // Video Module Blue bit mask (1 bit = 1 pixel, 8 pixels per byte).
#define IO_TZ_VMPAGE 0xFD // Video Module memory page register. [1:0] switches in 1 16Kb page (3 pages) of graphics ram to C000 - FFFF. Bits [1:0] = page, 00 = off, 01 = Red, 10 = Green, 11 = Blue. This overrides all MZ700/MZ80B page switching functions. [7] 0 - normal, 1 - switches in CGROM for upload at D000:DFFF.
//#define IO_TZ_GRAMOPT 0xF4 // MZ80B/MZ2000 GRAM configuration option.
#define IO_TZ_CRTGRPHPRIO 0xF5 // MZ2000 Graphics priority register, character or a graphics colour has front display priority.
#define IO_TZ_CRTGRPHSEL 0xF6 // MZ2000 Graphics output select on CRT or external CRT
#define IO_TZ_GRAMCOLRSEL 0xF7 // MZ2000 Graphics RAM colour bank select.
// Addresses on the tranZPUter board.
//
@@ -142,40 +184,50 @@
#define CPUMODE_IS_SOFT_MASK 0x03F // Mask to filter out the Soft CPU availability flags.
// CPLD Configuration constants.
#define MODE_MZ80K 0x00 // Hardware mode = MZ80K
#define MODE_MZ80C 0x01 // Hardware mode = MZ80C
#define MODE_MZ1200 0x02 // Hardware mode = MZ1200
#define MODE_MZ80A 0x03 // Hardware mode = MZ80A
#define MODE_MZ700 0x04 // Hardware mode = MZ700
#define MODE_MZ800 0x05 // Hardware mode = MZ800
#define MODE_MZ80B 0x06 // Hardware mode = MZ80B
#define MODE_MZ2000 0x07 // Hardware mode = MZ2000
#define MODE_VIDEO_MODULE_DISABLED 0x08 // Hardware enable (bit 3 = 0) or disable of the Video Module.
#define HWMODE_MZ80K 0x00 // Hardware mode = MZ80K
#define HWMODE_MZ80C 0x01 // Hardware mode = MZ80C
#define HWMODE_MZ1200 0x02 // Hardware mode = MZ1200
#define HWMODE_MZ80A 0x03 // Hardware mode = MZ80A
#define HWMODE_MZ700 0x04 // Hardware mode = MZ700
#define HWMODE_MZ800 0x05 // Hardware mode = MZ800
#define HWMODE_MZ80B 0x06 // Hardware mode = MZ80B
#define HWMODE_MZ2000 0x07 // Hardware mode = MZ2000
#define MODE_VIDEO_MODULE_ENABLED 0x08 // Hardware enable (bit 3 = 1) or disable of the Video Module on the newer version, the one below will be removed.
#define MODE_VIDEO_MODULE_DISABLED 0x00 // Hardware enable (bit 3 = 0) or disable of the Video Module.
#define MODE_PRESERVE_CONFIG 0x80 // Preserve hardware configuration on RESET.
// CPLD Command Instruction constants.
#define CPLD_RESET_HOST 1 // CPLD level command to reset the host system.
#define CPLD_HOLD_HOST_BUS 2 // CPLD command to hold the host bus.
#define CPLD_RELEASE_HOST_BUS 3 // CPLD command to release the host bus.
// Video Module control bits.
#define SYSMODE_MZ80A 0x00 // System board mode MZ80A, 2MHz CPU/Bus.
#define SYSMODE_MZ80B 0x01 // System board mode MZ80B, 4MHz CPU/Bus.
#define SYSMODE_MZ700 0x02 // System board mode MZ700, 3.54MHz CPU/Bus.
#define VMMODE_MASK 0xF8 // Mask to mask out video mode.
#define VMMODE_MZ80K MODE_MZ80K // Video mode = MZ80K
#define VMMODE_MZ80C MODE_MZ80C // Video mode = MZ80C
#define VMMODE_MZ1200 MODE_MZ1200 // Video mode = MZ1200
#define VMMODE_MZ80A MODE_MZ80A // Video mode = MZ80A
#define VMMODE_MZ700 MODE_MZ700 // Video mode = MZ700
#define VMMODE_MZ800 MODE_MZ800 // Video mode = MZ800
#define VMMODE_MZ80B MODE_MZ80B // Video mode = MZ80B
#define VMMODE_MZ2000 MODE_MZ2000 // Video mode = MZ2000
#define VMMODE_80CHAR 0x08 // Enable 80 character display.
#define VMMODE_80CHAR_MASK 0xF7 // Mask to filter out display width control bit.
#define VMMODE_COLOUR 0x10 // Enable colour display.
#define VMMODE_COLOUR_MASK 0xEF // Mask to filter out colour control bit.
#define VMMODE_PCGRAM 0x20 // Enable PCG RAM.
#define VMMODE_VGA_MASK 0x3F // Mask to filter out the VGA mode bits.
#define VMMODE_VGA_OFF 0x00 // Set VGA mode off, external monitor is driven by standard internal signals.
#define VMMODE_VGA_640x480 0x40 // Set external monitor to VGA 640x480 @ 60Hz mode.
#define VMMODE_VGA_1024x768 0x80 // Set external monitor to VGA 1024x768 @ 60Hz mode.
#define VMMODE_VGA_800x600 0xC0 // Set external monitor to VGA 800x600 @ 60Hz mode.
#define VMMODE_MASK 0xF0 // Mask to mask out video mode.
#define VMMODE_MZ80K 0x00 // Video mode = MZ80K
#define VMMODE_MZ80C 0x01 // Video mode = MZ80C
#define VMMODE_MZ1200 0x02 // Video mode = MZ1200
#define VMMODE_MZ80A 0x03 // Video mode = MZ80A
#define VMMODE_MZ700 0x04 // Video mode = MZ700
#define VMMODE_MZ800 0x05 // Video mode = MZ800
#define VMMODE_MZ1500 0x06 // Video mode = MZ1500
#define VMMODE_MZ80B 0x07 // Video mode = MZ80B
#define VMMODE_MZ2000 0x08 // Video mode = MZ2000
#define VMMODE_MZ2200 0x09 // Video mode = MZ2200
#define VMMODE_MZ2500 0x0A // Video mode = MZ2500
#define VMMODE_80CHAR 0x10 // Enable 80 character display.
#define VMMODE_80CHAR_MASK 0xEF // Mask to filter out display width control bit.
#define VMMODE_COLOUR 0x20 // Enable colour display.
#define VMMODE_COLOUR_MASK 0xDF // Mask to filter out colour control bit.
#define VMMODE_PCGRAM 0x40 // Enable PCG RAM.
#define VMMODE_VGA_MASK 0xF0 // Mask to filter out the VGA output mode bits.
#define VMMODE_VGA_OFF 0x00 // Set VGA mode off, external monitor is driven by standard internal 60Hz signals.
#define VMMODE_VGA_INT 0x00 // Set VGA mode off, external monitor is driven by standard internal 60Hz signals.
#define VMMODE_VGA_INT50 0x01 // Set VGA mode off, external monitor is driven by standard internal 50Hz signals.
#define VMMODE_VGA_640x480 0x02 // Set external monitor to VGA 640x480 @ 60Hz mode.
#define VMMODE_VGA_800x600 0x03 // Set external monitor to VGA 800x600 @ 60Hz mode.
// VGA mode border control constants.
//
@@ -226,7 +278,11 @@
#define MZ_CMT_ADDR 0x010F0 // Address of the CMT (tape) header record.
#define MZ_CMT_DEFAULT_LOAD_ADDR 0x01200 // The default load address for a CMT, anything below this is normally illegal.
#define MZ_VID_RAM_ADDR 0x0D000 // Start of Video RAM
#define MZ_VID_CGROM_ADDR 0x220000 // Start of the CG ROM memory.
#define MZ_VID_CGRAM_ADDR 0x221000 // Start of the CG RAM memory.
#define MZ_VID_RAM_SIZE 2048 // Size of Video RAM.
#define MZ_VID_MAX_COL 40 // Maximum column for the host display
#define MZ_VID_MAX_ROW 25 // Maximum row for the host display
#define MZ_VID_DFLT_BYTE 0x00 // Default character (SPACE) for video RAM.
#define MZ_ATTR_RAM_ADDR 0xD800 // On machines with the upgrade, the start of the Attribute RAM.
#define MZ_ATTR_RAM_SIZE 2048 // Size of the attribute RAM.
@@ -250,6 +306,7 @@
#define MZ_ROM_1Z_013A_80C "0:\\TZFS\\1z-013a-8.rom" // Original Monitor ROM patched for the Sharp MZ700 patched for 80 column mode.
#define MZ_ROM_1Z_013A_KM_40C "0:\\TZFS\\1z-013a-km.rom" // Original 40 character Monitor ROM for the Sharp MZ700 with keyboard remapped for the MZ80A.
#define MZ_ROM_1Z_013A_KM_80C "0:\\TZFS\\1z-013a-km-8.rom" // Original Monitor ROM patched for the Sharp MZ700 with keyboard remapped for the MZ80A and patched for 80 column mode.
#define MZ_ROM_1Z_013A_2000 "0:\\TZFS\\1z-013a-2000.rom" // Original 40 character Monitor ROM for the Sharp MZ700 modified to run on an MZ-2000.
#define MZ_ROM_9Z_504M_COMBINED "0:\\TZFS\\mz800_ipl.rom" // Original MZ-800 BIOS which comprises the 1Z_013B BIOS, 9Z_504M IPL, CGROM and IOCS.
#define MZ_ROM_9Z_504M "0:\\TZFS\\mz800_9z_504m.rom" // Modified MZ-800 9Z_504M IPL to contain a select TZFS option.
#define MZ_ROM_1Z_013B "0:\\TZFS\\mz800_1z_013b.rom" // Original MZ-800 1Z_013B MZ-700 compatible BIOS.
@@ -257,6 +314,8 @@
#define MZ_ROM_800_IOCS "0:\\TZFS\\mz800_iocs.rom" // Original MZ-800 common IOCS bios.
#define MZ_ROM_MZ80B_IPL "0:\\TZFS\\mz80b_ipl.rom" // Original IPL ROM for the Sharp MZ-80B.
#define MZ_ROM_MZ2000_IPL "0:\\TZFS\\mz2000_ipl.rom" // Original IPL ROM for the Sharp MZ-2000.
#define MZ_ROM_MZ2000_IPL_TZPU "0:\\TZFS\\mz2000_ipl_tzpu.rom" // Modified IPL ROM for the tranZPUter running on the Sharp MZ-2000.
#define MZ_ROM_MZ2000_CGROM "0:\\TZFS\\mz2000_cgrom.rom" // MZ-2000 CGROM.
#define MZ_ROM_TZFS "0:\\TZFS\\tzfs.rom" // tranZPUter Filing System ROM.
#define MZ_ROM_ZPU_ZOS "0:\\ZOS\\zos.rom" // zOS for the ZPU running on the tranZPUter SW-700 board.
@@ -274,6 +333,8 @@
#define TZSVC_CMD_STRUCT_ADDR_CPM 0x4F560 // Address of the command structure within CP/M - exists in 64K Block 4.
#define TZSVC_CMD_STRUCT_ADDR_MZ700 0x6FD80 // Address of the command structure within MZ700 compatible programs - exists in 64K Block 6.
#define TZSVC_CMD_STRUCT_ADDR_ZOS 0x11FD80 // 0x7FD80 // Address of the command structure for zOS use, exists in shared memory rather than FPGA. Spans top of block 6 and all of block 7.
#define TZSVC_CMD_STRUCT_ADDR_MZ2000_NST 0x6FD80 // Address of the command structure within MZ2000 compatible programs during normal state - exists in 64K Block 1.
#define TZSVC_CMD_STRUCT_ADDR_MZ2000_IPL 0x07D80 // Address of the command structure within MZ2000 compatible programs during IPL state - exists in 64K Block 0.
#define TZSVC_CMD_STRUCT_SIZE 0x280 // Size of the inter z80/K64 service command memory.
#define TZSVC_CMD_SIZE (sizeof(t_svcControl)-TZSVC_SECTOR_SIZE)
#define TZVC_MAX_CMPCT_DIRENT_BLOCK TZSVC_SECTOR_SIZE/TZSVC_CMPHDR_SIZE // Maximum number of directory entries per sector.
@@ -299,6 +360,7 @@
#define TZSVC_CMD_LOAD80BIPL 0x24 // Service command requesting the MZ-80B IPL is loaded.
#define TZSVC_CMD_LOAD800BIOS 0x25 // Service command requesting that the MZ800 9Z-504M BIOS is loaded.
#define TZSVC_CMD_LOAD2000IPL 0x26 // Service command requesting the MZ-2000 IPL is loaded.
#define TZSVC_CMD_LOADTZFS 0x2F // Service command requesting the loading of TZFS. This service is for machines which normally dont have a monitor BIOS. ie. MZ-80B/MZ-2000 and manually request TZFS.
#define TZSVC_CMD_LOADBDOS 0x30 // Service command to reload CPM BDOS+CCP.
#define TZSVC_CMD_ADDSDDRIVE 0x31 // Service command to attach a CPM disk to a drive number.
#define TZSVC_CMD_READSDDRIVE 0x32 // Service command to read an attached SD file as a CPM disk drive.
@@ -315,8 +377,11 @@
#define TZSVC_CMD_EMU_SETMZ80A 0x56 // "" "" "" MZ80A.
#define TZSVC_CMD_EMU_SETMZ700 0x57 // "" "" "" MZ700.
#define TZSVC_CMD_EMU_SETMZ800 0x58 // "" "" "" MZ800.
#define TZSVC_CMD_EMU_SETMZ80B 0x59 // "" "" "" MZ80B.
#define TZSVC_CMD_EMU_SETMZ2000 0x5A // "" "" "" MZ2000.
#define TZSVC_CMD_EMU_SETMZ1500 0x59 // "" "" "" MZ1500.
#define TZSVC_CMD_EMU_SETMZ80B 0x5A // "" "" "" MZ80B.
#define TZSVC_CMD_EMU_SETMZ2000 0x5B // "" "" "" MZ2000.
#define TZSVC_CMD_EMU_SETMZ2200 0x5C // "" "" "" MZ2200.
#define TZSVC_CMD_EMU_SETMZ2500 0x5D // "" "" "" MZ2500.
#define TZSVC_CMD_SD_DISKINIT 0x60 // Service command to initialise and provide raw access to the underlying SD card.
#define TZSVC_CMD_SD_READSECTOR 0x61 // Service command to provide raw read access to the underlying SD card.
#define TZSVC_CMD_SD_WRITESECTOR 0x62 // Service command to provide raw write access to the underlying SD card.
@@ -602,17 +667,43 @@ enum VIDEO_FRAMES {
WORKING = 1
};
// Possible machines the tranZPUter can be hosted on and can emulate.
// Possible machine hardware types the tranZPUter is functioning within.
//
enum MACHINE_HW_TYPES {
HW_MZ80K = HWMODE_MZ80K, // Host hardware = MZ-80K.
HW_MZ80C = HWMODE_MZ80C, // Host hardware = MZ-80C.
HW_MZ1200 = HWMODE_MZ1200, // Host hardware = MZ-1200.
HW_MZ80A = HWMODE_MZ80A, // Host hardware = MZ-80A.
HW_MZ700 = HWMODE_MZ700, // Host hardware = MZ-700.
HW_MZ800 = HWMODE_MZ800, // Host hardware = MZ-800.
HW_MZ80B = HWMODE_MZ80B, // Host hardware = MZ-80B.
HW_MZ2000 = HWMODE_MZ2000, // Host hardware = MZ-2000.
HW_UNKNOWN = 0xFF // Host hardware unknown, fault or CPLD misconfiguration.
};
// Possible machine types the tranZPUter can select. These are on a 1:1 with the video controller types for Sharp MZ machines.
//
enum MACHINE_TYPES {
MZ80K = MODE_MZ80K, // Machine = MZ-80K.
MZ80C = MODE_MZ80C, // Machine = MZ-80C.
MZ1200 = MODE_MZ1200, // Machine = MZ-1200.
MZ80A = MODE_MZ80A, // Machine = MZ-80A.
MZ700 = MODE_MZ700, // Machine = MZ-700.
MZ800 = MODE_MZ800, // Machine = MZ-800.
MZ80B = MODE_MZ80B, // Machine = MZ-80B.
MZ2000 = MODE_MZ2000 // Machine = MZ-2000.
MZ80K = VMMODE_MZ80K, // Machine = MZ-80K.
MZ80C = VMMODE_MZ80C, // Machine = MZ-80C.
MZ1200 = VMMODE_MZ1200, // Machine = MZ-1200.
MZ80A = VMMODE_MZ80A, // Machine = MZ-80A.
MZ700 = VMMODE_MZ700, // Machine = MZ-700.
MZ800 = VMMODE_MZ800, // Machine = MZ-800.
MZ1500 = VMMODE_MZ1500, // Machine = MZ-1500.
MZ80B = VMMODE_MZ80B, // Machine = MZ-80B.
MZ2000 = VMMODE_MZ2000, // Machine = MZ-2000.
MZ2200 = VMMODE_MZ2200, // Machine = MZ-2200.
MZ2500 = VMMODE_MZ2500, // Machine = MZ-2500.
UNKNOWN = 0xFF // Machine unknown, fault in coding.
};
// Groups to which the machines belong. This is a lineage route of the Sharp machines.
//
enum MACHINE_GROUP {
GROUP_MZ80K = 0, // Machines in the MZ80K group, ie. MZ80K/C/1200/80A
GROUP_MZ700 = 1, // Machines in the MZ700 group, ie. MZ700/800/1500
GROUP_MZ80B = 2 // Machines in the MZ80B group, ie. MZ80B/2000/2200/2500
};
// Get and Set flags within the CPLD config and status registers.
@@ -726,8 +817,12 @@ typedef struct {
enum CTRL_MODE ctrlMode; // Mode of control, ie normal Z80 Running, controlling mainboard, controlling tranZPUter.
enum BUS_DIRECTION busDir; // Direction the bus has been configured for.
enum MACHINE_TYPES hostType; // The underlying host machine, 0 = Sharp MZ-80A, 1 = MZ-700, 2 = MZ-80B
enum MACHINE_TYPES machineMode; // Machine compatibility, 0 = Sharp MZ-80K, 1 = MZ-80C, 2 = MZ-1200, 3 = MZ-80A, 4 = MZ-700, 5 = MZ-800, 6 = MZ-80B, 7 = MZ-2000
enum MACHINE_HW_TYPES hostType; // The underlying host machine, 0 = Sharp MZ-80A, 1 = MZ-700, 2 = MZ-80B
// enum MACHINE_TYPES machineMode; // Machine compatibility, 0 = Sharp MZ-80K, 1 = MZ-80C, 2 = MZ-1200, 3 = MZ-80A, 4 = MZ-700, 5 = MZ-800, 6 = MZ-80B, 7 = MZ-2000
uint8_t iplMode; // Flag to indicate if the host is in IPL (boot) or run mode. Applicable on the MZ-2000/MZ-80B only.
uint8_t blockResetActions; // Flag to request reset actions are blocked on the next detected reset. This is useful on startup or when loading a monitor ROM set different to the default.
uint8_t cpldVersion; // CPLD configuration version. 1 = original tranZPUter SW, 2 = tranZPUter SW-700 v1
uint8_t softcpuInfo; // FPGA Soft CPU capabilities. 0 = None.
t_mz700 mz700; // MZ700 emulation control to detect IO commands and adjust the memory map accordingly.
t_mz80b mz80b; // MZ-80B emulation control to detect IO commands and adjust the memory map and I/O forwarding accordingly.
@@ -818,6 +913,12 @@ typedef struct {
uint8_t asciiCode;
} t_asciiMap;
// Mapping table from Ascii to Sharp MZ display code.
//
typedef struct {
uint8_t dispCode;
} t_dispCodeMap;
// Application execution constants.
//
@@ -873,6 +974,8 @@ char *getAttributeFrame(enum VIDEO_FRAMES);
FRESULT loadZ80Memory(const char *, uint32_t, uint32_t, uint32_t, uint32_t *, enum TARGETS, uint8_t);
FRESULT saveZ80Memory(const char *, uint32_t, uint32_t, t_svcDirEnt *, enum TARGETS);
FRESULT loadMZFZ80Memory(const char *, uint32_t, uint32_t *, uint8_t, enum TARGETS, uint8_t);
void clsHost(void);
void printfHost(uint8_t, uint8_t, char *, ...);
// Getter/Setter methods!
uint8_t isZ80Reset(void);
@@ -901,13 +1004,14 @@ uint8_t svcWriteCPMDrive(void);
uint32_t getServiceAddr(void);
void processServiceRequest(void);
void TZPUservice(void);
uint8_t loadBIOS(const char *biosFileName, uint8_t machineMode, uint32_t loadAddr);
uint8_t loadBIOS(const char *, uint32_t);
FRESULT loadTZFS(char *, uint32_t);
void hardResetTranZPUter(void);
void loadTranZPUterDefaultROMS(uint8_t);
void tranZPUterControl(void);
uint8_t testTZFSAutoBoot(void);
void setHost(void);
void setupTranZPUter(void);
void setHost(uint8_t);
void setupTranZPUter(uint8_t, char *, char *);
void testRoutine(void);
// Sharp MZ Series emulation methods.

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startup/zos_k64f.ld
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@@ -39,7 +39,7 @@ ENTRY(_VectorsFlash)
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
RAM (rwx) : ORIGIN = 0x20006000, LENGTH = 0x0002A000
RAM (rwx) : ORIGIN = 0x2000E000, LENGTH = 0x00022000
}
/*
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
@@ -124,14 +124,14 @@ SECTIONS
} > RAM
__heap_section_start__ = .;
.heap 0x20016000:
.heap 0x2001E000:
{
. = ALIGN(8);
_ebss = .;
/* __end__ = .; */
/* PROVIDE(end = .); */
__HeapBase = .;
. += 0x00018000;
. += 0x00010000;
__HeapLimit = .;
} > RAM
__heap_section_end__ = .;

128
zOS/src/zOS.cpp
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@@ -35,6 +35,8 @@
// which are normally the first port of call for strange behaviour
// but it was seen that using them for running the tranzputer service
// wasnt really needed as this could be based on a readline idle call.
// Oct 2021 - Extensions to support the MZ-2000 host and the Sharp MZ Series FPGA
// Emulation.
//
// Notes: See Makefile to enable/disable conditional components
// USELOADB - The Byte write command is implemented in hw/sw so use it.
@@ -128,8 +130,8 @@
#endif
// Version info.
#define VERSION "v1.32"
#define VERSION_DATE "25/07/2021"
#define VERSION "v1.40b"
#define VERSION_DATE "28/10/2021"
#define PROGRAM_NAME "zOS"
// Utility functions.
@@ -301,6 +303,7 @@ void tranZPUterControl(void)
//
if(getZ80IO(&ioAddr) == 1)
{
//printf("Activity on IO:%02x\n", ioAddr);
switch(ioAddr)
{
// Service request. Actual data about the request is stored in the Z80 memory, so read the request and process.
@@ -323,6 +326,41 @@ void tranZPUterControl(void)
}
#endif
// Method to setup access to the SD card.
//
static uint8_t diskInitialised = 0;
static uint8_t fsInitialised = 0;
#if defined(__SD_CARD__)
int setupSDCard(void)
{
// Local variables.
FRESULT fr = FR_INVALID_DRIVE;
char buf[120];
// Initialise the first disk if FS enabled as external commands depend on it.
//
fr = FR_NOT_ENABLED;
if(!disk_initialize(0, 1))
{
sprintf(buf, "0:");
fr = f_mount(&G.FatFs[0], buf, 0);
}
if(fr)
{
printf("Failed to initialise sd card 0, please init manually.\n");
} else
{
// Indicate disk and filesystem are accessible.
diskInitialised = 1;
fsInitialised = 1;
}
// Indicate result, FR_OK = SD card setup and ready, all other values SD card not ready.
return(fr);
}
#endif
// Interactive command processor. Allow user to input a command and execute accordingly.
//
int cmdProcessor(void)
@@ -339,8 +377,6 @@ int cmdProcessor(void)
uint32_t memAddr;
#if defined(__SD_CARD__)
char *src1FileName;
uint8_t diskInitialised = 0;
uint8_t fsInitialised = 0;
uint8_t trying = 0;
uint32_t retCode = 0xffffffff;
FRESULT fr;
@@ -355,38 +391,6 @@ int cmdProcessor(void)
// Initialise any globals in the structure used to pass working variables to apps.
G.Sector = 0;
#if defined __TRANZPUTER__
// Setup the tranZPUter hardware ready for action!
setupTranZPUter();
#endif
// Initialise the first disk if FS enabled as external commands depend on it.
#if defined(__SD_CARD__)
fr = FR_NOT_ENABLED;
if(!disk_initialize(0, 1))
{
sprintf(line, "0:");
fr = f_mount(&G.FatFs[0], line, 0);
}
if(fr)
{
printf("Failed to initialise sd card 0, please init manually.\n");
} else
{
diskInitialised = 1;
fsInitialised = 1;
#if defined __TRANZPUTER__
// Setup memory on Z80 to default.
loadTranZPUterDefaultROMS(CPUMODE_SET_Z80);
// Cache initial directory.
svcCacheDir(TZSVC_DEFAULT_MZF_DIR, MZF, 1);
#endif
}
#endif
while(1)
{
// Prompt to indicate input required.
@@ -917,7 +921,6 @@ int main(int argc, char **argv)
//
#if defined __K64F__
Serial.begin(9600);
delay(2000); // Give time for the USB Serial Port to connect.
// I/O is connected in the _read and_write methods withiin startup file mx20dx128.c.
setbuf(stdout, NULL);
@@ -936,6 +939,11 @@ int main(int argc, char **argv)
#elif defined __M68K__
#endif
#if defined __TRANZPUTER__
// Setup the tranZPUter hardware ready for action!
setupTranZPUter(0, VERSION, VERSION_DATE);
#endif
// Setup the configuration using the SoC configuration register if implemented otherwise the compiled internals.
@@ -949,24 +957,50 @@ int main(int argc, char **argv)
//TIMER_COUNTER(TIMER1) = 100000; // Timer is prescaled to 100KHz
//enableTimer();
// Indicate life...
//
#if !defined __SHARPMZ__
printf("Running...\n");
#endif
#if !defined __SHARPMZ__
printf("Enabling interrupts...\n");
#endif
// Enable interrupts.
SetIntHandler(interrupt_handler);
#if defined __ZPU__
//EnableInterrupt(INTR_TIMER | INTR_PS2 | INTR_IOCTL_RD | INTR_IOCTL_WR | INTR_UART0_RX | INTR_UART0_TX | INTR_UART1_RX | INTR_UART1_TX);
//EnableInterrupt(INTR_UART0_RX | INTR_UART1_RX); // | INTR_TIMER);
#endif
// Intro screen
#if defined(__SD_CARD__)
setupSDCard();
#endif
#if defined __TRANZPUTER__
// If the SD card is present and ready, initialise the tranZPUter logic dependent upon file storage.
if(diskInitialised && fsInitialised)
{
// Setup memory on Z80 to default.
loadTranZPUterDefaultROMS(CPUMODE_SET_Z80);
// Cache initial directory.
svcCacheDir(TZSVC_DEFAULT_MZF_DIR, MZF, 1);
//No SD card found so setup tranZPUter accordingly.
setupTranZPUter(1, NULL, NULL);
} else
{
// No SD card found so setup tranZPUter accordingly.
setupTranZPUter(9, NULL, NULL);
}
#endif
#if defined __K64F__
// Give time for the USB Serial Port to connect.
delay(2000);
#endif
// Signon with version information.
printVersion(1);
#if defined __TRANZPUTER__
// Complete tranZPUter setup.
setupTranZPUter(8, NULL, NULL);
#endif
// Command processor. If it exits, then reset the CPU.
cmdProcessor();