diff --git a/apps/tzclear/tzclear.c b/apps/tzclear/tzclear.c index 1398cca..a58d8af 100644 --- a/apps/tzclear/tzclear.c +++ b/apps/tzclear/tzclear.c @@ -253,14 +253,14 @@ uint32_t app(uint32_t param1, uint32_t param2) printf("Mainboard only has 64K, please change the address or size.\n"); return(12); } - if(fpga_flag == 1 && (startAddr >= 0x1000000 || startAddr + memSize > 0x1000000)) + if(fpga_flag == 1 && (startAddr >= TZ_MAX_FPGA_MEM || startAddr + memSize > TZ_MAX_FPGA_MEM)) { - printf("FPGA only has a 16M window, please change the address or size.\n"); + printf("FPGA only has a %dM window, please change the address or size.\n", TZ_MAX_FPGA_MEM/1024000); return(13); } - if(mainboard_flag == 0 && fpga_flag == 0 && (startAddr >= 0x80000 || startAddr + memSize > 0x80000)) + if(mainboard_flag == 0 && fpga_flag == 0 && (startAddr >= TZ_MAX_Z80_MEM || startAddr + memSize > TZ_MAX_Z80_MEM)) { - printf("tranZPUter board only has 512K, please change the address or size.\n"); + printf("tranZPUter board only has %dK, please change the address or size.\n", TZ_MAX_Z80_MEM/1024); return(14); } diff --git a/apps/tzdump/tzdump.c b/apps/tzdump/tzdump.c index d097f98..f7426ac 100644 --- a/apps/tzdump/tzdump.c +++ b/apps/tzdump/tzdump.c @@ -249,14 +249,14 @@ uint32_t app(uint32_t param1, uint32_t param2) printf("Mainboard only has 64K, please change the address or size.\n"); return(11); } - if(fpga_flag == 1 && (startAddr >= 0x1000000 || startAddr + memSize > 0x1000000)) + if(fpga_flag == 1 && (startAddr >= TZ_MAX_FPGA_MEM || startAddr + memSize > TZ_MAX_FPGA_MEM)) { - printf("FPGA only has a 16M window, please change the address or size.\n"); + printf("FPGA only has a %dM window, please change the address or size.\n", TZ_MAX_FPGA_MEM/1024000); return(13); } - if(mainboard_flag == 0 && fpga_flag == 0 && (startAddr >= 0x80000 || startAddr + memSize > 0x80000)) + if(mainboard_flag == 0 && fpga_flag == 0 && (startAddr >= TZ_MAX_Z80_MEM || startAddr + memSize > TZ_MAX_Z80_MEM)) { - printf("tranZPUter board only has 512K, please change the address or size.\n"); + printf("tranZPUter board only has %dK, please change the address or size.\n", TZ_MAX_Z80_MEM/1024); return(12); } diff --git a/apps/tzload/tzload.c b/apps/tzload/tzload.c index ad39e74..bdd3cc4 100644 --- a/apps/tzload/tzload.c +++ b/apps/tzload/tzload.c @@ -323,14 +323,14 @@ uint32_t app(uint32_t param1, uint32_t param2) printf("Mainboard only has 64K, please change the address and size.\n"); return(19); } - if(fpga_flag == 1 && mzf_flag == 0 && (memAddr >= 0x1000000 || memAddr + memSize > 0x1000000)) + if(fpga_flag == 1 && mzf_flag == 0 && (memAddr >= TZ_MAX_FPGA_MEM || memAddr + memSize > TZ_MAX_FPGA_MEM)) { - printf("FPGA only has a 16M window, please change the address or size.\n"); + printf("FPGA only has a %dM window, please change the address or size.\n", TZ_MAX_FPGA_MEM/1024000); return(20); } - if(mainboard_flag == 0 && fpga_flag == 0 && mzf_flag == 0 && (memAddr >= 0x80000 || memAddr + memSize > 0x80000)) + if(mainboard_flag == 0 && fpga_flag == 0 && mzf_flag == 0 && (memAddr >= TZ_MAX_Z80_MEM || memAddr + memSize > TZ_MAX_Z80_MEM)) { - printf("tranZPUter board only has 512K, please change the address and size.\n"); + printf("tranZPUter board only has %dK, please change the address and size.\n", TZ_MAX_Z80_MEM/1024); return(21); } } diff --git a/common/k64f_soc.c b/common/k64f_soc.c index 842d60c..36ab00e 100644 --- a/common/k64f_soc.c +++ b/common/k64f_soc.c @@ -136,7 +136,7 @@ void showSoCConfig(void) #ifdef DRV_MMC printf(" MMC = %08lX\n", DRV_MMC); #endif - puts("\n"); + //puts("\n"); } // Function to print out the ZPU Id in text form. diff --git a/common/tranzputer.c b/common/tranzputer.c index f144e76..ab935d5 100644 --- a/common/tranzputer.c +++ b/common/tranzputer.c @@ -60,6 +60,7 @@ // v1.6 Apr 2021 - Fixed a SD directory cache bug when switching between directories. // The bug occurs due to an interaction between the heap management // and threads. +// v1.7 May 2021 - Changes to use 512K-1Mbyte Z80 Static RAM, build time configurable. // // Notes: See Makefile to enable/disable conditional components // @@ -1381,7 +1382,7 @@ uint8_t copyFromZ80(uint8_t *dst, uint32_t src, uint32_t size, enum TARGETS targ // Sanity checks. // - if((target == MAINBOARD && (src+size) > 0x10000) || (target == TRANZPUTER && (src+size) > 0x80000) || (target == FPGA && (src+size) > 0x1000000) ) + if((target == MAINBOARD && (src+size) > 0x10000) || (target == TRANZPUTER && (src+size) > TZ_MAX_Z80_MEM) || (target == FPGA && (src+size) > TZ_MAX_FPGA_MEM) ) return(1); // If the Z80 is in RUN mode, request the bus. @@ -1466,7 +1467,7 @@ uint8_t copyToZ80(uint32_t dst, uint8_t *src, uint32_t size, enum TARGETS target // Sanity checks. // - if((target == MAINBOARD && (dst+size) > 0x10000) || (target == TRANZPUTER && (dst+size) > 0x80000) || (target == FPGA && (dst+size) > 0x1000000) ) + if((target == MAINBOARD && (dst+size) > 0x10000) || (target == TRANZPUTER && (dst+size) > TZ_MAX_Z80_MEM) || (target == FPGA && (dst+size) > TZ_MAX_FPGA_MEM) ) return(1); // If the Z80 is in RUN mode, request the bus. @@ -1549,7 +1550,7 @@ void fillZ80Memory(uint32_t addr, uint32_t size, uint8_t data, enum TARGETS targ // Sanity checks. // - if((target == MAINBOARD && (addr+size) > 0x10000) || (target == TRANZPUTER && (addr+size) > 0x80000) || (target == FPGA && (addr+size) > 0x1000000) ) + if((target == MAINBOARD && (addr+size) > 0x10000) || (target == TRANZPUTER && (addr+size) > TZ_MAX_Z80_MEM) || (target == FPGA && (addr+size) > TZ_MAX_FPGA_MEM) ) return; // If the Z80 is in RUN mode, request the bus. @@ -2254,7 +2255,7 @@ int memoryDumpZ80(uint32_t memaddr, uint32_t memsize, uint32_t dispaddr, uint8_t // Sanity checks. // - if((target == MAINBOARD && (memaddr+memsize) > 0x10000) || (target == TRANZPUTER && (memaddr+memsize) > 0x80000) || (target == FPGA && (memaddr+memsize) > 0x1000000)) + if((target == MAINBOARD && (memaddr+memsize) > 0x10000) || (target == TRANZPUTER && (memaddr+memsize) > TZ_MAX_Z80_MEM) || (target == FPGA && (memaddr+memsize) > TZ_MAX_FPGA_MEM)) return(1); // If the Z80 is in RUN mode, request the bus. @@ -4216,7 +4217,7 @@ uint32_t getServiceAddr(void) // zOS addr = TZSVC_CMD_STRUCT_ADDR_ZOS; } -//printf("getServiceAddr:%02x,%02x,%02x,%01x,%08lx,%02x\n", z80Control.runCtrlLatch, z80Control.curCtrlLatch, memoryMode, cpuConfig, addr, svcControl.cmd); +printf("getServiceAddr:%02x,%02x,%02x,%01x,%08lx,%02x\n", z80Control.runCtrlLatch, z80Control.curCtrlLatch, memoryMode, cpuConfig, addr, svcControl.cmd); return(addr); } @@ -4244,12 +4245,12 @@ void processServiceRequest(void) z80Control.svcControlAddr = getServiceAddr(); // Get the command and associated parameters. - copyFromZ80((uint8_t *)&svcControl, z80Control.svcControlAddr, TZSVC_CMD_SIZE, z80Control.svcControlAddr > 0x80000 ? FPGA : TRANZPUTER); + copyFromZ80((uint8_t *)&svcControl, z80Control.svcControlAddr, TZSVC_CMD_SIZE, z80Control.svcControlAddr > TZ_MAX_Z80_MEM ? FPGA : TRANZPUTER); // Need to get the remainder of the data for the write operations. if(svcControl.cmd == TZSVC_CMD_WRITEFILE || svcControl.cmd == TZSVC_CMD_NEXTWRITEFILE || svcControl.cmd == TZSVC_CMD_WRITESDDRIVE || svcControl.cmd == TZSVC_CMD_SD_WRITESECTOR) { - copyFromZ80((uint8_t *)&svcControl.sector, z80Control.svcControlAddr+TZSVC_CMD_SIZE, TZSVC_SECTOR_SIZE, z80Control.svcControlAddr > 0x80000 ? FPGA : TRANZPUTER); + copyFromZ80((uint8_t *)&svcControl.sector, z80Control.svcControlAddr+TZSVC_CMD_SIZE, TZSVC_SECTOR_SIZE, z80Control.svcControlAddr > TZ_MAX_Z80_MEM ? FPGA : TRANZPUTER); } // Check this is a valid request. @@ -4531,7 +4532,7 @@ void processServiceRequest(void) // Update the status in the service control record then copy it across to the Z80. // svcControl.result = status; - copyToZ80(z80Control.svcControlAddr, (uint8_t *)&svcControl, copySize, z80Control.svcControlAddr > 0x80000 ? FPGA : TRANZPUTER); + copyToZ80(z80Control.svcControlAddr, (uint8_t *)&svcControl, copySize, z80Control.svcControlAddr > TZ_MAX_Z80_MEM ? FPGA : TRANZPUTER); // Need to refresh the directory? Do this at the end of the routine so the Sharp MZ80A isnt held up. if(refreshCacheDir) @@ -4696,7 +4697,7 @@ void setupTranZPUter(void) setupIRQ(); // Start off by clearing active memory banks, the AS6C4008 chip holds random values at power on. - fillZ80Memory(0x000000, 0x80000, 0x00, TRANZPUTER); + fillZ80Memory(0x000000, TZ_MAX_Z80_MEM, 0x00, TRANZPUTER); } // Test routine. Add code here to test an item within the kernel. Anything accessing hardware generally has to call the kernel as it doesnt have real access. diff --git a/include/sharpmz.h b/include/sharpmz.h index 6f90f98..69faf2f 100755 --- a/include/sharpmz.h +++ b/include/sharpmz.h @@ -67,28 +67,29 @@ // an address to read 32bit word aligned value. // // Y+100000:Y+17FFFF = 512K Static RAM on the tranZPUter board. All reads are 32bit, all writes are 8, 16 or 32bit wide on word boundary. -// Y+180000:Y+1BFFFF = 64K address space on host mainboard (ie. RAM/ROM/Memory mapped I/O) accessed 1 byte at a time. The physical address is word aligned per byte, so 4 bytes on the ZPU address space = 1 +// +// Y+200000:Y+23FFFF = 64K address space on host mainboard (ie. RAM/ROM/Memory mapped I/O) accessed 1 byte at a time. The physical address is word aligned per byte, so 4 bytes on the ZPU address space = 1 // byte on the Z80 address space. ie. 0x00780 ZPU = 0x0078 Z80. -// Y+1C0000:Y+1FFFFF = 64K I/O space on the host mainboard or the underlying CPLD/FPGA. 64K address space is due to the Z80 ability to address 64K via the Accumulator being set in 15:8 and the port in 7:0. +// Y+240000:Y+27FFFF = 64K I/O space on the host mainboard or the underlying CPLD/FPGA. 64K address space is due to the Z80 ability to address 64K via the Accumulator being set in 15:8 and the port in 7:0. // The ZPU, via a direct address will mimic this ability for hardware which requires it. ie. A write to 0x3F with 0x10 in the accumulator would yield an address of 0x103f. // All reads are 8 bit, writes are 8, 16 or 32bit wide on word boundary. The physical address is word aligned per byte, so 4 bytes on the ZPU address space = 1 // byte on the Z80 address space. ie. 0x00780 ZPU = 0x0078 Z80. // -// Y+200000:Y+20FFFF = 64K address space on host mainboard (ie. RAM/ROM/Memory mapped I/O) accessed 4 bytes at a time, a 32 bit read will return 4 consecutive bytes,1start of read must be on a 32bit word boundary. -// Y+280000:Y+2FFFFF = 512K unassigned. +// Y+280000:Y+28FFFF = 64K address space on host mainboard (ie. RAM/ROM/Memory mapped I/O) accessed 4 bytes at a time, a 32 bit read will return 4 consecutive bytes,1start of read must be on a 32bit word boundary. +// Y+290000:Y+2FFFFF = Unassigned. // // Y = 2Mbyte sector in ZPU address space the Z80 bus interface is located. This is normally below the ZPU I/O sector and set to 0xExxxxx // // // 0x000000 00000000 - Normal Sharp MZ behaviour, Video Controller controlled by Z80 bus transactions. // Y+100000:Y+17FFFF = 512K Static RAM on the tranZPUter board. All reads are 32bit, all writes are 8, 16 or 32bit wide on word boundary. -// Y+180000:Y+1BFFFF = 64K address space on host mainboard (ie. RAM/ROM/Memory mapped I/O) accessed 1 byte at a time. The physical address is word aligned per byte, so 4 bytes on the ZPU address space = 1 +// Y+200000:Y+23FFFF = 64K address space on host mainboard (ie. RAM/ROM/Memory mapped I/O) accessed 1 byte at a time. The physical address is word aligned per byte, so 4 bytes on the ZPU address space = 1 // byte on the Z80 address space. ie. 0x00780 ZPU = 0x0078 Z80. -// Y+1C0000:Y+1FFFFF = 64K I/O space on the host mainboard or the underlying CPLD/FPGA. 64K address space is due to the Z80 ability to address 64K via the Accumulator being set in 15:8 and the port in 7:0. +// Y+240000:Y+27FFFF = 64K I/O space on the host mainboard or the underlying CPLD/FPGA. 64K address space is due to the Z80 ability to address 64K via the Accumulator being set in 15:8 and the port in 7:0. // The ZPU, via a direct address will mimic this ability for hardware which requires it. ie. A write to 0x3F with 0x10 in the accumulator would yield an address of 0xF103f. // All reads are 8 bit, writes are 8, 16 or 32bit wide on word boundary. The physical address is word aligned per byte, so 4 bytes on the ZPU address space = 1 // byte on the Z80 address space. ie. 0x00780 ZPU = 0x0078 Z80. -// Y+200000:Y+20FFFF = 64K address space on host mainboard (ie. RAM/ROM/Memory mapped I/O) accessed 4 bytes at a time, a 32 bit read will return 4 consecutive bytes,1start of read must be on a 32bit word boundary. +// Y+290000:Y+28FFFF = 64K address space on host mainboard (ie. RAM/ROM/Memory mapped I/O) accessed 4 bytes at a time, a 32 bit read will return 4 consecutive bytes,1start of read must be on a 32bit word boundary. // // Where Y is the base address, 0xC00000 in this implementation. // ----------------------------------------------------------------------------------------------------------------------- @@ -267,9 +268,9 @@ // Memory mapped I/O on the mainboard. These addresses are processed by the Z80BUS FSM which converts a 32bit ZPU cycle into several 8bi Z80 cycles. // -#define MB_8BIT_BASE_ADDR Z80_BUS_BASE_ADDR + 0x080000 -#define MB_32BIT_BASE_ADDR Z80_BUS_BASE_ADDR + 0x100000 -#define MB_32BIT_IO_ADDR Z80_BUS_BASE_ADDR + 0x0C0000 +#define MB_8BIT_BASE_ADDR Z80_BUS_BASE_ADDR + 0x100000 +#define MB_32BIT_BASE_ADDR Z80_BUS_BASE_ADDR + 0x180000 +#define MB_32BIT_IO_ADDR Z80_BUS_BASE_ADDR + 0x140000 // 8 Bit access addresses - used for writing and reading on a 32bit boundary with lower address lines set to 00. Writing is 1 byte only. #define MBADDR_8BIT_KEYPA MB_8BIT_BASE_ADDR + (4*0xE000) // Mainboard 8255 Port A diff --git a/include/tranzputer.h b/include/tranzputer.h index 4dcbc21..8248dc5 100755 --- a/include/tranzputer.h +++ b/include/tranzputer.h @@ -11,6 +11,7 @@ // History: May 2020 - Initial write of the TranZPUter software. // Jul 2020 - Updates to accommodate v2.1 of the tranZPUter board. // Sep 2020 - Updates to accommodate v2.2 of the tranZPUter board. +// May 2021 - Changes to use 512K-1Mbyte Z80 Static RAM, build time configurable. // // Notes: See Makefile to enable/disable conditional components // @@ -43,6 +44,8 @@ #define DEFAULT_BUSREQ_TIMEOUT 5000 // Timeout for a Z80 Bus request operation in milliseconds. #define DEFAULT_RESET_PULSE_WIDTH 500000 // Pulse width of a reset signal in K64F clock ticks. #define TZFS_AUTOBOOT_FLAG "0:\\TZFSBOOT.FLG" // Filename used as a flag, if this file exists in the SD root directory then TZFS is booted automatically. +#define TZ_MAX_Z80_MEM 0x100000 // Maximum Z80 memory available on the tranZPUter board. +#define TZ_MAX_FPGA_MEM 0x1000000 // Maximum addressable memory area inside the FPGA. // tranZPUter Memory Modes - select one of the 32 possible memory models using these constants. // @@ -66,14 +69,14 @@ #define TZMM_FPGA 0x15 // Open up access for the K64F to the FPGA resources such as memory. All other access to RAM or mainboard is blocked. #define TZMM_TZPUM 0x16 // Everything is on mainboard, no access to tranZPUter memory. #define TZMM_TZPU 0x17 // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory. K64F drives A18-A16 allowing full access to RAM. -#define TZMM_TZPU0 0x18 // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected. -#define TZMM_TZPU1 0x19 // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected. -#define TZMM_TZPU2 0x1A // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected. -#define TZMM_TZPU3 0x1B // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected. -#define TZMM_TZPU4 0x1C // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected. -#define TZMM_TZPU5 0x1D // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected. -#define TZMM_TZPU6 0x1E // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected. -#define TZMM_TZPU7 0x1F // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected. +//#define TZMM_TZPU0 0x18 // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 0 is selected. +//#define TZMM_TZPU1 0x19 // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 1 is selected. +//#define TZMM_TZPU2 0x1A // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 2 is selected. +//#define TZMM_TZPU3 0x1B // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 3 is selected. +//#define TZMM_TZPU4 0x1C // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 4 is selected. +//#define TZMM_TZPU5 0x1D // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 5 is selected. +//#define TZMM_TZPU6 0x1E // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 6 is selected. +//#define TZMM_TZPU7 0x1F // Everything is in tranZPUter domain, no access to underlying Sharp mainboard unless memory management mode is switched. tranZPUter RAM 64K block 7 is selected. // IO addresses on the tranZPUter or mainboard. // @@ -687,7 +690,7 @@ typedef struct { // typedef struct { #if !defined(__APP__) || defined(__TZFLUPD__) - uint32_t svcControlAddr; // Address of the service control record within the 512K static RAM bank. + uint32_t svcControlAddr; // Address of the service control record within the Z80 static RAM bank. uint8_t refreshAddr; // Refresh address for times when the K64F must issue refresh cycles on the Z80 bus. uint8_t disableRefresh; // Disable refresh if the mainboard DRAM isnt being used. uint8_t runCtrlLatch; // Latch value the Z80 is running with. diff --git a/libraries/lib/libimath2-k64f.a b/libraries/lib/libimath2-k64f.a index 658e10a..d89d144 100644 Binary files a/libraries/lib/libimath2-k64f.a and b/libraries/lib/libimath2-k64f.a differ diff --git a/libraries/lib/libimath2-zpu.a b/libraries/lib/libimath2-zpu.a index d11406e..ba345a3 100644 Binary files a/libraries/lib/libimath2-zpu.a and b/libraries/lib/libimath2-zpu.a differ diff --git a/libraries/lib/libumansi-k64f.a b/libraries/lib/libumansi-k64f.a index 23b25ac..35d5c9d 100644 Binary files a/libraries/lib/libumansi-k64f.a and b/libraries/lib/libumansi-k64f.a differ diff --git a/libraries/lib/libumansi-zpu.a b/libraries/lib/libumansi-zpu.a index 1f1b83a..169007d 100644 Binary files a/libraries/lib/libumansi-zpu.a and b/libraries/lib/libumansi-zpu.a differ diff --git a/libraries/lib/libummath-k64f.a b/libraries/lib/libummath-k64f.a index 55e6206..400e289 100644 Binary files a/libraries/lib/libummath-k64f.a and b/libraries/lib/libummath-k64f.a differ diff --git a/libraries/lib/libummath-zpu.a b/libraries/lib/libummath-zpu.a index 68b58d6..b496220 100644 Binary files a/libraries/lib/libummath-zpu.a and b/libraries/lib/libummath-zpu.a differ diff --git a/libraries/lib/libummathf-k64f.a b/libraries/lib/libummathf-k64f.a index 9a36777..a2d0525 100644 Binary files a/libraries/lib/libummathf-k64f.a and b/libraries/lib/libummathf-k64f.a differ diff --git a/libraries/lib/libummathf-zpu.a b/libraries/lib/libummathf-zpu.a index 479507f..07398fb 100644 Binary files a/libraries/lib/libummathf-zpu.a and b/libraries/lib/libummathf-zpu.a differ diff --git a/libraries/lib/libummisc-k64f.a b/libraries/lib/libummisc-k64f.a index b565796..64fc3c3 100644 Binary files a/libraries/lib/libummisc-k64f.a and b/libraries/lib/libummisc-k64f.a differ diff --git a/libraries/lib/libummisc-zpu.a b/libraries/lib/libummisc-zpu.a index 21e59cd..406635a 100644 Binary files a/libraries/lib/libummisc-zpu.a and b/libraries/lib/libummisc-zpu.a differ diff --git a/libraries/lib/libumstdio-k64f.a b/libraries/lib/libumstdio-k64f.a index 0bf0ef5..c46bcb7 100644 Binary files a/libraries/lib/libumstdio-k64f.a and b/libraries/lib/libumstdio-k64f.a differ diff --git a/libraries/lib/libumstdio-zpu.a b/libraries/lib/libumstdio-zpu.a index 46d7279..3c71b90 100644 Binary files a/libraries/lib/libumstdio-zpu.a and b/libraries/lib/libumstdio-zpu.a differ diff --git a/rtl/IOCP_zOS_BootROM.vhd b/rtl/IOCP_zOS_BootROM.vhd index c864c66..3ed75cd 100644 --- a/rtl/IOCP_zOS_BootROM.vhd +++ b/rtl/IOCP_zOS_BootROM.vhd @@ -5393,18 +5393,18 @@ shared variable ram : ram_type := 6355 => x"f2397478", 6356 => x"317b2956", 6357 => x"fe9a39fb", - 6358 => x"3d0d86ee", + 6358 => x"3d0d878e", 6359 => x"808c53ff", 6360 => x"8a733487", 6361 => x"73348573", 6362 => x"34817334", - 6363 => x"86ee809c", + 6363 => x"878e809c", 6364 => x"5580f475", 6365 => x"34ffb075", - 6366 => x"3486ee80", + 6366 => x"34878e80", 6367 => x"98568076", 6368 => x"34807634", - 6369 => x"86ee8094", + 6369 => x"878e8094", 6370 => x"548a7434", 6371 => x"807434ff", 6372 => x"80753481", @@ -7183,13 +7183,13 @@ shared variable ram : ram_type := 8145 => x"59555874", 8146 => x"812e838c", 8147 => x"3881f054", - 8148 => x"7386ee80", + 8148 => x"73878e80", 8149 => x"8034800b", 8150 => x"87c09888", 8151 => x"0c87c098", 8152 => x"88085675", 8153 => x"802ef638", - 8154 => x"86ee8084", + 8154 => x"878e8084", 8155 => x"08577683", 8156 => x"f4f81534", 8157 => x"81147081", @@ -7492,8 +7492,8 @@ shared variable ram : ram_type := 8454 => x"850b83f3", 8455 => x"d4085556", 8456 => x"fe0b8115", - 8457 => x"34800b86", - 8458 => x"f080e834", + 8457 => x"34800b87", + 8458 => x"9080e834", 8459 => x"87c0989c", 8460 => x"0883f3d4", 8461 => x"085580ce", @@ -7563,7 +7563,7 @@ shared variable ram : ram_type := 8525 => x"f3d40855", 8526 => x"56fe0b81", 8527 => x"1534800b", - 8528 => x"86f080e8", + 8528 => x"879080e8", 8529 => x"3487c098", 8530 => x"9c0883f3", 8531 => x"d4085580", @@ -7653,7 +7653,7 @@ shared variable ram : ram_type := 8615 => x"f3d40855", 8616 => x"56fe0b81", 8617 => x"1534800b", - 8618 => x"86f080e8", + 8618 => x"879080e8", 8619 => x"3487c098", 8620 => x"9c0883f3", 8621 => x"d4085580", @@ -7707,8 +7707,8 @@ shared variable ram : ram_type := 8669 => x"850b83f3", 8670 => x"d4085656", 8671 => x"fe0b8116", - 8672 => x"34800b86", - 8673 => x"f080e834", + 8672 => x"34800b87", + 8673 => x"9080e834", 8674 => x"87c0989c", 8675 => x"0883f3d4", 8676 => x"085680ce", @@ -16010,11 +16010,11 @@ shared variable ram : ram_type := 16972 => x"7a4f5300", 16973 => x"2a2a2025", 16974 => x"73202800", - 16975 => x"31372f30", - 16976 => x"342f3230", + 16975 => x"31312f30", + 16976 => x"352f3230", 16977 => x"32310000", - 16978 => x"76312e32", - 16979 => x"00000000", + 16978 => x"76312e33", + 16979 => x"62000000", 16980 => x"205a5055", 16981 => x"2c207265", 16982 => x"76202530", diff --git a/rtl/TZSW_DualPort3264BootBRAM.vhd b/rtl/TZSW_DualPort3264BootBRAM.vhd index c5ffd3c..a16adba 100644 --- a/rtl/TZSW_DualPort3264BootBRAM.vhd +++ b/rtl/TZSW_DualPort3264BootBRAM.vhd @@ -2233,7 +2233,7 @@ architecture arch of DualPort3264BootBRAM is 2152 => x"76", 2153 => x"fb", 2154 => x"56", - 2155 => x"ee", + 2155 => x"8e", 2156 => x"87", 2157 => x"34", 2158 => x"75", @@ -3390,7 +3390,7 @@ architecture arch of DualPort3264BootBRAM is 3309 => x"83", 3310 => x"34", 3311 => x"56", - 3312 => x"86", + 3312 => x"87", 3313 => x"9c", 3314 => x"ce", 3315 => x"08", @@ -7543,7 +7543,7 @@ architecture arch of DualPort3264BootBRAM is 7462 => x"00", 7463 => x"00", 7464 => x"30", - 7465 => x"32", + 7465 => x"33", 7466 => x"55", 7467 => x"30", 7468 => x"25", @@ -11351,11 +11351,11 @@ architecture arch of DualPort3264BootBRAM is 2152 => x"38", 2153 => x"38", 2154 => x"29", - 2155 => x"86", + 2155 => x"87", 2156 => x"34", 2157 => x"73", 2158 => x"f4", - 2159 => x"ee", + 2159 => x"8e", 2160 => x"76", 2161 => x"74", 2162 => x"34", @@ -12246,7 +12246,7 @@ architecture arch of DualPort3264BootBRAM is 3047 => x"70", 3048 => x"33", 3049 => x"83", - 3050 => x"ee", + 3050 => x"8e", 3051 => x"98", 3052 => x"56", 3053 => x"80", @@ -20473,7 +20473,7 @@ architecture arch of DualPort3264BootBRAM is 2156 => x"73", 2157 => x"81", 2158 => x"80", - 2159 => x"86", + 2159 => x"87", 2160 => x"80", 2161 => x"8a", 2162 => x"75", @@ -21364,10 +21364,10 @@ architecture arch of DualPort3264BootBRAM is 3047 => x"05", 3048 => x"cd", 3049 => x"2e", - 3050 => x"86", + 3050 => x"87", 3051 => x"c0", 3052 => x"08", - 3053 => x"ee", + 3053 => x"8e", 3054 => x"f8", 3055 => x"06", 3056 => x"38", @@ -21554,7 +21554,7 @@ architecture arch of DualPort3264BootBRAM is 3237 => x"f3", 3238 => x"85", 3239 => x"fe", - 3240 => x"f0", + 3240 => x"90", 3241 => x"08", 3242 => x"90", 3243 => x"52", @@ -21599,7 +21599,7 @@ architecture arch of DualPort3264BootBRAM is 3282 => x"f3", 3283 => x"85", 3284 => x"fe", - 3285 => x"f0", + 3285 => x"90", 3286 => x"08", 3287 => x"90", 3288 => x"52", @@ -30485,7 +30485,7 @@ architecture arch of DualPort3264BootBRAM is 3050 => x"73", 3051 => x"87", 3052 => x"88", - 3053 => x"86", + 3053 => x"87", 3054 => x"f4", 3055 => x"ff", 3056 => x"cf", @@ -30637,7 +30637,7 @@ architecture arch of DualPort3264BootBRAM is 3202 => x"f3", 3203 => x"85", 3204 => x"fe", - 3205 => x"f0", + 3205 => x"90", 3206 => x"08", 3207 => x"90", 3208 => x"52", @@ -30672,7 +30672,7 @@ architecture arch of DualPort3264BootBRAM is 3237 => x"83", 3238 => x"34", 3239 => x"56", - 3240 => x"86", + 3240 => x"87", 3241 => x"9c", 3242 => x"ce", 3243 => x"08", @@ -30717,7 +30717,7 @@ architecture arch of DualPort3264BootBRAM is 3282 => x"83", 3283 => x"34", 3284 => x"56", - 3285 => x"86", + 3285 => x"87", 3286 => x"9c", 3287 => x"ce", 3288 => x"08", @@ -34896,7 +34896,7 @@ architecture arch of DualPort3264BootBRAM is 7461 => x"20", 7462 => x"7a", 7463 => x"73", - 7464 => x"34", + 7464 => x"35", 7465 => x"76", 7466 => x"20", 7467 => x"76", @@ -39754,7 +39754,7 @@ architecture arch of DualPort3264BootBRAM is 3201 => x"83", 3202 => x"34", 3203 => x"56", - 3204 => x"86", + 3204 => x"87", 3205 => x"9c", 3206 => x"ce", 3207 => x"08", @@ -56943,10 +56943,10 @@ architecture arch of DualPort3264BootBRAM is 2154 => x"9a", 2155 => x"8c", 2156 => x"34", - 2157 => x"ee", + 2157 => x"8e", 2158 => x"ff", 2159 => x"56", - 2160 => x"ee", + 2160 => x"8e", 2161 => x"74", 2162 => x"83", 2163 => x"e0", @@ -62249,7 +62249,7 @@ architecture arch of DualPort3264BootBRAM is 7460 => x"20", 7461 => x"00", 7462 => x"2a", - 7463 => x"37", + 7463 => x"31", 7464 => x"31", 7465 => x"00", 7466 => x"20", @@ -66061,10 +66061,10 @@ architecture arch of DualPort3264BootBRAM is 2154 => x"fe", 2155 => x"80", 2156 => x"73", - 2157 => x"86", + 2157 => x"87", 2158 => x"34", 2159 => x"98", - 2160 => x"86", + 2160 => x"87", 2161 => x"80", 2162 => x"52", 2163 => x"87", @@ -67216,7 +67216,7 @@ architecture arch of DualPort3264BootBRAM is 3309 => x"f3", 3310 => x"85", 3311 => x"fe", - 3312 => x"f0", + 3312 => x"90", 3313 => x"08", 3314 => x"90", 3315 => x"52", @@ -71369,7 +71369,7 @@ architecture arch of DualPort3264BootBRAM is 7462 => x"2a", 7463 => x"31", 7464 => x"32", - 7465 => x"00", + 7465 => x"62", 7466 => x"2c", 7467 => x"32", 7468 => x"73", diff --git a/rtl/TZSW_DualPortBootBRAM.vhd b/rtl/TZSW_DualPortBootBRAM.vhd index 8d9a28c..a34696b 100644 --- a/rtl/TZSW_DualPortBootBRAM.vhd +++ b/rtl/TZSW_DualPortBootBRAM.vhd @@ -4378,7 +4378,7 @@ architecture arch of DualPortBootBRAM is 4307 => x"78", 4308 => x"56", 4309 => x"fb", - 4310 => x"ee", + 4310 => x"8e", 4311 => x"ff", 4312 => x"87", 4313 => x"73", @@ -6477,7 +6477,7 @@ architecture arch of DualPortBootBRAM is 6406 => x"f3", 6407 => x"56", 6408 => x"15", - 6409 => x"86", + 6409 => x"87", 6410 => x"34", 6411 => x"9c", 6412 => x"d4", @@ -6692,7 +6692,7 @@ architecture arch of DualPortBootBRAM is 6621 => x"f3", 6622 => x"56", 6623 => x"16", - 6624 => x"86", + 6624 => x"87", 6625 => x"34", 6626 => x"9c", 6627 => x"d4", @@ -14998,7 +14998,7 @@ architecture arch of DualPortBootBRAM is 14927 => x"30", 14928 => x"30", 14929 => x"00", - 14930 => x"32", + 14930 => x"33", 14931 => x"00", 14932 => x"55", 14933 => x"65", @@ -22609,7 +22609,7 @@ architecture arch of DualPortBootBRAM is 4307 => x"74", 4308 => x"29", 4309 => x"39", - 4310 => x"86", + 4310 => x"87", 4311 => x"53", 4312 => x"34", 4313 => x"85", @@ -22617,7 +22617,7 @@ architecture arch of DualPortBootBRAM is 4315 => x"80", 4316 => x"f4", 4317 => x"b0", - 4318 => x"ee", + 4318 => x"8e", 4319 => x"80", 4320 => x"76", 4321 => x"80", @@ -24399,7 +24399,7 @@ architecture arch of DualPortBootBRAM is 6097 => x"58", 6098 => x"83", 6099 => x"f0", - 6100 => x"ee", + 6100 => x"8e", 6101 => x"80", 6102 => x"98", 6103 => x"c0", @@ -40845,13 +40845,13 @@ architecture arch of DualPortBootBRAM is 4312 => x"73", 4313 => x"34", 4314 => x"81", - 4315 => x"ee", + 4315 => x"8e", 4316 => x"80", 4317 => x"ff", - 4318 => x"86", + 4318 => x"87", 4319 => x"56", 4320 => x"80", - 4321 => x"ee", + 4321 => x"8e", 4322 => x"8a", 4323 => x"74", 4324 => x"75", @@ -42630,13 +42630,13 @@ architecture arch of DualPortBootBRAM is 6097 => x"55", 6098 => x"2e", 6099 => x"81", - 6100 => x"86", + 6100 => x"87", 6101 => x"34", 6102 => x"c0", 6103 => x"87", 6104 => x"08", 6105 => x"2e", - 6106 => x"ee", + 6106 => x"8e", 6107 => x"57", 6108 => x"f8", 6109 => x"14", @@ -43010,7 +43010,7 @@ architecture arch of DualPortBootBRAM is 6477 => x"d4", 6478 => x"fe", 6479 => x"34", - 6480 => x"f0", + 6480 => x"90", 6481 => x"87", 6482 => x"08", 6483 => x"08", @@ -43100,7 +43100,7 @@ architecture arch of DualPortBootBRAM is 6567 => x"d4", 6568 => x"fe", 6569 => x"34", - 6570 => x"f0", + 6570 => x"90", 6571 => x"87", 6572 => x"08", 6573 => x"08", @@ -51457,7 +51457,7 @@ architecture arch of DualPortBootBRAM is 14924 => x"4f", 14925 => x"2a", 14926 => x"20", - 14927 => x"37", + 14927 => x"31", 14928 => x"2f", 14929 => x"31", 14930 => x"31", @@ -59076,13 +59076,13 @@ architecture arch of DualPortBootBRAM is 4312 => x"8a", 4313 => x"73", 4314 => x"34", - 4315 => x"86", + 4315 => x"87", 4316 => x"55", 4317 => x"34", 4318 => x"34", 4319 => x"98", 4320 => x"34", - 4321 => x"86", + 4321 => x"87", 4322 => x"54", 4323 => x"80", 4324 => x"80", @@ -60867,7 +60867,7 @@ architecture arch of DualPortBootBRAM is 6103 => x"0c", 6104 => x"88", 6105 => x"80", - 6106 => x"86", + 6106 => x"87", 6107 => x"08", 6108 => x"f4", 6109 => x"81", @@ -61171,7 +61171,7 @@ architecture arch of DualPortBootBRAM is 6407 => x"d4", 6408 => x"fe", 6409 => x"34", - 6410 => x"f0", + 6410 => x"90", 6411 => x"87", 6412 => x"08", 6413 => x"08", @@ -61241,7 +61241,7 @@ architecture arch of DualPortBootBRAM is 6477 => x"f3", 6478 => x"56", 6479 => x"15", - 6480 => x"86", + 6480 => x"87", 6481 => x"34", 6482 => x"9c", 6483 => x"d4", @@ -61331,7 +61331,7 @@ architecture arch of DualPortBootBRAM is 6567 => x"f3", 6568 => x"56", 6569 => x"15", - 6570 => x"86", + 6570 => x"87", 6571 => x"34", 6572 => x"9c", 6573 => x"d4", @@ -61386,7 +61386,7 @@ architecture arch of DualPortBootBRAM is 6622 => x"d4", 6623 => x"fe", 6624 => x"34", - 6625 => x"f0", + 6625 => x"90", 6626 => x"87", 6627 => x"08", 6628 => x"08", @@ -69689,10 +69689,10 @@ architecture arch of DualPortBootBRAM is 14925 => x"2a", 14926 => x"73", 14927 => x"31", - 14928 => x"34", + 14928 => x"35", 14929 => x"32", 14930 => x"76", - 14931 => x"00", + 14931 => x"62", 14932 => x"20", 14933 => x"2c", 14934 => x"76", diff --git a/rtl/TZSW_SinglePortBootBRAM.vhd b/rtl/TZSW_SinglePortBootBRAM.vhd index e7cbadf..58d9c81 100644 --- a/rtl/TZSW_SinglePortBootBRAM.vhd +++ b/rtl/TZSW_SinglePortBootBRAM.vhd @@ -4373,7 +4373,7 @@ architecture arch of SinglePortBootBRAM is 4307 => x"78", 4308 => x"56", 4309 => x"fb", - 4310 => x"ee", + 4310 => x"8e", 4311 => x"ff", 4312 => x"87", 4313 => x"73", @@ -6472,7 +6472,7 @@ architecture arch of SinglePortBootBRAM is 6406 => x"f3", 6407 => x"56", 6408 => x"15", - 6409 => x"86", + 6409 => x"87", 6410 => x"34", 6411 => x"9c", 6412 => x"d4", @@ -6687,7 +6687,7 @@ architecture arch of SinglePortBootBRAM is 6621 => x"f3", 6622 => x"56", 6623 => x"16", - 6624 => x"86", + 6624 => x"87", 6625 => x"34", 6626 => x"9c", 6627 => x"d4", @@ -14993,7 +14993,7 @@ architecture arch of SinglePortBootBRAM is 14927 => x"30", 14928 => x"30", 14929 => x"00", - 14930 => x"32", + 14930 => x"33", 14931 => x"00", 14932 => x"55", 14933 => x"65", @@ -22604,7 +22604,7 @@ architecture arch of SinglePortBootBRAM is 4307 => x"74", 4308 => x"29", 4309 => x"39", - 4310 => x"86", + 4310 => x"87", 4311 => x"53", 4312 => x"34", 4313 => x"85", @@ -22612,7 +22612,7 @@ architecture arch of SinglePortBootBRAM is 4315 => x"80", 4316 => x"f4", 4317 => x"b0", - 4318 => x"ee", + 4318 => x"8e", 4319 => x"80", 4320 => x"76", 4321 => x"80", @@ -24394,7 +24394,7 @@ architecture arch of SinglePortBootBRAM is 6097 => x"58", 6098 => x"83", 6099 => x"f0", - 6100 => x"ee", + 6100 => x"8e", 6101 => x"80", 6102 => x"98", 6103 => x"c0", @@ -40840,13 +40840,13 @@ architecture arch of SinglePortBootBRAM is 4312 => x"73", 4313 => x"34", 4314 => x"81", - 4315 => x"ee", + 4315 => x"8e", 4316 => x"80", 4317 => x"ff", - 4318 => x"86", + 4318 => x"87", 4319 => x"56", 4320 => x"80", - 4321 => x"ee", + 4321 => x"8e", 4322 => x"8a", 4323 => x"74", 4324 => x"75", @@ -42625,13 +42625,13 @@ architecture arch of SinglePortBootBRAM is 6097 => x"55", 6098 => x"2e", 6099 => x"81", - 6100 => x"86", + 6100 => x"87", 6101 => x"34", 6102 => x"c0", 6103 => x"87", 6104 => x"08", 6105 => x"2e", - 6106 => x"ee", + 6106 => x"8e", 6107 => x"57", 6108 => x"f8", 6109 => x"14", @@ -43005,7 +43005,7 @@ architecture arch of SinglePortBootBRAM is 6477 => x"d4", 6478 => x"fe", 6479 => x"34", - 6480 => x"f0", + 6480 => x"90", 6481 => x"87", 6482 => x"08", 6483 => x"08", @@ -43095,7 +43095,7 @@ architecture arch of SinglePortBootBRAM is 6567 => x"d4", 6568 => x"fe", 6569 => x"34", - 6570 => x"f0", + 6570 => x"90", 6571 => x"87", 6572 => x"08", 6573 => x"08", @@ -51452,7 +51452,7 @@ architecture arch of SinglePortBootBRAM is 14924 => x"4f", 14925 => x"2a", 14926 => x"20", - 14927 => x"37", + 14927 => x"31", 14928 => x"2f", 14929 => x"31", 14930 => x"31", @@ -59071,13 +59071,13 @@ architecture arch of SinglePortBootBRAM is 4312 => x"8a", 4313 => x"73", 4314 => x"34", - 4315 => x"86", + 4315 => x"87", 4316 => x"55", 4317 => x"34", 4318 => x"34", 4319 => x"98", 4320 => x"34", - 4321 => x"86", + 4321 => x"87", 4322 => x"54", 4323 => x"80", 4324 => x"80", @@ -60862,7 +60862,7 @@ architecture arch of SinglePortBootBRAM is 6103 => x"0c", 6104 => x"88", 6105 => x"80", - 6106 => x"86", + 6106 => x"87", 6107 => x"08", 6108 => x"f4", 6109 => x"81", @@ -61166,7 +61166,7 @@ architecture arch of SinglePortBootBRAM is 6407 => x"d4", 6408 => x"fe", 6409 => x"34", - 6410 => x"f0", + 6410 => x"90", 6411 => x"87", 6412 => x"08", 6413 => x"08", @@ -61236,7 +61236,7 @@ architecture arch of SinglePortBootBRAM is 6477 => x"f3", 6478 => x"56", 6479 => x"15", - 6480 => x"86", + 6480 => x"87", 6481 => x"34", 6482 => x"9c", 6483 => x"d4", @@ -61326,7 +61326,7 @@ architecture arch of SinglePortBootBRAM is 6567 => x"f3", 6568 => x"56", 6569 => x"15", - 6570 => x"86", + 6570 => x"87", 6571 => x"34", 6572 => x"9c", 6573 => x"d4", @@ -61381,7 +61381,7 @@ architecture arch of SinglePortBootBRAM is 6622 => x"d4", 6623 => x"fe", 6624 => x"34", - 6625 => x"f0", + 6625 => x"90", 6626 => x"87", 6627 => x"08", 6628 => x"08", @@ -69684,10 +69684,10 @@ architecture arch of SinglePortBootBRAM is 14925 => x"2a", 14926 => x"73", 14927 => x"31", - 14928 => x"34", + 14928 => x"35", 14929 => x"32", 14930 => x"76", - 14931 => x"00", + 14931 => x"62", 14932 => x"20", 14933 => x"2c", 14934 => x"76", diff --git a/rtl/zOS_BootROM.vhd b/rtl/zOS_BootROM.vhd index 78c667d..afd977b 100644 --- a/rtl/zOS_BootROM.vhd +++ b/rtl/zOS_BootROM.vhd @@ -4372,18 +4372,18 @@ shared variable ram : ram_type := 4307 => x"f2397478", 4308 => x"317b2956", 4309 => x"fe9a39fb", - 4310 => x"3d0d86ee", + 4310 => x"3d0d878e", 4311 => x"808c53ff", 4312 => x"8a733487", 4313 => x"73348573", 4314 => x"34817334", - 4315 => x"86ee809c", + 4315 => x"878e809c", 4316 => x"5580f475", 4317 => x"34ffb075", - 4318 => x"3486ee80", + 4318 => x"34878e80", 4319 => x"98568076", 4320 => x"34807634", - 4321 => x"86ee8094", + 4321 => x"878e8094", 4322 => x"548a7434", 4323 => x"807434ff", 4324 => x"80753481", @@ -6162,13 +6162,13 @@ shared variable ram : ram_type := 6097 => x"59555874", 6098 => x"812e838c", 6099 => x"3881f054", - 6100 => x"7386ee80", + 6100 => x"73878e80", 6101 => x"8034800b", 6102 => x"87c09888", 6103 => x"0c87c098", 6104 => x"88085675", 6105 => x"802ef638", - 6106 => x"86ee8084", + 6106 => x"878e8084", 6107 => x"08577683", 6108 => x"f4f81534", 6109 => x"81147081", @@ -6471,8 +6471,8 @@ shared variable ram : ram_type := 6406 => x"850b83f3", 6407 => x"d4085556", 6408 => x"fe0b8115", - 6409 => x"34800b86", - 6410 => x"f080e834", + 6409 => x"34800b87", + 6410 => x"9080e834", 6411 => x"87c0989c", 6412 => x"0883f3d4", 6413 => x"085580ce", @@ -6542,7 +6542,7 @@ shared variable ram : ram_type := 6477 => x"f3d40855", 6478 => x"56fe0b81", 6479 => x"1534800b", - 6480 => x"86f080e8", + 6480 => x"879080e8", 6481 => x"3487c098", 6482 => x"9c0883f3", 6483 => x"d4085580", @@ -6632,7 +6632,7 @@ shared variable ram : ram_type := 6567 => x"f3d40855", 6568 => x"56fe0b81", 6569 => x"1534800b", - 6570 => x"86f080e8", + 6570 => x"879080e8", 6571 => x"3487c098", 6572 => x"9c0883f3", 6573 => x"d4085580", @@ -6686,8 +6686,8 @@ shared variable ram : ram_type := 6621 => x"850b83f3", 6622 => x"d4085656", 6623 => x"fe0b8116", - 6624 => x"34800b86", - 6625 => x"f080e834", + 6624 => x"34800b87", + 6625 => x"9080e834", 6626 => x"87c0989c", 6627 => x"0883f3d4", 6628 => x"085680ce", @@ -14989,11 +14989,11 @@ shared variable ram : ram_type := 14924 => x"7a4f5300", 14925 => x"2a2a2025", 14926 => x"73202800", - 14927 => x"31372f30", - 14928 => x"342f3230", + 14927 => x"31312f30", + 14928 => x"352f3230", 14929 => x"32310000", - 14930 => x"76312e32", - 14931 => x"00000000", + 14930 => x"76312e33", + 14931 => x"62000000", 14932 => x"205a5055", 14933 => x"2c207265", 14934 => x"76202530", diff --git a/rtl/zOS_DualPort3264BootBRAM.vhd b/rtl/zOS_DualPort3264BootBRAM.vhd index 60acf42..000add3 100644 --- a/rtl/zOS_DualPort3264BootBRAM.vhd +++ b/rtl/zOS_DualPort3264BootBRAM.vhd @@ -2233,7 +2233,7 @@ architecture arch of DualPort3264BootBRAM is 2152 => x"76", 2153 => x"fb", 2154 => x"56", - 2155 => x"ee", + 2155 => x"8e", 2156 => x"87", 2157 => x"34", 2158 => x"75", @@ -3390,7 +3390,7 @@ architecture arch of DualPort3264BootBRAM is 3309 => x"83", 3310 => x"34", 3311 => x"56", - 3312 => x"86", + 3312 => x"87", 3313 => x"9c", 3314 => x"ce", 3315 => x"08", @@ -7543,7 +7543,7 @@ architecture arch of DualPort3264BootBRAM is 7462 => x"00", 7463 => x"00", 7464 => x"30", - 7465 => x"32", + 7465 => x"33", 7466 => x"55", 7467 => x"30", 7468 => x"25", @@ -11351,11 +11351,11 @@ architecture arch of DualPort3264BootBRAM is 2152 => x"38", 2153 => x"38", 2154 => x"29", - 2155 => x"86", + 2155 => x"87", 2156 => x"34", 2157 => x"73", 2158 => x"f4", - 2159 => x"ee", + 2159 => x"8e", 2160 => x"76", 2161 => x"74", 2162 => x"34", @@ -12246,7 +12246,7 @@ architecture arch of DualPort3264BootBRAM is 3047 => x"70", 3048 => x"33", 3049 => x"83", - 3050 => x"ee", + 3050 => x"8e", 3051 => x"98", 3052 => x"56", 3053 => x"80", @@ -20473,7 +20473,7 @@ architecture arch of DualPort3264BootBRAM is 2156 => x"73", 2157 => x"81", 2158 => x"80", - 2159 => x"86", + 2159 => x"87", 2160 => x"80", 2161 => x"8a", 2162 => x"75", @@ -21364,10 +21364,10 @@ architecture arch of DualPort3264BootBRAM is 3047 => x"05", 3048 => x"cd", 3049 => x"2e", - 3050 => x"86", + 3050 => x"87", 3051 => x"c0", 3052 => x"08", - 3053 => x"ee", + 3053 => x"8e", 3054 => x"f8", 3055 => x"06", 3056 => x"38", @@ -21554,7 +21554,7 @@ architecture arch of DualPort3264BootBRAM is 3237 => x"f3", 3238 => x"85", 3239 => x"fe", - 3240 => x"f0", + 3240 => x"90", 3241 => x"08", 3242 => x"90", 3243 => x"52", @@ -21599,7 +21599,7 @@ architecture arch of DualPort3264BootBRAM is 3282 => x"f3", 3283 => x"85", 3284 => x"fe", - 3285 => x"f0", + 3285 => x"90", 3286 => x"08", 3287 => x"90", 3288 => x"52", @@ -30485,7 +30485,7 @@ architecture arch of DualPort3264BootBRAM is 3050 => x"73", 3051 => x"87", 3052 => x"88", - 3053 => x"86", + 3053 => x"87", 3054 => x"f4", 3055 => x"ff", 3056 => x"cf", @@ -30637,7 +30637,7 @@ architecture arch of DualPort3264BootBRAM is 3202 => x"f3", 3203 => x"85", 3204 => x"fe", - 3205 => x"f0", + 3205 => x"90", 3206 => x"08", 3207 => x"90", 3208 => x"52", @@ -30672,7 +30672,7 @@ architecture arch of DualPort3264BootBRAM is 3237 => x"83", 3238 => x"34", 3239 => x"56", - 3240 => x"86", + 3240 => x"87", 3241 => x"9c", 3242 => x"ce", 3243 => x"08", @@ -30717,7 +30717,7 @@ architecture arch of DualPort3264BootBRAM is 3282 => x"83", 3283 => x"34", 3284 => x"56", - 3285 => x"86", + 3285 => x"87", 3286 => x"9c", 3287 => x"ce", 3288 => x"08", @@ -34896,7 +34896,7 @@ architecture arch of DualPort3264BootBRAM is 7461 => x"20", 7462 => x"7a", 7463 => x"73", - 7464 => x"34", + 7464 => x"35", 7465 => x"76", 7466 => x"20", 7467 => x"76", @@ -39754,7 +39754,7 @@ architecture arch of DualPort3264BootBRAM is 3201 => x"83", 3202 => x"34", 3203 => x"56", - 3204 => x"86", + 3204 => x"87", 3205 => x"9c", 3206 => x"ce", 3207 => x"08", @@ -56943,10 +56943,10 @@ architecture arch of DualPort3264BootBRAM is 2154 => x"9a", 2155 => x"8c", 2156 => x"34", - 2157 => x"ee", + 2157 => x"8e", 2158 => x"ff", 2159 => x"56", - 2160 => x"ee", + 2160 => x"8e", 2161 => x"74", 2162 => x"83", 2163 => x"e0", @@ -62249,7 +62249,7 @@ architecture arch of DualPort3264BootBRAM is 7460 => x"20", 7461 => x"00", 7462 => x"2a", - 7463 => x"37", + 7463 => x"31", 7464 => x"31", 7465 => x"00", 7466 => x"20", @@ -66061,10 +66061,10 @@ architecture arch of DualPort3264BootBRAM is 2154 => x"fe", 2155 => x"80", 2156 => x"73", - 2157 => x"86", + 2157 => x"87", 2158 => x"34", 2159 => x"98", - 2160 => x"86", + 2160 => x"87", 2161 => x"80", 2162 => x"52", 2163 => x"87", @@ -67216,7 +67216,7 @@ architecture arch of DualPort3264BootBRAM is 3309 => x"f3", 3310 => x"85", 3311 => x"fe", - 3312 => x"f0", + 3312 => x"90", 3313 => x"08", 3314 => x"90", 3315 => x"52", @@ -71369,7 +71369,7 @@ architecture arch of DualPort3264BootBRAM is 7462 => x"2a", 7463 => x"31", 7464 => x"32", - 7465 => x"00", + 7465 => x"62", 7466 => x"2c", 7467 => x"32", 7468 => x"73", diff --git a/rtl/zOS_DualPortBootBRAM.vhd b/rtl/zOS_DualPortBootBRAM.vhd index a81ba0b..62d2209 100644 --- a/rtl/zOS_DualPortBootBRAM.vhd +++ b/rtl/zOS_DualPortBootBRAM.vhd @@ -4378,7 +4378,7 @@ architecture arch of DualPortBootBRAM is 4307 => x"78", 4308 => x"56", 4309 => x"fb", - 4310 => x"ee", + 4310 => x"8e", 4311 => x"ff", 4312 => x"87", 4313 => x"73", @@ -6477,7 +6477,7 @@ architecture arch of DualPortBootBRAM is 6406 => x"f3", 6407 => x"56", 6408 => x"15", - 6409 => x"86", + 6409 => x"87", 6410 => x"34", 6411 => x"9c", 6412 => x"d4", @@ -6692,7 +6692,7 @@ architecture arch of DualPortBootBRAM is 6621 => x"f3", 6622 => x"56", 6623 => x"16", - 6624 => x"86", + 6624 => x"87", 6625 => x"34", 6626 => x"9c", 6627 => x"d4", @@ -14998,7 +14998,7 @@ architecture arch of DualPortBootBRAM is 14927 => x"30", 14928 => x"30", 14929 => x"00", - 14930 => x"32", + 14930 => x"33", 14931 => x"00", 14932 => x"55", 14933 => x"65", @@ -22609,7 +22609,7 @@ architecture arch of DualPortBootBRAM is 4307 => x"74", 4308 => x"29", 4309 => x"39", - 4310 => x"86", + 4310 => x"87", 4311 => x"53", 4312 => x"34", 4313 => x"85", @@ -22617,7 +22617,7 @@ architecture arch of DualPortBootBRAM is 4315 => x"80", 4316 => x"f4", 4317 => x"b0", - 4318 => x"ee", + 4318 => x"8e", 4319 => x"80", 4320 => x"76", 4321 => x"80", @@ -24399,7 +24399,7 @@ architecture arch of DualPortBootBRAM is 6097 => x"58", 6098 => x"83", 6099 => x"f0", - 6100 => x"ee", + 6100 => x"8e", 6101 => x"80", 6102 => x"98", 6103 => x"c0", @@ -40845,13 +40845,13 @@ architecture arch of DualPortBootBRAM is 4312 => x"73", 4313 => x"34", 4314 => x"81", - 4315 => x"ee", + 4315 => x"8e", 4316 => x"80", 4317 => x"ff", - 4318 => x"86", + 4318 => x"87", 4319 => x"56", 4320 => x"80", - 4321 => x"ee", + 4321 => x"8e", 4322 => x"8a", 4323 => x"74", 4324 => x"75", @@ -42630,13 +42630,13 @@ architecture arch of DualPortBootBRAM is 6097 => x"55", 6098 => x"2e", 6099 => x"81", - 6100 => x"86", + 6100 => x"87", 6101 => x"34", 6102 => x"c0", 6103 => x"87", 6104 => x"08", 6105 => x"2e", - 6106 => x"ee", + 6106 => x"8e", 6107 => x"57", 6108 => x"f8", 6109 => x"14", @@ -43010,7 +43010,7 @@ architecture arch of DualPortBootBRAM is 6477 => x"d4", 6478 => x"fe", 6479 => x"34", - 6480 => x"f0", + 6480 => x"90", 6481 => x"87", 6482 => x"08", 6483 => x"08", @@ -43100,7 +43100,7 @@ architecture arch of DualPortBootBRAM is 6567 => x"d4", 6568 => x"fe", 6569 => x"34", - 6570 => x"f0", + 6570 => x"90", 6571 => x"87", 6572 => x"08", 6573 => x"08", @@ -51457,7 +51457,7 @@ architecture arch of DualPortBootBRAM is 14924 => x"4f", 14925 => x"2a", 14926 => x"20", - 14927 => x"37", + 14927 => x"31", 14928 => x"2f", 14929 => x"31", 14930 => x"31", @@ -59076,13 +59076,13 @@ architecture arch of DualPortBootBRAM is 4312 => x"8a", 4313 => x"73", 4314 => x"34", - 4315 => x"86", + 4315 => x"87", 4316 => x"55", 4317 => x"34", 4318 => x"34", 4319 => x"98", 4320 => x"34", - 4321 => x"86", + 4321 => x"87", 4322 => x"54", 4323 => x"80", 4324 => x"80", @@ -60867,7 +60867,7 @@ architecture arch of DualPortBootBRAM is 6103 => x"0c", 6104 => x"88", 6105 => x"80", - 6106 => x"86", + 6106 => x"87", 6107 => x"08", 6108 => x"f4", 6109 => x"81", @@ -61171,7 +61171,7 @@ architecture arch of DualPortBootBRAM is 6407 => x"d4", 6408 => x"fe", 6409 => x"34", - 6410 => x"f0", + 6410 => x"90", 6411 => x"87", 6412 => x"08", 6413 => x"08", @@ -61241,7 +61241,7 @@ architecture arch of DualPortBootBRAM is 6477 => x"f3", 6478 => x"56", 6479 => x"15", - 6480 => x"86", + 6480 => x"87", 6481 => x"34", 6482 => x"9c", 6483 => x"d4", @@ -61331,7 +61331,7 @@ architecture arch of DualPortBootBRAM is 6567 => x"f3", 6568 => x"56", 6569 => x"15", - 6570 => x"86", + 6570 => x"87", 6571 => x"34", 6572 => x"9c", 6573 => x"d4", @@ -61386,7 +61386,7 @@ architecture arch of DualPortBootBRAM is 6622 => x"d4", 6623 => x"fe", 6624 => x"34", - 6625 => x"f0", + 6625 => x"90", 6626 => x"87", 6627 => x"08", 6628 => x"08", @@ -69689,10 +69689,10 @@ architecture arch of DualPortBootBRAM is 14925 => x"2a", 14926 => x"73", 14927 => x"31", - 14928 => x"34", + 14928 => x"35", 14929 => x"32", 14930 => x"76", - 14931 => x"00", + 14931 => x"62", 14932 => x"20", 14933 => x"2c", 14934 => x"76", diff --git a/rtl/zOS_SinglePortBootBRAM.vhd b/rtl/zOS_SinglePortBootBRAM.vhd index 6136eae..3d77ab0 100644 --- a/rtl/zOS_SinglePortBootBRAM.vhd +++ b/rtl/zOS_SinglePortBootBRAM.vhd @@ -4373,7 +4373,7 @@ architecture arch of SinglePortBootBRAM is 4307 => x"78", 4308 => x"56", 4309 => x"fb", - 4310 => x"ee", + 4310 => x"8e", 4311 => x"ff", 4312 => x"87", 4313 => x"73", @@ -6472,7 +6472,7 @@ architecture arch of SinglePortBootBRAM is 6406 => x"f3", 6407 => x"56", 6408 => x"15", - 6409 => x"86", + 6409 => x"87", 6410 => x"34", 6411 => x"9c", 6412 => x"d4", @@ -6687,7 +6687,7 @@ architecture arch of SinglePortBootBRAM is 6621 => x"f3", 6622 => x"56", 6623 => x"16", - 6624 => x"86", + 6624 => x"87", 6625 => x"34", 6626 => x"9c", 6627 => x"d4", @@ -14993,7 +14993,7 @@ architecture arch of SinglePortBootBRAM is 14927 => x"30", 14928 => x"30", 14929 => x"00", - 14930 => x"32", + 14930 => x"33", 14931 => x"00", 14932 => x"55", 14933 => x"65", @@ -22604,7 +22604,7 @@ architecture arch of SinglePortBootBRAM is 4307 => x"74", 4308 => x"29", 4309 => x"39", - 4310 => x"86", + 4310 => x"87", 4311 => x"53", 4312 => x"34", 4313 => x"85", @@ -22612,7 +22612,7 @@ architecture arch of SinglePortBootBRAM is 4315 => x"80", 4316 => x"f4", 4317 => x"b0", - 4318 => x"ee", + 4318 => x"8e", 4319 => x"80", 4320 => x"76", 4321 => x"80", @@ -24394,7 +24394,7 @@ architecture arch of SinglePortBootBRAM is 6097 => x"58", 6098 => x"83", 6099 => x"f0", - 6100 => x"ee", + 6100 => x"8e", 6101 => x"80", 6102 => x"98", 6103 => x"c0", @@ -40840,13 +40840,13 @@ architecture arch of SinglePortBootBRAM is 4312 => x"73", 4313 => x"34", 4314 => x"81", - 4315 => x"ee", + 4315 => x"8e", 4316 => x"80", 4317 => x"ff", - 4318 => x"86", + 4318 => x"87", 4319 => x"56", 4320 => x"80", - 4321 => x"ee", + 4321 => x"8e", 4322 => x"8a", 4323 => x"74", 4324 => x"75", @@ -42625,13 +42625,13 @@ architecture arch of SinglePortBootBRAM is 6097 => x"55", 6098 => x"2e", 6099 => x"81", - 6100 => x"86", + 6100 => x"87", 6101 => x"34", 6102 => x"c0", 6103 => x"87", 6104 => x"08", 6105 => x"2e", - 6106 => x"ee", + 6106 => x"8e", 6107 => x"57", 6108 => x"f8", 6109 => x"14", @@ -43005,7 +43005,7 @@ architecture arch of SinglePortBootBRAM is 6477 => x"d4", 6478 => x"fe", 6479 => x"34", - 6480 => x"f0", + 6480 => x"90", 6481 => x"87", 6482 => x"08", 6483 => x"08", @@ -43095,7 +43095,7 @@ architecture arch of SinglePortBootBRAM is 6567 => x"d4", 6568 => x"fe", 6569 => x"34", - 6570 => x"f0", + 6570 => x"90", 6571 => x"87", 6572 => x"08", 6573 => x"08", @@ -51452,7 +51452,7 @@ architecture arch of SinglePortBootBRAM is 14924 => x"4f", 14925 => x"2a", 14926 => x"20", - 14927 => x"37", + 14927 => x"31", 14928 => x"2f", 14929 => x"31", 14930 => x"31", @@ -59071,13 +59071,13 @@ architecture arch of SinglePortBootBRAM is 4312 => x"8a", 4313 => x"73", 4314 => x"34", - 4315 => x"86", + 4315 => x"87", 4316 => x"55", 4317 => x"34", 4318 => x"34", 4319 => x"98", 4320 => x"34", - 4321 => x"86", + 4321 => x"87", 4322 => x"54", 4323 => x"80", 4324 => x"80", @@ -60862,7 +60862,7 @@ architecture arch of SinglePortBootBRAM is 6103 => x"0c", 6104 => x"88", 6105 => x"80", - 6106 => x"86", + 6106 => x"87", 6107 => x"08", 6108 => x"f4", 6109 => x"81", @@ -61166,7 +61166,7 @@ architecture arch of SinglePortBootBRAM is 6407 => x"d4", 6408 => x"fe", 6409 => x"34", - 6410 => x"f0", + 6410 => x"90", 6411 => x"87", 6412 => x"08", 6413 => x"08", @@ -61236,7 +61236,7 @@ architecture arch of SinglePortBootBRAM is 6477 => x"f3", 6478 => x"56", 6479 => x"15", - 6480 => x"86", + 6480 => x"87", 6481 => x"34", 6482 => x"9c", 6483 => x"d4", @@ -61326,7 +61326,7 @@ architecture arch of SinglePortBootBRAM is 6567 => x"f3", 6568 => x"56", 6569 => x"15", - 6570 => x"86", + 6570 => x"87", 6571 => x"34", 6572 => x"9c", 6573 => x"d4", @@ -61381,7 +61381,7 @@ architecture arch of SinglePortBootBRAM is 6622 => x"d4", 6623 => x"fe", 6624 => x"34", - 6625 => x"f0", + 6625 => x"90", 6626 => x"87", 6627 => x"08", 6628 => x"08", @@ -69684,10 +69684,10 @@ architecture arch of SinglePortBootBRAM is 14925 => x"2a", 14926 => x"73", 14927 => x"31", - 14928 => x"34", + 14928 => x"35", 14929 => x"32", 14930 => x"76", - 14931 => x"00", + 14931 => x"62", 14932 => x"20", 14933 => x"2c", 14934 => x"76", diff --git a/zOS/src/zOS.cpp b/zOS/src/zOS.cpp index 03431da..4356540 100644 --- a/zOS/src/zOS.cpp +++ b/zOS/src/zOS.cpp @@ -27,6 +27,7 @@ // Z80 direction wasnt always set correctly resulting in some strange // and hard to debug behaviour. // May 2021 - Preparations to add the M68000 architecture. +// - Updates to allow Z80 to access 1Mbyte static RAM. // // Notes: See Makefile to enable/disable conditional components // USELOADB - The Byte write command is implemented in hw/sw so use it. @@ -120,8 +121,8 @@ #endif // Version info. -#define VERSION "v1.2a" -#define VERSION_DATE "17/04/2021" +#define VERSION "v1.3b" +#define VERSION_DATE "11/05/2021" #define PROGRAM_NAME "zOS" // Utility functions.