589 lines
16 KiB
C
589 lines
16 KiB
C
/* Teensyduino Core Library
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* http://www.pjrc.com/teensy/
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* Copyright (c) 2017 PJRC.COM, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* 1. The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* 2. If the Software is incorporated into a build system that allows
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* selection among a list of target devices, then similar target
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* devices manufactured by PJRC.COM must be included in the list of
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* target devices and selectable in the same manner.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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// To configure the EEPROM size, edit E2END in avr/eeprom.h.
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//
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// Do *NOT* edit EEPROM_SIZE in this file. It will automatically
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// change based on your changes to E2END in avr/eeprom.h.
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//
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// Generally you should avoid editing this code, unless you really
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// know what you're doing.
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#include "kinetis.h"
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#include <avr/eeprom.h>
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//#include "HardwareSerial.h"
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#if F_CPU > 120000000 && defined(__MK66FX1M0__)
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#include "core_pins.h" // delayMicroseconds()
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#endif
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#if defined(__MK20DX128__) || defined(__MK20DX256__)
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#define EEPROM_MAX 2048
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#define EEPARTITION 0x03 // all 32K dataflash for EEPROM, none for Data
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#define EEESPLIT 0x30 // must be 0x30 on these chips
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#elif defined(__MK64FX512__)
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#define EEPROM_MAX 4096
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#define EEPARTITION 0x05 // all 128K dataflash for EEPROM
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#define EEESPLIT 0x10 // best endurance: 0x00 = first 12%, 0x10 = first 25%, 0x30 = all equal
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#elif defined(__MK66FX1M0__)
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#define EEPROM_MAX 4096
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#define EEPARTITION 0x05 // 128K dataflash for EEPROM, 128K for Data
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#define EEESPLIT 0x10 // best endurance: 0x00 = first 12%, 0x10 = first 25%, 0x30 = all equal
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#elif defined(__MKL26Z64__)
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#define EEPROM_MAX 255
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#endif
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#if E2END > (EEPROM_MAX-1)
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#error "E2END is set larger than the maximum possible EEPROM size"
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#endif
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#if defined(KINETISK)
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// The EEPROM is really RAM with a hardware-based backup system to
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// flash memory. Selecting a smaller size EEPROM allows more wear
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// leveling, for higher write endurance. If you edit this file,
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// set this to the smallest size your application can use. Also,
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// due to Freescale's implementation, writing 16 or 32 bit words
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// (aligned to 2 or 4 byte boundaries) has twice the endurance
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// compared to writing 8 bit bytes.
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//
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#if E2END < 32
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#define EEPROM_SIZE 32
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#define EEESIZE 0x09
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#elif E2END < 64
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#define EEPROM_SIZE 64
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#define EEESIZE 0x08
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#elif E2END < 128
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#define EEPROM_SIZE 128
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#define EEESIZE 0x07
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#elif E2END < 256
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#define EEPROM_SIZE 256
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#define EEESIZE 0x06
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#elif E2END < 512
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#define EEPROM_SIZE 512
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#define EEESIZE 0x05
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#elif E2END < 1024
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#define EEPROM_SIZE 1024
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#define EEESIZE 0x04
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#elif E2END < 2048
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#define EEPROM_SIZE 2048
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#define EEESIZE 0x03
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#elif E2END < 4096
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#define EEPROM_SIZE 4096
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#define EEESIZE 0x02
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#endif
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// Writing unaligned 16 or 32 bit data is handled automatically when
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// this is defined, but at a cost of extra code size. Without this,
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// any unaligned write will cause a hard fault exception! If you're
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// absolutely sure all 16 and 32 bit writes will be aligned, you can
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// remove the extra unnecessary code.
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//
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#define HANDLE_UNALIGNED_WRITES
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void eeprom_initialize(void)
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{
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uint32_t count=0;
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uint16_t do_flash_cmd[] = {
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0xf06f, 0x037f, 0x7003, 0x7803,
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0xf013, 0x0f80, 0xd0fb, 0x4770};
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uint8_t status;
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if (FTFL_FCNFG & FTFL_FCNFG_RAMRDY) {
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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// FlexRAM is configured as traditional RAM
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// We need to reconfigure for EEPROM usage
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kinetis_hsrun_disable();
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FTFL_FCCOB0 = 0x80; // PGMPART = Program Partition Command
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FTFL_FCCOB3 = 0;
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FTFL_FCCOB4 = EEESPLIT | EEESIZE;
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FTFL_FCCOB5 = EEPARTITION;
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__disable_irq();
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// do_flash_cmd() must execute from RAM. Luckily the C syntax is simple...
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(*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&FTFL_FSTAT);
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__enable_irq();
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kinetis_hsrun_enable();
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status = FTFL_FSTAT;
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if (status & 0x70) {
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FTFL_FSTAT = (status & 0x70);
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return; // error
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}
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}
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// wait for eeprom to become ready (is this really necessary?)
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while (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) {
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if (++count > 200000) break;
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}
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}
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#define FlexRAM ((volatile uint8_t *)0x14000000)
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uint8_t eeprom_read_byte(const uint8_t *addr)
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{
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE) return 0;
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if (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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return FlexRAM[offset];
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}
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uint16_t eeprom_read_word(const uint16_t *addr)
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{
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE-1) return 0;
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if (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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return *(uint16_t *)(&FlexRAM[offset]);
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}
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uint32_t eeprom_read_dword(const uint32_t *addr)
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{
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE-3) return 0;
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if (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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return *(uint32_t *)(&FlexRAM[offset]);
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}
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void eeprom_read_block(void *buf, const void *addr, uint32_t len)
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{
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uint32_t offset = (uint32_t)addr;
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uint8_t *dest = (uint8_t *)buf;
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uint32_t end = offset + len;
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if (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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if (end > EEPROM_SIZE) end = EEPROM_SIZE;
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while (offset < end) {
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*dest++ = FlexRAM[offset++];
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}
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}
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int eeprom_is_ready(void)
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{
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return (FTFL_FCNFG & FTFL_FCNFG_EEERDY) ? 1 : 0;
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}
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static void flexram_wait(void)
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{
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while (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) {
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// TODO: timeout
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}
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}
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void eeprom_write_byte(uint8_t *addr, uint8_t value)
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{
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE) return;
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if (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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if (FlexRAM[offset] != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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FlexRAM[offset] = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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}
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void eeprom_write_word(uint16_t *addr, uint16_t value)
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{
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE-1) return;
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if (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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#ifdef HANDLE_UNALIGNED_WRITES
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if ((offset & 1) == 0) {
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#endif
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if (*(uint16_t *)(&FlexRAM[offset]) != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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*(uint16_t *)(&FlexRAM[offset]) = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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#ifdef HANDLE_UNALIGNED_WRITES
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} else {
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if (FlexRAM[offset] != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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FlexRAM[offset] = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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if (FlexRAM[offset + 1] != (value >> 8)) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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FlexRAM[offset + 1] = value >> 8;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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}
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#endif
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}
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void eeprom_write_dword(uint32_t *addr, uint32_t value)
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{
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE-3) return;
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if (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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#ifdef HANDLE_UNALIGNED_WRITES
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switch (offset & 3) {
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case 0:
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#endif
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if (*(uint32_t *)(&FlexRAM[offset]) != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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*(uint32_t *)(&FlexRAM[offset]) = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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return;
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#ifdef HANDLE_UNALIGNED_WRITES
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case 2:
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if (*(uint16_t *)(&FlexRAM[offset]) != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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*(uint16_t *)(&FlexRAM[offset]) = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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if (*(uint16_t *)(&FlexRAM[offset + 2]) != (value >> 16)) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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*(uint16_t *)(&FlexRAM[offset + 2]) = value >> 16;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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return;
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default:
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if (FlexRAM[offset] != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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FlexRAM[offset] = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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if (*(uint16_t *)(&FlexRAM[offset + 1]) != (value >> 8)) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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*(uint16_t *)(&FlexRAM[offset + 1]) = value >> 8;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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if (FlexRAM[offset + 3] != (value >> 24)) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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FlexRAM[offset + 3] = value >> 24;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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}
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#endif
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}
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void eeprom_write_block(const void *buf, void *addr, uint32_t len)
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{
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uint32_t offset = (uint32_t)addr;
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const uint8_t *src = (const uint8_t *)buf;
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if (offset >= EEPROM_SIZE) return;
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if (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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if (len >= EEPROM_SIZE) len = EEPROM_SIZE;
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if (offset + len >= EEPROM_SIZE) len = EEPROM_SIZE - offset;
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while (len > 0) {
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uint32_t lsb = offset & 3;
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if (lsb == 0 && len >= 4) {
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// write aligned 32 bits
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uint32_t val32;
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val32 = *src++;
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val32 |= (*src++ << 8);
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val32 |= (*src++ << 16);
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val32 |= (*src++ << 24);
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if (*(uint32_t *)(&FlexRAM[offset]) != val32) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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*(uint32_t *)(&FlexRAM[offset]) = val32;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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offset += 4;
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len -= 4;
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} else if ((lsb == 0 || lsb == 2) && len >= 2) {
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// write aligned 16 bits
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uint16_t val16;
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val16 = *src++;
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val16 |= (*src++ << 8);
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if (*(uint16_t *)(&FlexRAM[offset]) != val16) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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*(uint16_t *)(&FlexRAM[offset]) = val16;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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offset += 2;
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len -= 2;
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} else {
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// write 8 bits
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uint8_t val8 = *src++;
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if (FlexRAM[offset] != val8) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL_FSTAT & 0x70;
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if (stat) FTFL_FSTAT = stat;
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FlexRAM[offset] = val8;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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offset++;
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len--;
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}
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}
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}
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/*
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void do_flash_cmd(volatile uint8_t *fstat)
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{
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*fstat = 0x80;
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while ((*fstat & 0x80) == 0) ; // wait
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}
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00000000 <do_flash_cmd>:
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0: f06f 037f mvn.w r3, #127 ; 0x7f
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4: 7003 strb r3, [r0, #0]
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6: 7803 ldrb r3, [r0, #0]
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8: f013 0f80 tst.w r3, #128 ; 0x80
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c: d0fb beq.n 6 <do_flash_cmd+0x6>
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e: 4770 bx lr
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*/
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#elif defined(KINETISL)
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#define EEPROM_SIZE (E2END+1)
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#define FLASH_BEGIN (uint16_t *)63488
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#define FLASH_END (uint16_t *)65536
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static uint16_t flashend = 0;
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void eeprom_initialize(void)
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{
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const uint16_t *p = FLASH_BEGIN;
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do {
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if (*p++ == 0xFFFF) {
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flashend = (uint32_t)(p - 2);
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return;
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}
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} while (p < FLASH_END);
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flashend = (uint32_t)(FLASH_END - 1);
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}
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uint8_t eeprom_read_byte(const uint8_t *addr)
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{
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uint32_t offset = (uint32_t)addr;
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const uint16_t *p = FLASH_BEGIN;
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const uint16_t *end = (const uint16_t *)((uint32_t)flashend);
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uint16_t val;
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uint8_t data=0xFF;
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if (!end) {
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eeprom_initialize();
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end = (const uint16_t *)((uint32_t)flashend);
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}
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if (offset < EEPROM_SIZE) {
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while (p <= end) {
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val = *p++;
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if ((val & 255) == offset) data = val >> 8;
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}
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}
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return data;
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}
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static void flash_write(const uint16_t *code, uint32_t addr, uint32_t data)
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{
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// with great power comes great responsibility....
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uint32_t stat;
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*(uint32_t *)&FTFL_FCCOB3 = 0x06000000 | (addr & 0x00FFFFFC);
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*(uint32_t *)&FTFL_FCCOB7 = data;
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__disable_irq();
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(*((void (*)(volatile uint8_t *))((uint32_t)code | 1)))(&FTFL_FSTAT);
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__enable_irq();
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stat = FTFL_FSTAT & 0x70;
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if (stat) {
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FTFL_FSTAT = stat;
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}
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MCM_PLACR |= MCM_PLACR_CFCC;
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}
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void eeprom_write_byte(uint8_t *addr, uint8_t data)
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{
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uint32_t offset = (uint32_t)addr;
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const uint16_t *p, *end = (const uint16_t *)((uint32_t)flashend);
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uint32_t i, val, flashaddr;
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uint16_t do_flash_cmd[] = {
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0x2380, 0x7003, 0x7803, 0xb25b, 0x2b00, 0xdafb, 0x4770};
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uint8_t buf[EEPROM_SIZE];
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if (offset >= EEPROM_SIZE) return;
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if (!end) {
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eeprom_initialize();
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end = (const uint16_t *)((uint32_t)flashend);
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}
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if (++end < FLASH_END) {
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val = (data << 8) | offset;
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flashaddr = (uint32_t)end;
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flashend = flashaddr;
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if ((flashaddr & 2) == 0) {
|
|
val |= 0xFFFF0000;
|
|
} else {
|
|
val <<= 16;
|
|
val |= 0x0000FFFF;
|
|
}
|
|
flash_write(do_flash_cmd, flashaddr, val);
|
|
} else {
|
|
for (i=0; i < EEPROM_SIZE; i++) {
|
|
buf[i] = 0xFF;
|
|
}
|
|
for (p = FLASH_BEGIN; p < FLASH_END; p++) {
|
|
val = *p;
|
|
if ((val & 255) < EEPROM_SIZE) {
|
|
buf[val & 255] = val >> 8;
|
|
}
|
|
}
|
|
buf[offset] = data;
|
|
for (flashaddr=(uint32_t)FLASH_BEGIN; flashaddr < (uint32_t)FLASH_END; flashaddr += 1024) {
|
|
*(uint32_t *)&FTFL_FCCOB3 = 0x09000000 | flashaddr;
|
|
__disable_irq();
|
|
(*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&FTFL_FSTAT);
|
|
__enable_irq();
|
|
val = FTFL_FSTAT & 0x70;
|
|
if (val) FTFL_FSTAT = val;
|
|
MCM_PLACR |= MCM_PLACR_CFCC;
|
|
}
|
|
flashaddr=(uint32_t)FLASH_BEGIN;
|
|
for (i=0; i < EEPROM_SIZE; i++) {
|
|
if (buf[i] == 0xFF) continue;
|
|
if ((flashaddr & 2) == 0) {
|
|
val = (buf[i] << 8) | i;
|
|
} else {
|
|
val = val | (buf[i] << 24) | (i << 16);
|
|
flash_write(do_flash_cmd, flashaddr, val);
|
|
}
|
|
flashaddr += 2;
|
|
}
|
|
flashend = flashaddr;
|
|
if ((flashaddr & 2)) {
|
|
val |= 0xFFFF0000;
|
|
flash_write(do_flash_cmd, flashaddr, val);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
void do_flash_cmd(volatile uint8_t *fstat)
|
|
{
|
|
*fstat = 0x80;
|
|
while ((*fstat & 0x80) == 0) ; // wait
|
|
}
|
|
00000000 <do_flash_cmd>:
|
|
0: 2380 movs r3, #128 ; 0x80
|
|
2: 7003 strb r3, [r0, #0]
|
|
4: 7803 ldrb r3, [r0, #0]
|
|
6: b25b sxtb r3, r3
|
|
8: 2b00 cmp r3, #0
|
|
a: dafb bge.n 4 <do_flash_cmd+0x4>
|
|
c: 4770 bx lr
|
|
*/
|
|
|
|
|
|
uint16_t eeprom_read_word(const uint16_t *addr)
|
|
{
|
|
const uint8_t *p = (const uint8_t *)addr;
|
|
return eeprom_read_byte(p) | (eeprom_read_byte(p+1) << 8);
|
|
}
|
|
|
|
uint32_t eeprom_read_dword(const uint32_t *addr)
|
|
{
|
|
const uint8_t *p = (const uint8_t *)addr;
|
|
return eeprom_read_byte(p) | (eeprom_read_byte(p+1) << 8)
|
|
| (eeprom_read_byte(p+2) << 16) | (eeprom_read_byte(p+3) << 24);
|
|
}
|
|
|
|
void eeprom_read_block(void *buf, const void *addr, uint32_t len)
|
|
{
|
|
const uint8_t *p = (const uint8_t *)addr;
|
|
uint8_t *dest = (uint8_t *)buf;
|
|
while (len--) {
|
|
*dest++ = eeprom_read_byte(p++);
|
|
}
|
|
}
|
|
|
|
int eeprom_is_ready(void)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
void eeprom_write_word(uint16_t *addr, uint16_t value)
|
|
{
|
|
uint8_t *p = (uint8_t *)addr;
|
|
eeprom_write_byte(p++, value);
|
|
eeprom_write_byte(p, value >> 8);
|
|
}
|
|
|
|
void eeprom_write_dword(uint32_t *addr, uint32_t value)
|
|
{
|
|
uint8_t *p = (uint8_t *)addr;
|
|
eeprom_write_byte(p++, value);
|
|
eeprom_write_byte(p++, value >> 8);
|
|
eeprom_write_byte(p++, value >> 16);
|
|
eeprom_write_byte(p, value >> 24);
|
|
}
|
|
|
|
void eeprom_write_block(const void *buf, void *addr, uint32_t len)
|
|
{
|
|
uint8_t *p = (uint8_t *)addr;
|
|
const uint8_t *src = (const uint8_t *)buf;
|
|
while (len--) {
|
|
eeprom_write_byte(p++, *src++);
|
|
}
|
|
}
|
|
|
|
|
|
#endif // KINETISL
|