508 lines
29 KiB
ArmAsm
508 lines
29 KiB
ArmAsm
/* ---------------------------------------------------------------------------------------*/
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/* @file: startup_MK64F12.s */
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/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
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/* MK64F12 */
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/* @version: 2.5 */
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/* @date: 2014-2-10 */
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/* @build: b140606 */
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/* ---------------------------------------------------------------------------------------*/
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/* */
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/* Copyright (c) 1997 - 2014 , Freescale Semiconductor, Inc. */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without modification, */
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/* are permitted provided that the following conditions are met: */
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/* */
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/* o Redistributions of source code must retain the above copyright notice, this list */
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/* of conditions and the following disclaimer. */
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/* */
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/* o Redistributions in binary form must reproduce the above copyright notice, this */
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/* list of conditions and the following disclaimer in the documentation and/or */
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/* other materials provided with the distribution. */
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/* */
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/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */
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/* contributors may be used to endorse or promote products derived from this */
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/* software without specific prior written permission. */
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/* */
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/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
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/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
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/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
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/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
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/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
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/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
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/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
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/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
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/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
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/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/*****************************************************************************/
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/* Version: GCC for ARM Embedded Processors */
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/*****************************************************************************/
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.syntax unified
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.arch armv7-m
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.section .isr_vector, "a"
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.align 2
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.global __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler*/
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.long HardFault_Handler /* Hard Fault Handler*/
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.long MemManage_Handler /* MPU Fault Handler*/
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.long BusFault_Handler /* Bus Fault Handler*/
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.long UsageFault_Handler /* Usage Fault Handler*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long SVC_Handler /* SVCall Handler*/
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.long DebugMon_Handler /* Debug Monitor Handler*/
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.long 0 /* Reserved*/
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.long PendSV_Handler /* PendSV Handler*/
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.long SysTick_Handler /* SysTick Handler*/
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/* External Interrupts*/
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.long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/
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.long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/
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.long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/
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.long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/
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.long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/
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.long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/
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.long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/
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.long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/
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.long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/
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.long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/
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.long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/
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.long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/
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.long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/
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.long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/
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.long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/
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.long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/
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.long DMA_Error_IRQHandler /* DMA Error Interrupt*/
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.long MCM_IRQHandler /* Normal Interrupt*/
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.long FTFE_IRQHandler /* FTFE Command complete interrupt*/
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.long Read_Collision_IRQHandler /* Read Collision Interrupt*/
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.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/
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.long LLW_IRQHandler /* Low Leakage Wakeup*/
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.long Watchdog_IRQHandler /* WDOG Interrupt*/
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.long RNG_IRQHandler /* RNG Interrupt*/
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.long I2C0_IRQHandler /* I2C0 interrupt*/
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.long I2C1_IRQHandler /* I2C1 interrupt*/
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.long SPI0_IRQHandler /* SPI0 Interrupt*/
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.long SPI1_IRQHandler /* SPI1 Interrupt*/
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.long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/
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.long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/
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.long UART0_LON_IRQHandler /* UART0 LON interrupt*/
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.long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/
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.long UART0_ERR_IRQHandler /* UART0 Error interrupt*/
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.long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/
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.long UART1_ERR_IRQHandler /* UART1 Error interrupt*/
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.long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/
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.long UART2_ERR_IRQHandler /* UART2 Error interrupt*/
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.long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt*/
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.long UART3_ERR_IRQHandler /* UART3 Error interrupt*/
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.long ADC0_IRQHandler /* ADC0 interrupt*/
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.long CMP0_IRQHandler /* CMP0 interrupt*/
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.long CMP1_IRQHandler /* CMP1 interrupt*/
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.long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/
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.long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/
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.long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/
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.long CMT_IRQHandler /* CMT interrupt*/
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.long RTC_IRQHandler /* RTC interrupt*/
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.long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
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.long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/
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.long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/
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.long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/
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.long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/
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.long PDB0_IRQHandler /* PDB0 Interrupt*/
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.long USB0_IRQHandler /* USB0 interrupt*/
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.long USBDCD_IRQHandler /* USBDCD Interrupt*/
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.long Reserved71_IRQHandler /* Reserved interrupt 71*/
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.long DAC0_IRQHandler /* DAC0 interrupt*/
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.long MCG_IRQHandler /* MCG Interrupt*/
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.long LPTimer_IRQHandler /* LPTimer interrupt*/
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.long PORTA_IRQHandler /* Port A interrupt*/
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.long PORTB_IRQHandler /* Port B interrupt*/
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.long PORTC_IRQHandler /* Port C interrupt*/
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.long PORTD_IRQHandler /* Port D interrupt*/
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.long PORTE_IRQHandler /* Port E interrupt*/
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.long SWI_IRQHandler /* Software interrupt*/
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.long SPI2_IRQHandler /* SPI2 Interrupt*/
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.long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt*/
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.long UART4_ERR_IRQHandler /* UART4 Error interrupt*/
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.long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt*/
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.long UART5_ERR_IRQHandler /* UART5 Error interrupt*/
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.long CMP2_IRQHandler /* CMP2 interrupt*/
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.long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/
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.long DAC1_IRQHandler /* DAC1 interrupt*/
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.long ADC1_IRQHandler /* ADC1 interrupt*/
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.long I2C2_IRQHandler /* I2C2 interrupt*/
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.long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/
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.long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/
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.long CAN0_Error_IRQHandler /* CAN0 error interrupt*/
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.long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/
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.long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/
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.long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/
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.long SDHC_IRQHandler /* SDHC interrupt*/
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.long ENET_1588_Timer_IRQHandler /* Ethernet MAC IEEE 1588 Timer Interrupt*/
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.long ENET_Transmit_IRQHandler /* Ethernet MAC Transmit Interrupt*/
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.long ENET_Receive_IRQHandler /* Ethernet MAC Receive Interrupt*/
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.long ENET_Error_IRQHandler /* Ethernet MAC Error and miscelaneous Interrupt*/
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.long DefaultISR /* 102*/
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.long DefaultISR /* 103*/
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.long DefaultISR /* 104*/
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.long DefaultISR /* 105*/
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.long DefaultISR /* 106*/
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.long DefaultISR /* 107*/
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.long DefaultISR /* 108*/
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.long DefaultISR /* 109*/
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.long DefaultISR /* 110*/
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.long DefaultISR /* 111*/
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.long DefaultISR /* 112*/
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.long DefaultISR /* 113*/
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.long DefaultISR /* 114*/
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.long DefaultISR /* 115*/
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.long DefaultISR /* 116*/
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.long DefaultISR /* 117*/
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.long DefaultISR /* 118*/
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.long DefaultISR /* 119*/
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.long DefaultISR /* 120*/
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.long DefaultISR /* 121*/
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.long DefaultISR /* 122*/
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.long DefaultISR /* 123*/
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.long DefaultISR /* 124*/
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.long DefaultISR /* 125*/
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.long DefaultISR /* 126*/
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.long DefaultISR /* 127*/
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.long DefaultISR /* 128*/
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.long DefaultISR /* 129*/
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.long DefaultISR /* 130*/
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.long DefaultISR /* 131*/
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.long DefaultISR /* 132*/
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.long DefaultISR /* 133*/
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.long DefaultISR /* 134*/
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.long DefaultISR /* 135*/
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.long DefaultISR /* 136*/
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.long DefaultISR /* 137*/
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.long DefaultISR /* 138*/
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.long DefaultISR /* 139*/
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.long DefaultISR /* 140*/
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.long DefaultISR /* 141*/
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.long DefaultISR /* 142*/
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.long DefaultISR /* 143*/
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.long DefaultISR /* 144*/
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.long DefaultISR /* 145*/
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.long DefaultISR /* 146*/
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.long DefaultISR /* 147*/
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.long DefaultISR /* 148*/
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.long DefaultISR /* 149*/
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.long DefaultISR /* 150*/
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.long DefaultISR /* 151*/
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.long DefaultISR /* 152*/
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.long DefaultISR /* 153*/
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.long DefaultISR /* 154*/
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.long DefaultISR /* 155*/
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.long DefaultISR /* 156*/
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.long DefaultISR /* 157*/
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.long DefaultISR /* 158*/
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.long DefaultISR /* 159*/
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.long DefaultISR /* 160*/
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.long DefaultISR /* 161*/
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.long DefaultISR /* 162*/
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.long DefaultISR /* 163*/
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.long DefaultISR /* 164*/
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.long DefaultISR /* 165*/
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.long DefaultISR /* 166*/
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.long DefaultISR /* 167*/
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.long DefaultISR /* 168*/
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.long DefaultISR /* 169*/
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.long DefaultISR /* 170*/
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.long DefaultISR /* 171*/
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.long DefaultISR /* 172*/
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.long DefaultISR /* 173*/
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.long DefaultISR /* 174*/
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.long DefaultISR /* 175*/
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.long DefaultISR /* 176*/
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.long DefaultISR /* 177*/
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.long DefaultISR /* 178*/
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.long DefaultISR /* 179*/
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.long DefaultISR /* 180*/
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.long DefaultISR /* 181*/
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.long DefaultISR /* 182*/
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.long DefaultISR /* 183*/
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.long DefaultISR /* 184*/
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.long DefaultISR /* 185*/
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.long DefaultISR /* 186*/
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.long DefaultISR /* 187*/
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.long DefaultISR /* 188*/
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.long DefaultISR /* 189*/
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.long DefaultISR /* 190*/
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.long DefaultISR /* 191*/
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.long DefaultISR /* 192*/
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.long DefaultISR /* 193*/
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.long DefaultISR /* 194*/
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.long DefaultISR /* 195*/
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.long DefaultISR /* 196*/
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.long DefaultISR /* 197*/
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.long DefaultISR /* 198*/
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.long DefaultISR /* 199*/
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.long DefaultISR /* 200*/
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.long DefaultISR /* 201*/
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.long DefaultISR /* 202*/
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.long DefaultISR /* 203*/
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.long DefaultISR /* 204*/
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.long DefaultISR /* 205*/
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.long DefaultISR /* 206*/
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.long DefaultISR /* 207*/
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.long DefaultISR /* 208*/
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.long DefaultISR /* 209*/
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.long DefaultISR /* 210*/
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.long DefaultISR /* 211*/
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.long DefaultISR /* 212*/
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.long DefaultISR /* 213*/
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.long DefaultISR /* 214*/
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.long DefaultISR /* 215*/
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.long DefaultISR /* 216*/
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.long DefaultISR /* 217*/
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.long DefaultISR /* 218*/
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.long DefaultISR /* 219*/
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.long DefaultISR /* 220*/
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.long DefaultISR /* 221*/
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.long DefaultISR /* 222*/
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.long DefaultISR /* 223*/
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.long DefaultISR /* 224*/
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.long DefaultISR /* 225*/
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.long DefaultISR /* 226*/
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.long DefaultISR /* 227*/
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.long DefaultISR /* 228*/
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.long DefaultISR /* 229*/
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.long DefaultISR /* 230*/
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.long DefaultISR /* 231*/
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.long DefaultISR /* 232*/
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.long DefaultISR /* 233*/
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.long DefaultISR /* 234*/
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.long DefaultISR /* 235*/
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.long DefaultISR /* 236*/
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.long DefaultISR /* 237*/
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.long DefaultISR /* 238*/
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.long DefaultISR /* 239*/
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.long DefaultISR /* 240*/
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.long DefaultISR /* 241*/
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.long DefaultISR /* 242*/
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.long DefaultISR /* 243*/
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.long DefaultISR /* 244*/
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.long DefaultISR /* 245*/
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.long DefaultISR /* 246*/
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.long DefaultISR /* 247*/
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.long DefaultISR /* 248*/
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.long DefaultISR /* 249*/
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.long DefaultISR /* 250*/
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.long DefaultISR /* 251*/
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.long DefaultISR /* 252*/
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.long DefaultISR /* 253*/
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.long DefaultISR /* 254*/
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.long 0xFFFFFFFF /* Reserved for user TRIM value*/
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.size __isr_vector, . - __isr_vector
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/* Flash Configuration */
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.section .FlashConfig, "a"
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFE
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.equ _NVIC_ICER0, 0xE000E180
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.equ _NVIC_ICPR0, 0xE000E280
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.text
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.thumb
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/* Reset Handler */
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.thumb_func
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.align 2
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.global Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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cpsid i /* Mask interrupts */
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ldr r0, =_NVIC_ICER0 /* Disable interrupts and clear pending flags */
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ldr r1, =_NVIC_ICPR0
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ldr r2, =0xFFFFFFFF
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mov r3, #8
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_irq_clear:
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cbz r3, _irq_clear_end
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str r2, [r0], #4 /* NVIC_ICERx - clear enable IRQ register */
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str r2, [r1], #4 /* NVIC_ICPRx - clear pending IRQ register */
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sub r3, r3, #1
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b _irq_clear
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_irq_clear_end:
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/*
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#ifndef __NO_SYSTEM_INIT
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bl SystemInit
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#endif
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*/
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cpsie i /* Unmask interrupts */
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/* Loop to copy data from read only memory to RAM. The ranges
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* of copy from/to are specified by following symbols evaluated in
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* linker script.
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* __etext: End of code section, i.e., begin of data sections to copy from.
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* __data_start__/__data_end__: RAM address range that data should be
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* copied to. Both must be aligned to 4 bytes boundary. */
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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subs r3, r2
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ble .LC1
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.LC0:
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subs r3, #4
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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bgt .LC0
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.LC1:
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#ifdef __STARTUP_CLEAR_BSS
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/* This part of work usually is done in C library startup code. Otherwise,
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* define this macro to enable it in this startup.
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*
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* Loop to zero out BSS section, which uses following symbols
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* in linker script:
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* __bss_start__: start of BSS section. Must align to 4
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* __bss_end__: end of BSS section. Must align to 4
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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movs r0, 0
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.LC2:
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cmp r1, r2
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itt lt
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strlt r0, [r1], #4
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blt .LC2
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#endif /* __STARTUP_CLEAR_BSS */
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#ifndef __START
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#define __START _start
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#endif
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bl main
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/* bl __START */
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak Default_Handler
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.type Default_Handler, %function
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Default_Handler:
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b .
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.size Default_Handler, . - Default_Handler
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, Default_Handler
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.endm
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/* Exception Handlers */
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler MemManage_Handler
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def_irq_handler BusFault_Handler
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def_irq_handler UsageFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler DebugMon_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler DMA0_IRQHandler
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def_irq_handler DMA1_IRQHandler
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def_irq_handler DMA2_IRQHandler
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def_irq_handler DMA3_IRQHandler
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def_irq_handler DMA4_IRQHandler
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def_irq_handler DMA5_IRQHandler
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def_irq_handler DMA6_IRQHandler
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def_irq_handler DMA7_IRQHandler
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def_irq_handler DMA8_IRQHandler
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def_irq_handler DMA9_IRQHandler
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def_irq_handler DMA10_IRQHandler
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def_irq_handler DMA11_IRQHandler
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def_irq_handler DMA12_IRQHandler
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def_irq_handler DMA13_IRQHandler
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def_irq_handler DMA14_IRQHandler
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def_irq_handler DMA15_IRQHandler
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def_irq_handler DMA_Error_IRQHandler
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def_irq_handler MCM_IRQHandler
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def_irq_handler FTFE_IRQHandler
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def_irq_handler Read_Collision_IRQHandler
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def_irq_handler LVD_LVW_IRQHandler
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def_irq_handler LLW_IRQHandler
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def_irq_handler Watchdog_IRQHandler
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def_irq_handler RNG_IRQHandler
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def_irq_handler I2C0_IRQHandler
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def_irq_handler I2C1_IRQHandler
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def_irq_handler SPI0_IRQHandler
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def_irq_handler SPI1_IRQHandler
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def_irq_handler I2S0_Tx_IRQHandler
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def_irq_handler I2S0_Rx_IRQHandler
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def_irq_handler UART0_LON_IRQHandler
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def_irq_handler UART0_RX_TX_IRQHandler
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def_irq_handler UART0_ERR_IRQHandler
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def_irq_handler UART1_RX_TX_IRQHandler
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def_irq_handler UART1_ERR_IRQHandler
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def_irq_handler UART2_RX_TX_IRQHandler
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def_irq_handler UART2_ERR_IRQHandler
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def_irq_handler UART3_RX_TX_IRQHandler
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def_irq_handler UART3_ERR_IRQHandler
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def_irq_handler ADC0_IRQHandler
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def_irq_handler CMP0_IRQHandler
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def_irq_handler CMP1_IRQHandler
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def_irq_handler FTM0_IRQHandler
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def_irq_handler FTM1_IRQHandler
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def_irq_handler FTM2_IRQHandler
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def_irq_handler CMT_IRQHandler
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def_irq_handler RTC_IRQHandler
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def_irq_handler RTC_Seconds_IRQHandler
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def_irq_handler PIT0_IRQHandler
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def_irq_handler PIT1_IRQHandler
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def_irq_handler PIT2_IRQHandler
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def_irq_handler PIT3_IRQHandler
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def_irq_handler PDB0_IRQHandler
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def_irq_handler USB0_IRQHandler
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def_irq_handler USBDCD_IRQHandler
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def_irq_handler Reserved71_IRQHandler
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def_irq_handler DAC0_IRQHandler
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def_irq_handler MCG_IRQHandler
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def_irq_handler LPTimer_IRQHandler
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def_irq_handler PORTA_IRQHandler
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def_irq_handler PORTB_IRQHandler
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def_irq_handler PORTC_IRQHandler
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def_irq_handler PORTD_IRQHandler
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def_irq_handler PORTE_IRQHandler
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def_irq_handler SWI_IRQHandler
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def_irq_handler SPI2_IRQHandler
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def_irq_handler UART4_RX_TX_IRQHandler
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def_irq_handler UART4_ERR_IRQHandler
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def_irq_handler UART5_RX_TX_IRQHandler
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def_irq_handler UART5_ERR_IRQHandler
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def_irq_handler CMP2_IRQHandler
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def_irq_handler FTM3_IRQHandler
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def_irq_handler DAC1_IRQHandler
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def_irq_handler ADC1_IRQHandler
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def_irq_handler I2C2_IRQHandler
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def_irq_handler CAN0_ORed_Message_buffer_IRQHandler
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def_irq_handler CAN0_Bus_Off_IRQHandler
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def_irq_handler CAN0_Error_IRQHandler
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def_irq_handler CAN0_Tx_Warning_IRQHandler
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def_irq_handler CAN0_Rx_Warning_IRQHandler
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def_irq_handler CAN0_Wake_Up_IRQHandler
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def_irq_handler SDHC_IRQHandler
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def_irq_handler ENET_1588_Timer_IRQHandler
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def_irq_handler ENET_Transmit_IRQHandler
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def_irq_handler ENET_Receive_IRQHandler
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def_irq_handler ENET_Error_IRQHandler
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def_irq_handler DefaultISR
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.end
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