37 lines
966 B
VHDL
37 lines
966 B
VHDL
others => x"00000000"
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);
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begin
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process (clk)
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begin
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if (clk'event and clk = '1') then
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if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
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report "write collision" severity failure;
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end if;
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if (memAWriteEnable = '1') then
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ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE)))) := memAWrite;
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memARead <= memAWrite;
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else
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memARead <= ram(to_integer(unsigned(memAAddr(ADDR_32BIT_BRAM_RANGE))));
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end if;
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end if;
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end process;
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process (clk)
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begin
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if (clk'event and clk = '1') then
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if (memBWriteEnable = '1') then
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ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE)))) := memBWrite;
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memBRead <= memBWrite;
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else
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memBRead <= ram(to_integer(unsigned(memBAddr(ADDR_32BIT_BRAM_RANGE))));
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end if;
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end if;
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end process;
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end arch;
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