commit 6ac7fa5563a513c7603c34266065a393554c60d7 Author: Philip Smart Date: Thu Feb 17 13:17:58 2022 +0000 First push diff --git a/DefaultSession.hsf b/DefaultSession.hsf new file mode 100644 index 0000000..bea5f0e --- /dev/null +++ b/DefaultSession.hsf @@ -0,0 +1,107 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.3" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"{0CE21862-D122-40C7-8480-3B1EC1503AF0}ZipcCtrlViews" "0" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" "" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointFlag" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointStatus" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBrowseDirectory" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlSplitterPosition" "242" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "1" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlWindowProperties" "17" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineWndInstanceKey0" "{WK_00000001_CmdLine}" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileDir" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileName" "" +"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" +[LANGUAGE] +"English" +[CONFIG_INFO_VD1] +1 +[CONFIG_INFO_VD2] +0 +[CONFIG_INFO_VD3] +0 +[CONFIG_INFO_VD4] +0 +[WINDOW_POSITION_STATE_DATA_VD1] +"Help" "TOOLBAR 0" 59419 2 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_00000001_CmdLine}" "WINDOW" 59422 0 1 "0.17" 340 60 0 350 200 17 0 "32771|32772|32778|<>|32773|32774|<>|32820|<>|32801|32824" "0.0" +"{WK_00000001_MAPSCT}X1keybordDefaultSession" "WINDOW" 59422 0 0 "1.00" 557 283 103 795 557 2053 0 "32812|<>|32813|32814|<>|32816|<>|32822|32821|<>|32796|32797|<>|32833|<>|32825|32829|<>|32852" "29.5" +"{WK_00000001_MAPSYM}X1keybordDefaultSession" "WINDOW" 59422 0 0 "1.00" 516 327 127 802 516 2053 0 "32833|<>|32826|32828|<>|32852" "50.0" +"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 340 518 256 350 200 18 0 "36756|36757|36758|36759|<>|36746|36747|<>|39531|<>|39500|39534|<>|36687" "0.0" +"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 180 518 256 350 200 18 0 "" "0.0" +"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 2 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 2 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 1 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000010_TOOLS}" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 1 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000026_MACRO}" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000028_RTOSDEBUG}" "TOOLBAR 0" 59419 2 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[WINDOW_Z_ORDER] +"D:\Renesas\x1key\main.c" +[TARGET_NAME] +"" "" 1632504443 +[STATUSBAR_STATEINFO_VD1] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD2] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD3] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD4] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD1] +[STATUSBAR_DEBUGGER_PANESTATE_VD2] +[STATUSBAR_DEBUGGER_PANESTATE_VD3] +[STATUSBAR_DEBUGGER_PANESTATE_VD4] +[DEBUGGER_OPTIONS] +"" +[DOWNLOAD_MODULES] +[CONNECT_ON_GO] +"FALSE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[REMOVE_BREAKPOINTS_ON_DOWNLOAD] +"FALSE" +[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION] +"FALSE" +[LIMIT_DISASSEMBLY_MEMORY_ACCESS] +"FALSE" +[DISABLE_MEMORY_ACCESS_DURING_EXECUTION] +"FALSE" +[DEBUGGER_OPTIONS_PROPERTIES] +"1" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"" +[FLASH_DETAILS] +"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/Release/Release.hdp b/Release/Release.hdp new file mode 100644 index 0000000..b001148 Binary files /dev/null and b/Release/Release.hdp differ diff --git a/Release/keyconv.m16cc b/Release/keyconv.m16cc new file mode 100644 index 0000000..b7509b3 --- /dev/null +++ b/Release/keyconv.m16cc @@ -0,0 +1,10 @@ +-lang=c +-D__UART0__ +-c +-finfo +-dir "D:\Renesas\mz25key\Release" +-O5 +-OR +-silent +-R8C +"D:\Renesas\mz25key\keyconv.c" diff --git a/Release/keyconv.obj b/Release/keyconv.obj new file mode 100644 index 0000000..94b74d0 Binary files /dev/null and b/Release/keyconv.obj differ diff --git a/Release/main.m16cc b/Release/main.m16cc new file mode 100644 index 0000000..2135488 --- /dev/null +++ b/Release/main.m16cc @@ -0,0 +1,10 @@ +-lang=c +-D__UART0__ +-c +-finfo +-dir "D:\Renesas\mz25key\Release" +-O5 +-OR +-silent +-R8C +"D:\Renesas\mz25key\main.c" diff --git a/Release/main.obj b/Release/main.obj new file mode 100644 index 0000000..3d6ef4c Binary files /dev/null and b/Release/main.obj differ diff --git a/Release/ncrt0.lst b/Release/ncrt0.lst new file mode 100644 index 0000000..d666bc2 --- /dev/null +++ b/Release/ncrt0.lst @@ -0,0 +1,212 @@ +* M16C Series and R8C Family Assmbler * SOURCE LIST Sat Dec 18 13:03:52 2021 PAGE 001 + + SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4....*....5....*....6....*....7....*....8....*....9....*....0 + + 1 ;---------------------------------------------------------------------- + 2 ; | + 3 ; | + 4 ; | + 5 ; DESCRIPTION : Startup Program. (for Assembler language) | + 6 ; | + 7 ; | + 8 ; This file is generated by Renesas Project Generator. | + 9 ; | + 10 ;---------------------------------------------------------------------- + 11 ;/********************************************************************* + 12 ;* + 13 ;* Device : R8C Family + 14 ;* + 15 ;* File Name : ncrt0.a30 + 16 ;* + 17 ;* Abstract : Startup Program + 18 ;* + 19 ;* History : 1.01 (2006-11-22) + 20 ;* + 21 ;* NOTE : THIS IS A TYPICAL EXAMPLE. + 22 ;* + 23 ;* Copyright (C) 2006 Renesas Electronics Corporation. + 24 ;* and Renesas Solutions Corp. + 25 ;* + 26 ;*********************************************************************/ + 27 ;--------------------------------------------------------------------- + 28 ; include files + 29 ;--------------------------------------------------------------------- + 30 .list OFF + 31 .list ON + 32 + 33 ;===================================================================== + 34 ; Interrupt section start + 35 ;--------------------------------------------------------------------- + 36 .glb start + 37 .section interrupt,CODE,ALIGN + 38 .insf start,G,0 + 39 00000 start: + 40 ;--------------------------------------------------------------------- + 41 ; after reset,this program will start + 42 ;--------------------------------------------------------------------- + 43 00000 EB400000r ldc #((topof istack)+(sizeof istack)),isp ;set istack pointer + 44 00004 C7020A00 S mov.b #02h,0ah + 45 00008 B70400 Z mov.b #00h,04h ;set processer mode + 46 0000B B70A00 Z mov.b #00h,0ah + 47 .if __STACKSIZE__ != 0 + 48 0000E EB308000 ldc #0080h,flg + 49 00012 EB500000r ldc #((topof stack)+(sizeof stack)),sp ;set stack pointer + 50 .else + 51 .endif + 52 00016 EB600004 ldc #__SB__,sb ;set sb register + 53 + 54 ; If the destination is INTBL or INTBH, + 55 ; make sure that bytes are transferred in succession. + 56 0001A EB200000r ldc #((topof vector)>>16)&0FFFFh,INTBH + 57 0001E EB100000r ldc #(topof vector)&0FFFFh,INTBL + 58 + 59 ;===================================================================== + 60 ; NEAR area initialize. + 61 ;--------------------------------------------------------------------- + 62 ; bss zero clear + * M16C Series and R8C Family Assmbler * SOURCE LIST Sat Dec 18 13:03:52 2021 PAGE 002 + + SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4....*....5....*....6....*....7....*....8....*....9....*....0 + + 63 ;--------------------------------------------------------------------- + 64 N_BZERO (topof bss_SE),bss_SE + 65 00022 B4 1 M Z mov.b #00H, R0L + 66 00023 AA0000r 1 M S mov.w #((topof bss_SE) & 0FFFFH), A1 + 67 00026 75C30000r 1 M mov.w #sizeof bss_SE , R3 + 68 0002A 7CEA 1 M sstr.b + 69 1 M .endm + 70 N_BZERO (topof bss_SO),bss_SO + 71 0002C B4 1 M Z mov.b #00H, R0L + 72 0002D AA0000r 1 M S mov.w #((topof bss_SO) & 0FFFFH), A1 + 73 00030 75C30000r 1 M mov.w #sizeof bss_SO , R3 + 74 00034 7CEA 1 M sstr.b + 75 1 M .endm + 76 N_BZERO (topof bss_NE),bss_NE + 77 00036 B4 1 M Z mov.b #00H, R0L + 78 00037 AA0000r 1 M S mov.w #((topof bss_NE) & 0FFFFH), A1 + 79 0003A 75C30000r 1 M mov.w #sizeof bss_NE , R3 + 80 0003E 7CEA 1 M sstr.b + 81 1 M .endm + 82 N_BZERO (topof bss_NO),bss_NO + 83 00040 B4 1 M Z mov.b #00H, R0L + 84 00041 AA0000r 1 M S mov.w #((topof bss_NO) & 0FFFFH), A1 + 85 00044 75C30000r 1 M mov.w #sizeof bss_NO , R3 + 86 00048 7CEA 1 M sstr.b + 87 1 M .endm + 88 + 89 ;--------------------------------------------------------------------- + 90 ; initialize data section + 91 ;--------------------------------------------------------------------- + 92 N_BCOPY (topof data_SEI),(topof data_SE),data_SE + 93 0004A A20000r 1 M S mov.w #((topof data_SEI) & 0FFFFH),A0 + 94 0004D 74C300r 1 M mov.b #((topof data_SEI) >>16),R1H + 95 00050 AA0000r 1 M S mov.w #(topof data_SE) ,A1 + 96 00053 75C30000r 1 M mov.w #sizeof data_SE , R3 + 97 00057 7CE8 1 M smovf.b + 98 1 M .endm + 99 N_BCOPY (topof data_SOI),(topof data_SO),data_SO + 100 00059 A20000r 1 M S mov.w #((topof data_SOI) & 0FFFFH),A0 + 101 0005C 74C300r 1 M mov.b #((topof data_SOI) >>16),R1H + 102 0005F AA0000r 1 M S mov.w #(topof data_SO) ,A1 + 103 00062 75C30000r 1 M mov.w #sizeof data_SO , R3 + 104 00066 7CE8 1 M smovf.b + 105 1 M .endm + 106 N_BCOPY (topof data_NEI),(topof data_NE),data_NE + 107 00068 A20000r 1 M S mov.w #((topof data_NEI) & 0FFFFH),A0 + 108 0006B 74C300r 1 M mov.b #((topof data_NEI) >>16),R1H + 109 0006E AA0000r 1 M S mov.w #(topof data_NE) ,A1 + 110 00071 75C30000r 1 M mov.w #sizeof data_NE , R3 + 111 00075 7CE8 1 M smovf.b + 112 1 M .endm + 113 N_BCOPY (topof data_NOI),(topof data_NO),data_NO + 114 00077 A20000r 1 M S mov.w #((topof data_NOI) & 0FFFFH),A0 + 115 0007A 74C300r 1 M mov.b #((topof data_NOI) >>16),R1H + 116 0007D AA0000r 1 M S mov.w #(topof data_NO) ,A1 + 117 00080 75C30000r 1 M mov.w #sizeof data_NO , R3 + 118 00084 7CE8 1 M smovf.b + 119 1 M .endm + 120 + 121 ;===================================================================== + 122 ; heap area initialize + 123 ;--------------------------------------------------------------------- + 124 .if __HEAPSIZE__ != 0 + * M16C Series and R8C Family Assmbler * SOURCE LIST Sat Dec 18 13:03:52 2021 PAGE 003 + + SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4....*....5....*....6....*....7....*....8....*....9....*....0 + + 125 .endif + 126 + 127 ;===================================================================== + 128 ; Initialize standard I/O + 129 ;--------------------------------------------------------------------- + 130 .if __STANDARD_IO__ == 1 + 131 .endif + 132 + 133 ;===================================================================== + 134 ; Call main() function + 135 ;--------------------------------------------------------------------- + 136 00086 EB700000 ldc #0h,fb ; for debuger + 137 + 138 ; Remove the comment when you use global class object + 139 ; Sections C$INIT will be generated + 140 ; .glb __CALL_INIT + 141 ; .call __CALL_INIT,G + 142 ; jsr.a __CALL_INIT + 143 + 144 .glb _main + 145 .call _main,G + 146 0008A FD000000r A jsr.a _main + 147 + 148 ;===================================================================== + 149 ; exit() function + 150 ;--------------------------------------------------------------------- + 151 .glb _exit + 152 .glb $exit + 153 .glb __exit_loop + 154 0008E _exit: + 155 0008E $exit: + 156 + 157 ; Remove the comment when you use global class object + 158 ; Sections C$INIT will be generated + 159 ; .glb __CALL_END + 160 ; .call __CALL_END,G + 161 ; jsr.a __CALL_END + 162 + 163 0008E __exit_loop: ; End program + 164 0008E FEFF B jmp __exit_loop + 165 .einsf + 166 ;===================================================================== + 167 ; dummy interrupt function + 168 ;--------------------------------------------------------------------- + 169 .glb dummy_int + 170 00090 dummy_int: + 171 00090 FB reit + 172 + 173 .end + +Information List + +TOTAL ERROR(S) 00000 +TOTAL WARNING(S) 00000 +TOTAL LINE(S) 00173 LINES + +Section List + +Attr Size Name +DATA 0000000(00000H) data_SE +DATA 0000000(00000H) bss_SE +DATA 0000000(00000H) data_SO +DATA 0000000(00000H) bss_SO +DATA 0000000(00000H) data_NE +DATA 0000000(00000H) bss_NE +DATA 0000000(00000H) data_NO +DATA 0000000(00000H) bss_NO +DATA 0000128(00080H) stack +DATA 0000128(00080H) istack +ROMDATA 0000000(00000H) data_SEI +ROMDATA 0000000(00000H) data_SOI +ROMDATA 0000000(00000H) data_NEI +ROMDATA 0000000(00000H) data_NOI +ROMDATA 0000000(00000H) vector +ROMDATA 0000040(00028H) fvector +CODE 0000145(00091H) interrupt diff --git a/Release/ncrt0.m16ca b/Release/ncrt0.m16ca new file mode 100644 index 0000000..660dda2 --- /dev/null +++ b/Release/ncrt0.m16ca @@ -0,0 +1,7 @@ +-finfo +-O"D:\Renesas\mz25key\Release" +-LM +-. +-D__R8C__=1 +-R8C +"D:\Renesas\mz25key\ncrt0.a30" diff --git a/Release/ncrt0.obj b/Release/ncrt0.obj new file mode 100644 index 0000000..3653fbf Binary files /dev/null and b/Release/ncrt0.obj differ diff --git a/Release/ps2.m16cc b/Release/ps2.m16cc new file mode 100644 index 0000000..5014b86 --- /dev/null +++ b/Release/ps2.m16cc @@ -0,0 +1,10 @@ +-lang=c +-D__UART0__ +-c +-finfo +-dir "D:\Renesas\mz25key\Release" +-O5 +-OR +-silent +-R8C +"D:\Renesas\mz25key\ps2.c" diff --git a/Release/ps2.obj b/Release/ps2.obj new file mode 100644 index 0000000..3bb35f8 Binary files /dev/null and b/Release/ps2.obj differ diff --git a/Release/timer.m16cc b/Release/timer.m16cc new file mode 100644 index 0000000..6d5896b --- /dev/null +++ b/Release/timer.m16cc @@ -0,0 +1,10 @@ +-lang=c +-D__UART0__ +-c +-finfo +-dir "D:\Renesas\mz25key\Release" +-O5 +-OR +-silent +-R8C +"D:\Renesas\mz25key\timer.c" diff --git a/Release/timer.obj b/Release/timer.obj new file mode 100644 index 0000000..9037788 Binary files /dev/null and b/Release/timer.obj differ diff --git a/Release/x1key.m16cc b/Release/x1key.m16cc new file mode 100644 index 0000000..bf97c30 --- /dev/null +++ b/Release/x1key.m16cc @@ -0,0 +1,10 @@ +-lang=c +-D__UART0__ +-c +-finfo +-dir "D:\Renesas\mz25key\Release" +-O5 +-OR +-silent +-R8C +"D:\Renesas\mz25key\x1key.c" diff --git a/Release/x1key.obj b/Release/x1key.obj new file mode 100644 index 0000000..fa3c8e3 Binary files /dev/null and b/Release/x1key.obj differ diff --git a/X1key.tps b/X1key.tps new file mode 100644 index 0000000..a66c798 --- /dev/null +++ b/X1key.tps @@ -0,0 +1,26 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.1" +[SESSIONS_] +"DefaultSession" +[CONFIGURATIONS] +"Debug" +"Release" +[CURRENT_CONFIGURATION] +"Release" +[CURRENT_SESSION] +"DefaultSession" +[GENERAL_DATA_PROJECT] +[GENERAL_DATA_CONFIGURATION_Debug] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Debug] +"DefaultSession" +[GENERAL_DATA_CONFIGURATION_Release] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_Release] +"DefaultSession" +[GENERAL_DATA_SESSION_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Release_DefaultSession] +[END] diff --git a/doc/Readme.txt b/doc/Readme.txt new file mode 100644 index 0000000..07ba841 --- /dev/null +++ b/doc/Readme.txt @@ -0,0 +1,19 @@ +-------- PROJECT GENERATOR -------- +PROJECT NAME: X1keybord +PROJECT DIRECTORY: C: \ Users \ uts \ SkyDrive \ Documents \ HEW \ R8C_X1keybord \ X1keybord +CPU SERIES: R8C / Tiny +CPU GROUP: M12A +TOOLCHAIN NAME: Renesas M16C Standard Toolchain +TOOLCHAIN VERSION: 6.00.00 +GENERATION FILES: + C: \ Users \ uts \ SkyDrive \ Documents \ HEW \ R8C_X1keybord \ X1keybord \ X1keybord.c + main program file. + C: \ Users \ uts \ SkyDrive \ Documents \ HEW \ R8C_X1keybord \ X1keybord \ nc_define.inc + interrupt program. +START UP FILES: + C: \ Users \ uts \ SkyDrive \ Documents \ HEW \ R8C_X1keybord \ X1keybord \ ncrt0.a30 + C: \ Users \ uts \ SkyDrive \ Documents \ HEW \ R8C_X1keybord \ X1keybord \ sfr_r8m12a.h + C: \ Users \ uts \ SkyDrive \ Documents \ HEW \ R8C_X1keybord \ X1keybord \ sfr_r8m12a.inc + C: \ Users \ uts \ SkyDrive \ Documents \ HEW \ R8C_X1keybord \ X1keybord \ sect30.inc + +DATE & TIME: 2014/07/16 3:13:49 diff --git a/doc/ps2.txt b/doc/ps2.txt new file mode 100644 index 0000000..6e21a68 --- /dev/null +++ b/doc/ps2.txt @@ -0,0 +1,176 @@ +/ * +Connect a PS / 2 keyboard to SHARP X1 +PS / 2 keyboard reception processing +. +It's easy because you only read one bit at a time at the falling edge of the clock. +Start bit 1 +Data bit 8 +Parity bit 1 +Stop bit 1 +. +11-bit odd parity in total +I wrote the key code sent to me at http://kyoutan.jpn.org/uts/pc/pic/x68key/. + + + +Created July 22, 2014 +. +Kyoichi Sato http://kyoutan.jpn.org/ + +There is no guarantee. +The part created by Kyoichi Sato has no restrictions on its use. You can use it freely regardless of whether it is commercial or non-commercial. +It means that you can copy, modify, distribute, or sell it without permission. +No need to contact. +* / / + +#include "sfr_r8m12a.h" +#include "ps2.h" +#include "iodefine.h" + +volatile unsigned short PS2TIMER = 0; // PS2 receive timeout timer +volatile unsigned char PS2BUFF [PS2BUFFSIZE]; // PS2 receive buffer +volatile unsigned char PS2RPOS = 0; // PS2 read position +volatile unsigned char PS2WPOS = 0; // PS2 write position + +void ps2key_init (void) +{ +/ * INT0 External interrupt initialization * / +// INT0 PS / 2 CLOCK +intf0 = 0b00000001; // Use INT0 f1 filter 1 * 3 / 18.432 = 0.16us +iscr0 = 0b00000000; // INT0 Falling edge +inten = 0b00000001; // INT0 input permission +{ +unsigned char a; +for (a = (6 * 8); a! = 0; a--) asm ("nop"); // Wait a minute +} +// PMLi PMHi ISCR0 INTEN KIEN Rewriting the register may set the interrupt request flag to 1. +// is written in the manual, so clear the flag +while (1 == iri0) iri0 = 0; +} + +// External interrupt INT0 +// Interrupt at the fall of PS / 2 CLOCK and capture data bit by bit +#pragma INTERRUPT INT_int0 (vect = 29) +void INT_int0 (void) +{ +static unsigned short bit = 1; +static unsigned short data = 0; +static unsigned char parity = 0; +. +// If the reception is stopped, clear the status and receive from the beginning +if ((bit! = 1) && (PS2TIMEOUT ps2size ()) // Is there a free buffer? +{ +PS2BUFF [PS2WPOS] = ((data >> 1) & 0xFF); +. +if ((PS2BUFFSIZE-1)> PS2WPOS) +{ +PS2WPOS ++; +} +else else +{ +PS2WPOS = 0; +} +} +else else +{ +// Buffer full +} +} +else else +{ +// Parity error +} + +bit = 1; +data = 0; +parity = 0; +} +else else +{ +if ((1 == bit) && (data! = 0)) +{// start bit is not zero state reset +bit = 1; +data = 0; +parity = 0; +} +else else +{// Ready to read the next bit +bit = (bit << 1); +PS2TIMER = 0; // Clear timeout timer +} +} +. +while (1 == iri0) iri0 = 0; // The interrupt flag is automatically cleared, so you don't have to do this line. +} + +// Returns the number of valid data in the buffer +unsigned char ps2size (void) +{ +signed int size; +. +size = (signed int) PS2WPOS-PS2RPOS; +if (0> size) +{ +size = PS2BUFFSIZE + size; +} +. +return size; +// size = 5 wpos = 2 rpos = 3 4 +} + +// Clear the receive buffer +void ps2clear (void) +{ +PS2WPOS = 0; +PS2RPOS = 0; +PS2BUFF [PS2RPOS] = 0; +} + +// Read 1 byte from the buffer +unsigned char ps2read (void) +{ +unsigned char data = 0; + +if (PS2WPOS! = PS2RPOS) // Is there data in the buffer? +{ +data = PS2BUFF [PS2RPOS]; + +if ((PS2BUFFSIZE-1)> PS2RPOS) +{ +PS2RPOS ++; +} +else else +{ +PS2RPOS = 0; +} +} +return data; +} + +// Wait until it is received and read 1 byte +unsigned char ps2get (void) +{ +while (0 == ps2size ()); // Wait until the buffer is filled with data +return ps2read (); +} diff --git a/flash/X1KEY.AWS b/flash/X1KEY.AWS new file mode 100644 index 0000000..4daf14d --- /dev/null +++ b/flash/X1KEY.AWS @@ -0,0 +1,29 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"5.0" +[WORKSPACE_DETAILS] +"X1KEY" "D:\Renesas\x1key\flash" "D:\Renesas\x1key\flash\X1KEY.AWS" "All Flash Devices" "" +[SHARED_WORKSPACE_CONTROL_STATUS] +"" "" "" +"" "" "" +[PROJECTS] +"X1KEY" "D:\Renesas\x1key\flash\X1KEY" "D:\Renesas\x1key\flash\X1KEY\X1KEY.FWP" 0 +[INFORMATION] +"No workspace information available" +[SCRAP] +[PROJECT_DEPENDENCY] +[WORKSPACE_PROPERTIES] +[VCS] +"" "" "" 0 +[VCS_PROJECT] +[HELP_FILES] +[GENERAL_DATA_PROJECT] +[SYSMENUTOOLS] +[USERMENUTOOLS] +[CUSTOMPLACEHOLDERS] +[MAKEFILE_BUILD_INFO] +"$(WORKSPDIR)\make\$(PROJECTNAME).mak" "" 0 0 +[VD_CONFIGURATION_OPTIONS] +[VD_CONFIGURATIONS] +[END] diff --git a/flash/X1KEY.tws b/flash/X1KEY.tws new file mode 100644 index 0000000..d7da85e --- /dev/null +++ b/flash/X1KEY.tws @@ -0,0 +1,12 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.0" +[CURRENT_PROJECT] +"X1KEY" +[GENERAL_DATA] +"EDITOR_WINDOWS_MAXIMISED" "1" +[BREAKPOINTS] +[OPEN_WORKSPACE_FILES] +[WORKSPACE_FILE_STATES] +[END] diff --git a/flash/X1KEY/Default.hsf b/flash/X1KEY/Default.hsf new file mode 100644 index 0000000..e5fe675 --- /dev/null +++ b/flash/X1KEY/Default.hsf @@ -0,0 +1,32 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.3" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "0" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" +[WINDOW_POSITION_STATE_DATA_VD1] +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[TARGET_NAME] +"" +[DEBUGGER_OPTIONS] +"" +[DOWNLOAD_MODULES] +[CONNECT_ON_GO] +"FALSE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"" +[FLASH_DETAILS] +"0.000000" 0 0 "D" 500000 "COM5" 115200 0 "R5F2M122A" 1 0 0 2 1 -1 0 "C:\Program Files (x86)\Renesas\FDT4.09\kernels\ProtD\R5F2M122A\Renesas\1_0_00\" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/flash/X1KEY/Default.shl b/flash/X1KEY/Default.shl new file mode 100644 index 0000000..cc3f6ac --- /dev/null +++ b/flash/X1KEY/Default.shl @@ -0,0 +1,61 @@ +[ColorGroups] +Group1=Text +Group2=Text Selection +Group3=Line Comment +Group4=Block Comment +NumGroups=4 + +[Text] +Foreground=0,0,0 +ForeColorAutomatic=0 +Background=255,255,255 +BackColorAutomatic=0 +DisplayName=Text +Configurable=1 + +[Text Selection] +Foreground=255,255,255 +ForeColorAutomatic=0 +Background=0,0,0 +BackColorAutomatic=0 +DisplayName=Text Selection +Configurable=1 + +[Line Comment] +Foreground=0,0,0 +ForeColorAutomatic=0 +Background=255,255,255 +BackColorAutomatic=0 +DisplayName=Line Comment +Configurable=1 + +[Block Comment] +Foreground=0,0,0 +ForeColorAutomatic=0 +Background=255,255,255 +BackColorAutomatic=0 +DisplayName=Block Comment +Configurable=1 + +[Keywords] +[Parser] +Operators= +Delimiters = !"#$%&'()*+,-./:;<=>?@[\]^`{|}~ +KWStartChars= +KWMiddleChars= +KWEndChars= +NumTags=1 + +[Tag1] +ColorGroup=String +BeginTag=" +EndTag=" +MultiLine=0 +Escapechar=\ + +[Editor] +ShowWhitespace=0 +VirtualWhitespace=0 +VirtualWhitespace=0 +MatchCase=1 + diff --git a/flash/X1KEY/X1KEY.FWP b/flash/X1KEY/X1KEY.FWP new file mode 100644 index 0000000..faaaa29 --- /dev/null +++ b/flash/X1KEY/X1KEY.FWP @@ -0,0 +1,109 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.5" +[PROJECT_DETAILS] +"X1KEY" "D:\Renesas\x1key\flash\X1KEY" "D:\Renesas\x1key\flash\X1KEY\X1KEY.FWP" "All Flash Devices" "" "FDT Project Generator" +[INFORMATION] +"No project information available" +[TOOL_CHAIN] +"" "" +[CONFIGURATIONS] +"Default" "D:\Renesas\x1key\flash\X1KEY\Default" +[BUILD_PHASES] +[DEFINITION_PARSERS] +[TOOL_ENVIRONMENT] +[EXTENSIONS] +"FDT DDI Files" "DDI" +"S-Record Files" "MOT" +"S2 Files" "S2" +"FDT Binary Files" "CDE" +"Binary Files" "BIN" +"IAR A20 Files" "A20" +"IAR A37 Files" "A37" +"REC Files" "REC" +[FILE_GROUPS] +"FDT DDI Files" "BIN" "EDITOR" "" +"S-Record Files" "BIN" "HEX_EDITOR" "" +"S2 Files" "BIN" "HEX_EDITOR" "" +"FDT Binary Files" "BIN" "HEX_EDITOR" "" +"Binary Files" "BIN" "HEX_EDITOR" "" +"IAR A20 Files" "BIN" "HEX_EDITOR" "" +"IAR A37 Files" "BIN" "HEX_EDITOR" "" +"REC Files" "BIN" "HEX_EDITOR" "" +[ASSOCIATED_APPLICATIONS] +[TOOLCHAIN_PHASE] +[UTILITY_PHASE] +[CUSTOM_PHASES] +[CUSTOM_PHASE_INPUT_GROUP] +[BUILD_ORDER] +[BUILD_PHASE_DETAILS] +[SCRAP] +"Project Generator Setup File" "" +[MAPPINGS] +[PROJECT_FILES] +[FOLDER] +[GENERAL_DATA_PROJECT] +"FDT_BaseDevice" "R5F2M122A" +"FDT_Comments" "" +"FDT_DoSecurityProtection" "Prompt" +"FDT_BlockProtectConnect" "1" +"FDT_Interface" "Direct Connection" +"FDT_UseDefaultBaudRate" "FALSE" +"FDT_ResetPinLowOnDisconnect" "FALSE" +"FDT_DoSecurityProtectionLevel" "00" +"FDT_ResetPinOutputs" "FFFFFFFF" +"FDT_ConnectionResetSuppression" "FFFFFFFF" +"FDT_ResetOnDisconnect" "No" +"FDT_McuId" "2" +"FDT_ResetPinSettings" "FFFFFFFF" +"FDT_KernelPath" "C:\Program Files (x86)\Renesas\FDT4.09\kernels\ProtD\R5F2M122A\Renesas\1_0_00\" +"FDT_KernelResident" "FALSE" +"FDT_UPMPinSettings" "FFFFFFFF" +"FDT_InternalClock" "FALSE" +"FDT_CKM" "0" +"FDT_ClockMode" "-1" +"FDT_UserPinOutputs" "FFFFFFFF" +"FDT_UserPinSettings" "FFFFFFFF" +"FDT_UseInternalKernel" "TRUE" +"FDT_BlockProtectDisconnect" "1" +"FDT_SerNumConfigString" "" +"FDT_Port" "COM5" +"FDT_BlockLockConnect" "1" +"FDT_BlockLockDisconnect" "1" +"FDT_MessageLevel" "1" +"FDT_CKP" "0" +"FDT_BootMode" "TRUE" +"FDT_BaudRate" "115200" +"FDT_FileOverRomSizeOption" "Yes" +"FDT_PinOutputs" "FFFFFFFF" +"FDT_IDWriteEnable" "TRUE" +"FDT_IDWriteSecurityLevel" "1" +"FDT_Protection" "2" +"FDT_Protocol" "D" +"FDT_PinSettings" "FFFFFFFF" +"FDT_ErasureOfUserBootArea" "No" +"FDT_ClockType" "" +"FDT_ClockSync" "00000000" +"FDT_ReinterrogateGenericDevice" "No" +"FDT_Device" "R5F2M122A" +"FDT_AutoConnect" "0" +"FDT_Frequency" "0.0000" +"FDT_DoReadbackVerification" "Yes" +"FDT_IDWriteDisconnect" "1" +[ON_DEMAND_COMPONENTS_LOADED] +[SYNC_SESSION_NAMES] +[SESSIONS] +"Default" "D:\Renesas\x1key\flash\X1KEY\Default.hsf" 0 +[GENERAL_DATA_SESSION_Default] +[OPTIONS_Default] +"" 0 +[SESSION_DATA_CONFIGURATION_SESSION_Default_Default] +"MEMORY_MAPPING_OPTIONS" "" +[EXT_DEBUGGER_INFO] +0 "" "" "" "" +[EXCLUDED_FILES_Default] +[LINKAGE_ORDER_Default] +[GENERAL_DATA_CONFIGURATION_Default] +[GENERAL_DATA_CONFIGURATION_SESSION_Default_Default] +[END] diff --git a/flash/X1KEY/X1KEY.tps b/flash/X1KEY/X1KEY.tps new file mode 100644 index 0000000..5c2cef6 --- /dev/null +++ b/flash/X1KEY/X1KEY.tps @@ -0,0 +1,20 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.1" +[SESSIONS_] +"Default" +[CONFIGURATIONS] +"Default" +[CURRENT_CONFIGURATION] +"Default" +[CURRENT_SESSION] +"Default" +[GENERAL_DATA_PROJECT] +"FDT_UserBootAreaFiles" "" +[SESSIONS_Default] +"Default" +[GENERAL_DATA_CONFIGURATION_Default] +[GENERAL_DATA_CONFIGURATION_SESSION_Default_Default] +[GENERAL_DATA_SESSION_Default] +[END] diff --git a/flash/X1KEY/editordefault.shl b/flash/X1KEY/editordefault.shl new file mode 100644 index 0000000..cc3f6ac --- /dev/null +++ b/flash/X1KEY/editordefault.shl @@ -0,0 +1,61 @@ +[ColorGroups] +Group1=Text +Group2=Text Selection +Group3=Line Comment +Group4=Block Comment +NumGroups=4 + +[Text] +Foreground=0,0,0 +ForeColorAutomatic=0 +Background=255,255,255 +BackColorAutomatic=0 +DisplayName=Text +Configurable=1 + +[Text Selection] +Foreground=255,255,255 +ForeColorAutomatic=0 +Background=0,0,0 +BackColorAutomatic=0 +DisplayName=Text Selection +Configurable=1 + +[Line Comment] +Foreground=0,0,0 +ForeColorAutomatic=0 +Background=255,255,255 +BackColorAutomatic=0 +DisplayName=Line Comment +Configurable=1 + +[Block Comment] +Foreground=0,0,0 +ForeColorAutomatic=0 +Background=255,255,255 +BackColorAutomatic=0 +DisplayName=Block Comment +Configurable=1 + +[Keywords] +[Parser] +Operators= +Delimiters = !"#$%&'()*+,-./:;<=>?@[\]^`{|}~ +KWStartChars= +KWMiddleChars= +KWEndChars= +NumTags=1 + +[Tag1] +ColorGroup=String +BeginTag=" +EndTag=" +MultiLine=0 +Escapechar=\ + +[Editor] +ShowWhitespace=0 +VirtualWhitespace=0 +VirtualWhitespace=0 +MatchCase=1 + diff --git a/iodefine.h b/iodefine.h new file mode 100644 index 0000000..789cefb --- /dev/null +++ b/iodefine.h @@ -0,0 +1,55 @@ +/* + Connect a PS / 2 keyboard to SHARP X1 + Definition of I / O pins, etc. + + Created July 22, 2014 + + Kyoichi Sato http://kyoutan.jpn.org/ + + There is no guarantee. + The part created by Kyoichi Sato has no restrictions on its use. You can use it freely regardless of whether it is commercial or non-commercial. + It means that you can copy, modify, distribute, or sell it without permission. + No need to contact. +*/ + +#ifndef IODEFINE_H +#define IODEFINE_H + +#ifdef __cplusplus + extern "C" { +#endif + +// LED +#define LED p1_0 + +// UART +#define TXD p1_4 +#define RXD p1_5 + +// PS/2 Interface. +#define PS2_DATA_IN p3_3 +#define PS2_DATA_OUT p4_2 +#define PS2_CLK_IN p4_5 +#define PS2_CLK_OUT p1_1 +#define PS2DATA p3_3 +#define X1KEYOUT p3_7 + +// X1 Keyboard interface. +#define X1DATA p3_7 + +#define TRUE 1 +#define FALSE 0 +#define ON 1 +#define OFF 0 +#define NULL 0 + +#define DI() asm ("FCLR I") // Interrupt disabled +#define EI() asm ("FSET I") // Interrupt enabled + +// Types missing in the Renesas C compiler headers. +typedef unsigned char uint8_t; + +#ifdef __cplusplus +} +#endif +#endif // IODEFINE_H diff --git a/keyconv.c b/keyconv.c new file mode 100644 index 0000000..e5e72e9 --- /dev/null +++ b/keyconv.c @@ -0,0 +1,243 @@ +/* + Connect a PS / 2 keyboard to SHARP X1 + Key code conversion process + + Created on July 23, 2014 + + Kyoichi Sato http://kyoutan.jpn.org/ + + There is no guarantee. + The part created by Kyoichi Sato has no restrictions on its use. You can use it freely regardless of whether it is commercial or non-commercial. + It means that you can copy, modify, distribute, or sell it without permission. + No need to contact. +*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "sfr_r8m12a.h" +#include "keyconv.h" +#include "iodefine.h" +#include "keytable.h" +#include "ps2.h" +#include "x1key.h" + +volatile unsigned short x1shift = 0xFF; // Valid at X1 shift state save 0 +#define TENKEY ((unsigned char) (1 << 7)) +#define PRESS ((unsigned char) (1 << 6)) +#define REPEAT ((unsigned char) (1 << 5)) +#define GRAPH ((unsigned char) (1 << 4)) +#define CAPS ((unsigned char) (1 << 3)) +#define KANA ((unsigned char) (1 << 2)) +#define SHIFT ((unsigned char) (1 << 1)) +#define CTRL ((unsigned char) (1 << 0)) + + +volatile unsigned char ps2ex = 0; // PS2 keyboard extended key flag +#define EXKEY ((unsigned char) (1 << 0)) +#define RELEASE ((unsigned char) (1 << 1)) +#define PAUSE_BREAK ((unsigned char) (1 << 2)) + + +unsigned char codeconv(unsigned char data); +unsigned char checkbreak(void); +unsigned char x1code(unsigned char data); +void x1trans(unsigned char data); + + +void keyconv(void) +{ + unsigned char data; + + data = ps2get (); // Wait until it is received from the PS / 2 keyboard and read 1 byte + switch (data) + { + case 0xE0: // Extended key + ps2ex |= EXKEY; // Extended key flag set + break; + + case 0xF0: // separated + ps2ex |= RELEASE; // Separated flag set + break; + + default: + // Convert PS / 2 code to internal code + if (0xE1 == data) data = checkbreak (); // PAUSE / BREAK key determination + + if (0 == (ps2ex & EXKEY)) + {// normal key + if (0x8F data)) || (0x5A ret)) ret -= 0x20; // Uppercase alphabet + return ret; + } + if ((KANA | GRAPH | CTRL) == status) // CAPS + SHIFT + { + unsigned char ret; + ret = CHR_TBL1 [data]; + if ((0x40 ret)) ret += 0x20; // In lowercase letters + return ret; + } + + status &= (GRAPH | KANA | SHIFT | CTRL); + + if ((GRAPH | KANA | CTRL) == status) return CHR_TBL1 [data]; // SHIFT + if ((GRAPH | KANA | SHIFT) == status) return CHR_TBL3 [data]; // CTRL + if ((KANA | SHIFT | CTRL) == status) return CHR_TBL2 [data]; // GRAPH + if ((SHIFT | CTRL) == status) return CHR_TBL2 [data]; // GRAPH + KANA + if ((GRAPH | SHIFT | CTRL) == status) return CHR_TBL4 [data]; // KANA + if ((GRAPH | CTRL) == status) return CHR_TBL5 [data]; // KANA + SHIFT + + return CHR_TBL0 [data]; // No shift +} +#ifdef __cplusplus +} +#endif diff --git a/keyconv.h b/keyconv.h new file mode 100644 index 0000000..5240c97 --- /dev/null +++ b/keyconv.h @@ -0,0 +1,27 @@ +/* + Connect a PS / 2 keyboard to SHARP X1 + Key code conversion process + + Created on July 23, 2014 + + Kyoichi Sato http://kyoutan.jpn.org/ + + There is no guarantee. + The part created by Kyoichi Sato has no restrictions on its use. You can use it freely regardless of whether it is commercial or non-commercial. + It means that you can copy, modify, distribute, or sell it without permission. + No need to contact. +*/ + +#ifndef KEYCONV_H +#define KEYCONV_H + +#ifdef __cplusplus + extern "C" { +#endif + +void keyconv(void); + +#ifdef __cplusplus +} +#endif +#endif // KEYCONV_H diff --git a/keytable.h b/keytable.h new file mode 100644 index 0000000..baf7fa8 --- /dev/null +++ b/keytable.h @@ -0,0 +1,294 @@ +/* + PS / 2- SHARP X1 keycode conversion table + + I don't have the actual X1 keyboard, so the X1 keycode is + X1 emulator Xmillennium v0.26 T-tune STEP 1.43 (http://www.x1center.org/emu.html) + I used the table in Input.cpp contained in. + + + Created on July 23, 2014 + + Kyoichi Sato http://kyoutan.jpn.org/ + + There is no guarantee. + The part created by Kyoichi Sato has no restrictions on its use. You can use it freely regardless of whether it is commercial or non-commercial. + It means that you can copy, modify, distribute, or sell it without permission. + No need to contact. +*/ + + +typedef const unsigned char BYTE; + +#pragma section rom flash_data // Place the conversion table in the data flash +/* ~~~ ~~~~~~~~~~ + | +-The name of the section you like. + | Add placement attributes such as _NE _NO to this name + | Build-Specify the starting address in the linker section settings + | (No need to edit the sect30.inc file) + + --------- Default section name (program, rom, data, bss) + + +For placement attributes and default section names, +M16C Series, R8C Family C / C ++ Compiler User's Manual Chapter 2 Basic Usage of the Compiler +2.2.3 Customizing memory allocation a. See Section Configuration for more information. + +(The manual is installed with the "High-performancd Embedded Workshop (HEW)" +You can see it in "Manual Navigator") +*/ + + +#ifndef KEYTABLE_H +#define KEYTABLE_H + +#ifdef __cplusplus + extern "C" { +#endif + +// PS / 2 106 Keyboard to internal code conversion table +// If you convert the PS / 2 code directly to the X1 code, the X1 table will become large. +// Convert to internal code once +BYTE KEY106[0x100] = +{ +// 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F +// 0x00 F9 F5 F3 F1 F2 F12 F10 F8 F6 F4 TAB ‘SŠp + 0x00,0x43,0x00,0x3F,0x3D,0x3B,0x3C,0x58,0x00,0x44,0x42,0x40,0x3E,0x0F,0x29,0x00, +// 0x10 ALT SH L ‚Ђç CTRL Q 1 Z S A W 2 WIN + 0x00,0x38,0x2A,0x55,0x1D,0x10,0x02,0x00,0x00,0x00,0x2C,0x1F,0x1E,0x11,0x03,0x00, +// 0x20 C X D E 4 3 WIN SP V F T R 5 APL + 0x00,0x2E,0x2D,0x20,0x12,0x05,0x04,0x00,0x00,0x39,0x2F,0x21,0x14,0x13,0x06,0x00, +// 0x30 N B H G Y 6 M J U 7 8 + 0x00,0x31,0x30,0x23,0x22,0x15,0x07,0x00,0x00,0x00,0x32,0x24,0x16,0x08,0x09,0x00, +// 0x40 , K I O 0 9 . / L ; P - + 0x00,0x33,0x25,0x17,0x18,0x0B,0x0A,0x00,0x00,0x34,0x35,0x26,0x27,0x19,0x0C,0x00, +// 0x50 ‚ë : @ ^ CAPS SH R ENT [ ] + 0x00,0x59,0x28,0x00,0x1A,0x0d,0x00,0x00,0x3A,0x36,0x1C,0x1B,0x00,0x2B,0x00,0x00, +// 0x60 •ÏŠ· BS –³•Ï 1 \ 4 7 + 0x00,0x00,0x00,0x00,0x5E,0x00,0x0E,0x56,0x00,0x4F,0x5A,0x4B,0x47,0x00,0x00,0x00, +// 0x70 0 . 2 5 6 8 ESC NUM F11 + 3 - * 9 ScLk + 0x52,0x53,0x50,0x4C,0x4D,0x48,0x01,0x00,0x57,0x4E,0x51,0x4A,0x37,0x49,0x00,0x00, +// 0x80 BRK F7 + 0x45,0x00,0x00,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + +// Extended key +// 0x60 END © HOME + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x5F,0x00,0xCB,0xC7,0x00,0x00,0x00, +// 0x70 INS DEL « ¨ ª PgDn PgUp + 0xD2,0xD3,0xD0,0x00,0xCD,0xC8,0x00,0x00,0x00,0x00,0x5C,0x00,0x00,0x5B,0x00,0x00, + + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +// PAUSE/BREAK E1 14 77 E1 F0 14 F0 77 ¨ 0x80 +// PRINT SCREEN E0 12 E0 7C ¨ [SH L]+[*(TEN KEY)] +}; +/* ƒŠƒ^[ƒ“ƒR[ƒh ‘Œ©•\ + 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F + 0x00 ESC 1 2 3 4 5 6 7 8 9 0 - ^ BS TAB + 0x10 Q W E R T Y U I O P @ [ ENT CTRL A S + 0x20 D F G H J K L ; : ‘S SH L ] Z X C V + 0x30 B N M , . / SH R * ALT SP CAPS F1 F2 F3 F4 F5 + 0x40 F6 F7 F8 F9 F10 BRK 7 8 9 - 4 5 6 + 1 + 0x50 2 3 0 . ‚©‚È –³•Ï F11 F12 ‚ë \ PgUp PgDn = •ÏŠ· END + 0x60 + 0x70 + 0x80 + 0x90 + 0xA0 + 0xB0 + 0xC0 HOME ª © ¨ + 0xD0 « INS DEL +*/ + +#define GRAPH_CODE1 0x56 // Immutable +#define GRAPH_CODE2 0x38 // ALT +#define CAPS_CODE 0x3A // CAPS +#define KANA_CODE 0x55 // Katakana / Hiragana +#define SHIFTL_CODE 0x2A // Left SHIFT +#define SHIFTR_CODE 0x36 // Right SHIFT +#define CTRL_CODE 0x1D // CTRL +#define UP_CODE 0xC8 // ↑ +#define DOWN_CODE 0xD0 // ↓ +#define LEFT_CODE 0xCB // ← +#define RIGHT_CODE 0xCD // → → +#define INS_CODE 0xD2 // INS +#define DEL_CODE 0xD3 // DEL +#define HOME_CODE 0xC7 // HOME + +BYTE BREAK_CODE[8]={0xE1,0x14,0x77,0xE1,0xF0,0x14,0xF0,0x77}; // BREAK key code string + +// BASE +BYTE CHR_TBL0[]={ +/* -- , ESC, ‚P, ‚Q, ‚R, ‚S, ‚T, ‚U, 0x00 */ + 0x00,0x1b, '1', '2', '3', '4', '5', '6', +/* ‚V, ‚W, ‚X, ‚O, |, O, BS, TAB, 0x08 */ + '7', '8', '9', '0', '-', '^',0x08,0x09, +/* ‚p, ‚v, ‚d, ‚q, ‚s, ‚x, ‚t, ‚h, 0x10 */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', +/* ‚n, ‚o, —, m, Ent,Ctrl, ‚`, ‚r, 0x18 */ + 'o', 'p', '@', '[',0x0d,0x00, 'a', 's', +/* ‚c, ‚e, ‚f, ‚g, ‚i, ‚j, ‚k, G, 0x20 */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', +/* F, ‘S,SftL, n, ‚y, ‚w, ‚b, ‚u, 0x28 */ + ':',0x00,0x00, ']', 'z', 'x', 'c', 'v', +/* ‚a, ‚m, ‚l, C, D, ^,SftR, [*], 0x30 */ + 'b', 'n', 'm', ',', '.', '/',0x00,0x2a, +/* Alt, SPC, Cap, f.1, f.2, f.3, f.4, f.5, 0x38 */ + 0x00, ' ',0x00, 'q', 'r', 's', 't', 'u', +/* f.6, f.7, f.8, f.9,f.10,Paus,ScrL, [7], 0x40 */ + 0xec,0xeb,0xe2,0xe1,0x00,0x13,0x00, '7', +/* [8], [9], [-], [4], [5], [6], [+], [1], 0x48 */ + '8', '9', '-', '4', '5', '6', '+', '1', +/* [2], [3], [0], [.], ???, ???, ???,f.11, 0x50 */ + '2', '3', '0', '.',0x00,0x00,0x00,0x00, +/*f.12, _ , \ ,RLUP,RLDN,<>,XFER, END, 0x58 */ + 0x00,0x00,'\\',0x0e,0x0f, '=',0xfe,0x11, +}; + +// SHIFT +BYTE CHR_TBL1[]={ +/* -- , ESC, ‚P, ‚Q, ‚R, ‚S, ‚T, ‚U, 0x00 */ + 0x00,0x1b, '!',0x22, '#', '$',0x25, '&', +/* ‚V, ‚W, ‚X, ‚O, |, O, BS, TAB, 0x08 */ + 0x27, '(', ')', '0', '=',0x60,0x12,0x09, +/* ‚p, ‚v, ‚d, ‚q, ‚s, ‚x, ‚t, ‚h, 0x10 */ + 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', +/* ‚n, ‚o, —, m, Ent,Ctrl, ‚`, ‚r, 0x18 */ + 'O', 'P',0x7e, '{',0x0d,0x00, 'A', 'S', +/* ‚c, ‚e, ‚f, ‚g, ‚i, ‚j, ‚k, G, 0x20 */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', '+', +/* F, ‘S,SftL, n, ‚y, ‚w, ‚b, ‚u, 0x28 */ + 0x2a,0x00,0x00, '}', 'Z', 'X', 'C', 'V', +/* ‚a, ‚m, ‚l, C, D, ^,SftR, [*], 0x30 */ + 'B', 'N', 'M', '<', '>',0x3f,0x00,0x2a, +/* Alt, SPC, Cap, f.1, f.2, f.3, f.4, f.5, 0x38 */ + 0x00, ' ',0x00, 'v', 'w', 'x', 'y', 'z', +/* f.6, f.7, f.8, f.9,f.10,Paus, ???, [7], 0x40 */ + 0x00,0x00,0x00,0x00,0x00,0x03,0x00, '7', +/* [8], [9], [-], [4], [5], [6], [+], [1], 0x48 */ + '8', '9', '-', '4', '5', '6', '+', '1', +/* [2], [3], [0], [.], ???, ???, ???,f.11, 0x50 */ + '2', '3', '0', '.',0x00,0x00,0x00,0x00, +/*f.12, _ , \ ,RLUP,RLDN,<>,XFER, END, 0x58 */ + 0x00, '_', '|',0x0e,0x0f, '=',0xfe,0x11, +}; + +// GRPH (Alt) +BYTE CHR_TBL2[]={ +/* -- , ESC, ‚P, ‚Q, ‚R, ‚S, ‚T, ‚U, 0x00 */ + 0x00,0x00,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6, +/* ‚V, ‚W, ‚X, ‚O, |, O, BS, TAB, 0x08 */ + 0xf7,0xf8,0xf9,0xfa,0x8c,0x8b,0x00,0x00, +/* ‚p, ‚v, ‚d, ‚q, ‚s, ‚x, ‚t, ‚h, 0x10 */ + 0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, +/* ‚n, ‚o, —, m, Ent,Ctrl, ‚`, ‚r, 0x18 */ + 0xf0,0x8d,0x8a,0xfc,0x00,0x00,0x7f,0xe9, +/* ‚c, ‚e, ‚f, ‚g, ‚i, ‚j, ‚k, G, 0x20 */ + 0xea,0xeb,0xec,0xed,0xee,0xef,0x8e,0x89, +/* F, ‘S,SftL, n, ‚y, ‚w, ‚b, ‚u, 0x28 */ + 0xfd,0x00,0x00,0xe8,0x80,0x81,0x82,0x83, +/* ‚a, ‚m, ‚l, C, D, ^,SftR, [*], 0x30 */ + 0x84,0x85,0x86,0x87,0x88,0xfe,0x00,0x9b, +/* Alt, SPC, Cap, f.1, f.2, f.3, f.4, f.5, 0x38 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/* f.6, f.7, f.8, f.9,f.10,Paus, ???, [7], 0x40 */ + 0x00,0x00,0x00,0x00,0x00,0x13,0x00,0x9a, +/* [8], [9], [-], [4], [5], [6], [+], [1], 0x48 */ + 0x93,0x97,0x9c,0x95,0x96,0x94,0x9d,0x99, +/* [2], [3], [0], [.], ???, ???, ???,f.11, 0x50 */ + 0x92,0x98,0x8f,0x91,0x00,0x00,0x00,0x00, +/*f.12, _ , \ ,RLUP,RLDN,<>,XFER, END, 0x58 */ + 0x00,0xff,0xfb,0x0e,0x0f,0x90,0xfe,0x11, +}; + +// CTRL +BYTE CHR_TBL3[]={ +/* -- , ESC, ‚P, ‚Q, ‚R, ‚S, ‚T, ‚U, 0x00 */ + 0x00,0x1b, '1', '2', '3', '4', '5', '6', +/* ‚V, ‚W, ‚X, ‚O, |, O, BS, TAB, 0x08 */ + '7', '8', '9', '0',0x00,0x1e,0x08,0x09, +/* ‚p, ‚v, ‚d, ‚q, ‚s, ‚x, ‚t, ‚h, 0x10 */ + 0x11,0x17,0x05,0x12,0x14,0x19,0x15,0x09, +/* ‚n, ‚o, —, m, Ent,Ctrl, ‚`, ‚r, 0x18 */ + 0x0f,0x10, '@',0x1b,0x0d,0x00,0x01,0x13, +/* ‚c, ‚e, ‚f, ‚g, ‚i, ‚j, ‚k, G, 0x20 */ + 0x04,0x06,0x07,0x08,0x0a,0x0b,0x0c, ';', +/* F, ‘S,SftL, n, ‚y, ‚w, ‚b, ‚u, 0x28 */ + ':',0x00,0x1c,0x1d,0x1a,0x18,0x03,0x16, +/* ‚a, ‚m, ‚l, C, D, ^,SftR, [*], 0x30 */ + 0x02,0x0e,0x0d,0x00,0x00,0x00,0x00,0x2a, +/* Alt, SPC, Cap, f.1, f.2, f.3, f.4, f.5, 0x38 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/* f.6, f.7, f.8, f.9,f.10,Paus, ???, [7], 0x40 */ + 0xec,0xeb,0xe2,0xe1,0x00,0x03,0x00, '7', +/* [8], [9], [-], [4], [5], [6], [+], [1], 0x48 */ + '8', '9', '-', '4', '5', '6', '+', '1', +/* [2], [3], [0], [.], ???, ???, ???,f.11, 0x50 */ + '2', '3', '0', '.',0x00,0x00,0x00,0x00, +/*f.12, _ , \ ,RLUP,RLDN,<>,XFER, END, 0x58 */ + 0x00,0x00,0x1c,0x0e,0x0f, '=',0xfe,0x11, +}; + +// ¶Å +BYTE CHR_TBL4[]={ +/* -- , ESC, ‚P, ‚Q, ‚R, ‚S, ‚T, ‚U, 0x00 */ + 0x00,0x1b, 'Ç', 'Ì', '±', '³', '´', 'µ', +/* ‚V, ‚W, ‚X, ‚O, |, O, BS, TAB, 0x08 */ + 'Ô', 'Õ', 'Ö', 'Ü', 'Î', 'Í',0x08,0x09, +/* ‚p, ‚v, ‚d, ‚q, ‚s, ‚x, ‚t, ‚h, 0x10 */ + 'À', 'Ã', '²', '½', '¶', 'Ý', 'Å', 'Æ', +/* ‚n, ‚o, —, m, Ent,Ctrl, ‚`, ‚r, 0x18 */ + '×', '¾', 'Þ', 'ß',0x0d,0x00, 'Á', 'Ä', +/* ‚c, ‚e, ‚f, ‚g, ‚i, ‚j, ‚k, G, 0x20 */ + '¼', 'Ê', '·', '¸', 'Ï', 'É', 'Ø', 'Ú', +/* F, ‘S,SftL, n, ‚y, ‚w, ‚b, ‚u, 0x28 */ + '¹',0x00,0x00, 'Ñ', 'Â', '»', '¿', 'Ë', +/* ‚a, ‚m, ‚l, C, D, ^,SftR, [*], 0x30 */ + 'º', 'Ð', 'Ó', 'È', 'Ù', 'Ò',0x00,0x2a, +/* Alt, SPC, Cap, f.1, f.2, f.3, f.4, f.5, 0x38 */ + 0x00,0x20,0x00, 'q', 'r', 's', 't', 'u', +/* f.6, f.7, f.8, f.9,f.10,Paus, ???, [7], 0x40 */ + 0xec,0xeb,0xe2,0xe1,0x00,0x13,0x00, '7', +/* [8], [9], [-], [4], [5], [6], [+], [1], 0x48 */ + '8', '9', '-', '4', '5', '6', '+', '1', +/* [2], [3], [0], [.], ???, ???, ???,f.11, 0x50 */ + '2', '3', '0', '.',0x00,0x00,0x00,0x00, +/*f.12, _ , \ ,RLUP,RLDN,<>,XFER, END, 0x58 */ + 0x00, 'Û', '°',0x0e,0x0f, '=',0xfe,0x11, +}; + +// ¶Å+¼ÌÄ +BYTE CHR_TBL5[]={ +/* -- , ESC, ‚P, ‚Q, ‚R, ‚S, ‚T, ‚U, 0x00 */ + 0x00,0x1b, 'Ç', 'Ì', '§', '©', 'ª', '«', +/* ‚V, ‚W, ‚X, ‚O, |, O, BS, TAB, 0x08 */ + '¬', '­', '®', '¦', 'Î', 'Í',0x12,0x09, +/* ‚p, ‚v, ‚d, ‚q, ‚s, ‚x, ‚t, ‚h, 0x10 */ + 'À', 'Ã', '¨', '½', '¶', 'Ý', 'Å', 'Æ', +/* ‚n, ‚o, —, m, Ent,Ctrl, ‚`, ‚r, 0x18 */ + '×', '¾', 'Þ', '¢',0x0d,0x00, 'Á', 'Ä', +/* ‚c, ‚e, ‚f, ‚g, ‚i, ‚j, ‚k, G, 0x20 */ + '¼', 'Ê', '·', '¸', 'Ï', 'É', 'Ø', 'Ú', +/* F, ‘S,SftL, n, ‚y, ‚w, ‚b, ‚u, 0x28 */ + '¹',0x00,0x00, '£', '¯', '»', '¿', 'Ë', +/* ‚a, ‚m, ‚l, C, D, ^,SftR, [*], 0x30 */ + 'º', 'Ð', 'Ó', '¤', '¡', '¥',0x00,0x2a, +/* Alt, SPC, Cap, f.1, f.2, f.3, f.4, f.5, 0x38 */ + 0x00, ' ',0x00, 'v', 'w', 'x', 'y', 'z', +/* f.6, f.7, f.8, f.9,f.10,Paus, ???, [7], 0x40 */ + 0x00,0x00,0x00,0x00,0x00,0x03,0x00, '7', +/* [8], [9], [-], [4], [5], [6], [+], [1], 0x48 */ + '8', '9', '-', '4', '5', '6', '+', '1', +/* [2], [3], [0], [.], ???, ???, ???,f.11, 0x50 */ + '2', '3', '0', '.',0x00,0x00,0x00,0x00, +/*f.12, _ , \ ,RLUP,RLDN,<>,XFER, END, 0x58 */ + 0x00, 'Û', '°',0x0e,0x0f, '=',0xfe,0x11, +}; + +#pragma section rom rom + +#ifdef __cplusplus +} +#endif +#endif // KEYTABLE_H diff --git a/main.c b/main.c new file mode 100644 index 0000000..1e9557f --- /dev/null +++ b/main.c @@ -0,0 +1,214 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: main.c +// Created: Jan 2022 +// Version: v1.0 +// Author(s): Philip Smart +// Description: X1 Keyboard logic. +// This source file was originally written by Sato Kyoichi and has been translated and +// changes made to accommodate the updated hardware key. Please see this repository +// for the original source if needed. +// It contains the startup code to configure the I/O and timers, initialise the sub- +// modules and then start key conversion, incoming keys are mapped realtime and sent +// immediately to the X1. +// Credits: Kyoichi Sato http://kyoutan.jpn.org/ - Firmware based on and uses components of +// X1Keybord by Kyoichi Sato. +// Copyright: Changes from original source (c) 2022 Philip Smart +// +// History: Jan 2022 - Initial write. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus + extern "C" { +#endif + +#include "sfr_r8m12a.h" +#include "iodefine.h" +#include "x1key.h" +#include "ps2.h" +#include "timer.h" +#include "keyconv.h" +#include "main.h" + +void main(void) +{ + // Locals. + int idx; + unsigned long idx2; + + // Disable interrupts during config to prevent spurious triggers. + DI(); + + // Initialise the oscillator, use internal 18.432MHz clock. + osc_init(); + + // Initialise all the I/O ports, default interrupts/level and timer settings. + io_init(); + + // Start the PS/2 timer. + timer_start(); + +/* + // PS / 2 lead test + while (TRUE) + { + puth2 (ps2get ()); + // puth2 (PS2RPOS); + // puth2 (PS2WPOS); + } +*/ + +/* + // X1 delivery test + { + unsigned short a = 0; + unsigned char b = 0x20; + + while (TRUE) + { + if (10 <(TIMER-a)) // Every second + { + a = TIMER; + + X1_send (((unsigned short) 0b10111111 << 8) + b); // Press + X1_send (((unsigned short) 0b11111111 << 8) + 0x00); // Release + + if (0x7F == b) + { + b = 0x20; + } + else + { + b ++; + } + } + } + } +*/ + + // Enable interrupts as we are ready to process PS/2 data -> MZ-2500/2800. + EI(); + + // Feel good factor, show the unit is working by blinking LED. + for(idx=0; idx < 10; idx++) + { + LED = OFF; + for(idx2=0; idx2 < 100000; idx2++); + LED = ON; + for(idx2=0; idx2 < 100000; idx2++); + } + LED = OFF; + + // Key conversion. PS/2 data arrives via interrupt, X1 data is sent via interrupt. + while(TRUE) + { + keyconv(); + } +} + +void osc_init(void) +{ + // Switch to built-in high speed oscillator + prc0 = 1; // Clock register permission + ococr = 0b00000001; // High-speed on-chip oscillator oscillation Low-speed oscillation + { + unsigned char a; + for (a = 0; a <255; a ++) asm ("nop"); // Wait for the oscillator oscillation to stabilize, so wait for an appropriate amount of time. + } + sckcr = 0b01000000; // Select high speed by selecting XIN / high speed oscillator No CPU clock division + ckstpr = 0b10000000; // Select high speed by system clock low speed / high speed selection + phisel = 0x00; // No system clock division + frv1 = fr18s0; // Adjust high speed on-chip oscillator to 18.432MHz + frv2 = fr18s1; + prc0 = 0; // Clock register access prohibited +} + +void io_init(void) +{ + // I/O ports available on processor and applicable use. + // + // P1_0 LED - 1 = Light LED, 0 = LED off. + // P1_1 PS2_CLK_OUT - Clock output to PS/2 keyboard (used to pull clock low as keyboard generates actual clock). + // P1_2 + // P1_3 + // P1_4 TXD - for writing / communication + // P1_5 RXD - communication (TRJIO) + // P1_6 RXD - for writing (TRJO) + // P1_7 + + // P3_3 PS2_DATA_IN - (/INT3) Input data from PS/2 keyboard. + // P3_4 + // P3_5 + // P3_7 X1DATA - used when hardware converts PS/2 to X1 data stream. (TRJ0) + + // P4_2 PS2_DATA_OUT - Output data to PS/2 keyboard. + // P4_5 PS2_CLK_IN(/INT0) - Clock intput from PS/2 keyboard. + // P4_6 + // P4_7 + + // PA_0 /RESET + + // Setup default pin value. + X1KEYOUT = 1; + p1_4 = 1; // TXD + + // Port orientation 0: Input, 1: Output + pd1 = 0b00011111; // P1_5 P1_6 RXD are inputs. LED, PS2_CLK_OUT, TXD are outputs. + pd3 = 0b11110111; // P3_7 TRJO X1KEYOUT output | P3_3 PS/2 DATA input + pd4 = 0b11011111; // P4_5 INT0 PS/2 CLK input + + // Pull up 0: No. 1: Yes + pur1 = 0b01100000; // RXD + pur3 = 0b00001000; // PS2_DATA_IN + pur4 = 0b00100000; // PS2_CLK_IN + + // Open drain output 1: Yes + pod1 = 0b00000000; + pod3 = 0b00001000; + pod4 = 0b00100000; + + // Initialise the sub modules for data in/out. + x1key_init (); + ps2key_init (); + timer_init (); + + // Interrupt priority level + // CAUTION: It takes more than 20 cycles to respond to interrupts. ie. 1uS at 20MHz + ilvlb = 0x01; // TIMER RJ 1 + ilvlc = 0x01; // TIMER RB 1 + ilvle = 0x20; // INT0 2 Higher priority than TIMER RJ + + // Processor interrupt priority level 0 (interrupts higher than this value are accepted) + asm ("LDIPL # 0"); + + // Port mapping + pml1 = 0b00000000; // P1_0 I/O Port for LED control. + pmh1 = 0b00000101; // P1_4: TXD P1_5: RXD + pmh1e = 0b00000000; + pml3 = 0b00000000; + pmh3 = 0b10000000; // P3_7 TRJO X1KEYOUT + pml4 = 0b00000000; + pmh4 = 0b00000100; // P4_5 INT0 PS / 2 CLK + pmh4e = 0b00010000; // P4_6 Enhanced bit to 0 + pamcr = 0b00010001; // PA reset +} + +#ifdef __cplusplus +} +#endif diff --git a/main.h b/main.h new file mode 100644 index 0000000..9e6e291 --- /dev/null +++ b/main.h @@ -0,0 +1,58 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: main.h +// Created: Jan 2022 +// Version: v1.0 +// Author(s): Philip Smart +// Description: X1 Keyboard logic. +// This source file was originally written by Sato Kyoichi and has been translated and +// changes made to accommodate the updated hardware key. Please see this repository +// for the original source if needed. +// It contains the startup code to configure the I/O and timers, initialise the sub- +// modules and then start key conversion, incoming keys are mapped realtime and sent +// immediately to the X1. +// Credits: Kyoichi Sato http://kyoutan.jpn.org/ - Firmware based on and uses components of +// X1Keybord by Kyoichi Sato. +// Copyright: Changes from original source (c) 2022 Philip Smart +// +// History: Jan 2022 - Initial write. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#ifndef MAIN_H +#define MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +#pragma section rom flash_data + +// Version string. +const char VERSION[] = "v1.0"; + +#pragma section rom rom + +// Prototypes. +void main(void); +void osc_init(void); +void io_init(void); + +#ifdef __cplusplus +} +#endif +#endif // MAIN_H diff --git a/nc_define.inc b/nc_define.inc new file mode 100644 index 0000000..ec059e2 --- /dev/null +++ b/nc_define.inc @@ -0,0 +1,15 @@ +;------------------------------------------------------------------------ +; | +; FILE :nc_define.inc | +; DATE :Wed, Jul 16, 2014 | +; DESCRIPTION :interrupt program. | +; CPU GROUP :M12A | +; | +; This file is generated by Renesas Project Generator (Ver.4.19). | +; NOTE:THIS IS A TYPICAL EXAMPLE. | +;------------------------------------------------------------------------ +; Macro Symbol definition +__STANDARD_IO__ .equ 0 ; STANDARD I/O flag definition +__HEAPSIZE__ .equ 0H ; HEEP SIZE definition +__STACKSIZE__ .equ 080H ; STACK SIZE definition +__ISTACKSIZE__ .equ 080H ; INTERRUPT STACK SIZE definition diff --git a/ncrt0.a30 b/ncrt0.a30 new file mode 100644 index 0000000..7ec0276 --- /dev/null +++ b/ncrt0.a30 @@ -0,0 +1,139 @@ +;---------------------------------------------------------------------- +; | +; | +; | +; DESCRIPTION : Startup Program. (for Assembler language) | +; | +; | +; This file is generated by Renesas Project Generator. | +; | +;---------------------------------------------------------------------- +;/********************************************************************* +;* +;* Device : R8C Family +;* +;* File Name : ncrt0.a30 +;* +;* Abstract : Startup Program +;* +;* History : 1.01 (2006-11-22) +;* +;* NOTE : THIS IS A TYPICAL EXAMPLE. +;* +;* Copyright (C) 2006 Renesas Electronics Corporation. +;* and Renesas Solutions Corp. +;* +;*********************************************************************/ +;--------------------------------------------------------------------- +; include files +;--------------------------------------------------------------------- + .list OFF + .include nc_define.inc + .include sect30.inc + .list ON + +;===================================================================== +; Interrupt section start +;--------------------------------------------------------------------- + .glb start + .section interrupt,CODE,ALIGN + .insf start,G,0 +start: +;--------------------------------------------------------------------- +; after reset,this program will start +;--------------------------------------------------------------------- + ldc #((topof istack)+(sizeof istack)),isp ;set istack pointer + mov.b #02h,0ah + mov.b #00h,04h ;set processer mode + mov.b #00h,0ah +.if __STACKSIZE__ != 0 + ldc #0080h,flg + ldc #((topof stack)+(sizeof stack)),sp ;set stack pointer +.else + ldc #0000h,flg +.endif + ldc #__SB__,sb ;set sb register + + ; If the destination is INTBL or INTBH, + ; make sure that bytes are transferred in succession. + ldc #((topof vector)>>16)&0FFFFh,INTBH + ldc #(topof vector)&0FFFFh,INTBL + +;===================================================================== +; NEAR area initialize. +;--------------------------------------------------------------------- +; bss zero clear +;--------------------------------------------------------------------- + N_BZERO (topof bss_SE),bss_SE + N_BZERO (topof bss_SO),bss_SO + N_BZERO (topof bss_NE),bss_NE + N_BZERO (topof bss_NO),bss_NO + +;--------------------------------------------------------------------- +; initialize data section +;--------------------------------------------------------------------- + N_BCOPY (topof data_SEI),(topof data_SE),data_SE + N_BCOPY (topof data_SOI),(topof data_SO),data_SO + N_BCOPY (topof data_NEI),(topof data_NE),data_NE + N_BCOPY (topof data_NOI),(topof data_NO),data_NO + +;===================================================================== +; heap area initialize +;--------------------------------------------------------------------- +.if __HEAPSIZE__ != 0 + .glb __mnext + .glb __msize + mov.w #((topof heap_NE)&0FFFFH),__mnext + mov.w #(__HEAPSIZE__&0FFFFH),__msize +.endif + +;===================================================================== +; Initialize standard I/O +;--------------------------------------------------------------------- +.if __STANDARD_IO__ == 1 + .glb __init + .call __init,G + jsr.a __init +.endif + +;===================================================================== +; Call main() function +;--------------------------------------------------------------------- + ldc #0h,fb ; for debuger + +; Remove the comment when you use global class object +; Sections C$INIT will be generated +; .glb __CALL_INIT +; .call __CALL_INIT,G +; jsr.a __CALL_INIT + + .glb _main + .call _main,G + jsr.a _main + +;===================================================================== +; exit() function +;--------------------------------------------------------------------- + .glb _exit + .glb $exit + .glb __exit_loop +_exit: +$exit: + +; Remove the comment when you use global class object +; Sections C$INIT will be generated +; .glb __CALL_END +; .call __CALL_END,G +; jsr.a __CALL_END + +__exit_loop: ; End program + jmp __exit_loop + .einsf +;===================================================================== +; dummy interrupt function +;--------------------------------------------------------------------- + .glb dummy_int +dummy_int: + reit + + .end diff --git a/ps2.c b/ps2.c new file mode 100644 index 0000000..5c45bb8 --- /dev/null +++ b/ps2.c @@ -0,0 +1,186 @@ +/* + Connect a PS / 2 keyboard to SHARP X1 + PS / 2 keyboard reception processing + + It's easy because you only read one bit at a time at the falling edge of the clock. + Start bit 1 + Data bit 8 + Parity bit 1 + Stop bit 1 + + 11-bit odd parity in total + I wrote the key code sent to me at http://kyoutan.jpn.org/uts/pc/pic/x68key/. + + + + Created July 22, 2014 + + Kyoichi Sato http://kyoutan.jpn.org/ + + There is no guarantee. + The part created by Kyoichi Sato has no restrictions on its use. You can use it freely regardless of whether it is commercial or non-commercial. + It means that you can copy, modify, distribute, or sell it without permission. + No need to contact. +*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "sfr_r8m12a.h" +#include "ps2.h" +#include "iodefine.h" + +volatile unsigned short PS2TIMER = 0; // PS2 receive timeout timer +volatile unsigned char PS2BUFF [PS2BUFFSIZE]; // PS2 receive buffer +volatile unsigned char PS2RPOS = 0; // PS2 read position +volatile unsigned char PS2WPOS = 0; // PS2 write position + +void ps2key_init(void) +{ + /* INT0 External interrupt initialization */ + // INT0 PS / 2 CLOCK + intf0 = 0b00000001; // Use INT0 f1 filter 1 * 3 / 18.432 = 0.16us + iscr0 = 0b00000000; // INT0 Falling edge + inten = 0b00000001; // INT0 input permission + { + unsigned char a; + for (a = (6 * 8); a != 0; a--) asm ("nop"); // Wait a minute + } + // PMLi PMHi ISCR0 INTEN KIEN Rewriting the register may set the interrupt request flag to 1. + // is written in the manual, so clear the flag + while (1 == iri0) iri0 = 0; +} + +// External interrupt INT0 +// Interrupt at the fall of PS / 2 CLOCK and capture data bit by bit +#pragma INTERRUPT INT_int0 (vect = 29) +void INT_int0(void) +{ + static unsigned short bit = 1; + static unsigned short data = 0; + static unsigned char parity = 0; + + // If the reception is stopped, clear the status and receive from the beginning + if ((bit != 1) && (PS2TIMEOUT ps2size ()) // Is there a free buffer? + { + PS2BUFF [PS2WPOS] = ((data >> 1) & 0xFF); + + if ((PS2BUFFSIZE-1)> PS2WPOS) + { + PS2WPOS++; + } + else + { + PS2WPOS = 0; + } + } + else + { + // Buffer full + } + } + else + { + // Parity error + } + + bit = 1; + data = 0; + parity = 0; + LED = OFF; + } + else + { + if ((1 == bit) && (data != 0)) + {// start bit is not zero state reset + bit = 1; + data = 0; + parity = 0; + } + else + {// Ready to read the next bit + bit = (bit << 1); + PS2TIMER = 0; // Clear timeout timer + } + } + + while (1 == iri0) iri0 = 0; // The interrupt flag is automatically cleared, so you don't have to do this line. +} + +// Returns the number of valid data in the buffer +unsigned char ps2size(void) +{ +signed int size; + + size = (signed int) PS2WPOS-PS2RPOS; + if (0> size) + { + size = PS2BUFFSIZE + size; + } + + return size; + // size = 5 wpos = 2 rpos = 3 4 +} + +// Clear the receive buffer +void ps2clear (void) +{ + PS2WPOS = 0; + PS2RPOS = 0; + PS2BUFF [PS2RPOS] = 0; +} + +// Read 1 byte from the buffer +unsigned char ps2read(void) +{ + unsigned char data = 0; + + if (PS2WPOS != PS2RPOS) // Is there data in the buffer? + { + data = PS2BUFF [PS2RPOS]; + + if ((PS2BUFFSIZE-1)> PS2RPOS) + { + PS2RPOS++; + } + else + { + PS2RPOS = 0; + } + } + return data; +} + +// Wait until it is received and read 1 byte +unsigned char ps2get(void) +{ + while (0 == ps2size ()); // Wait until the buffer is filled with data + return ps2read (); +} + +#ifdef __cplusplus +} +#endif diff --git a/ps2.h b/ps2.h new file mode 100644 index 0000000..669b7f9 --- /dev/null +++ b/ps2.h @@ -0,0 +1,40 @@ +/* + Connect a PS / 2 keyboard to SHARP X1 + PS / 2 keyboard reception processing + + Created July 22, 2014 + + Kyoichi Sato http://kyoutan.jpn.org/ + + There is no guarantee. + The part created by Kyoichi Sato has no restrictions on its use. You can use it freely regardless of whether it is commercial or non-commercial. + It means that you can copy, modify, distribute, or sell it without permission. + No need to contact. +*/ + +#ifndef PS2_H +#define PS2_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#define PS2TIMEOUT 30 // PS2 timeout 30 * 100 [ms] = 3 [s] +#define PS2BUFFSIZE 0x10 + +extern volatile unsigned short PS2TIMER; // PS2 receive timeout timer +// extern volatile unsigned char PS2BUFF [PS2BUFFSIZE]; // PS2 receive buffer +// extern volatile unsigned char PS2RPOS; // PS2 read position +// extern volatile unsigned char PS2WPOS; // PS2 write position + +void ps2key_init(void); +unsigned char ps2size(void); +void ps2clear(void); +unsigned char ps2read(void); +unsigned char ps2get(void); + +#ifdef __cplusplus +} +#endif +#endif // PS2_H diff --git a/sect30.inc b/sect30.inc new file mode 100644 index 0000000..c951df5 --- /dev/null +++ b/sect30.inc @@ -0,0 +1,157 @@ +;---------------------------------------------------------------------- +; | +; | +; | +; DESCRIPTION : Section definition. (for Assembler language) | +; | +; | +; This file is generated by Renesas Project Generator. | +; | +;---------------------------------------------------------------------- +;/********************************************************************* +;* +;* Device : R8C/Mx +;* +;* File Name : sect30.inc +;* +;* Abstract : Section definition +;* +;* History : 1.00 (2011-02-01) +;* +;* NOTE : THIS IS A TYPICAL EXAMPLE. +;* +;* Copyright (C) 2011 Renesas Electronics Corporation. and +;* Renesas Solutions Corp. All rights reserved. +;* +;*********************************************************************/ + +;===================================================================== +; +; Definition of section +; +;--------------------------------------------------------------------- +; Near RAM data area +;--------------------------------------------------------------------- +; SBDATA area + .section data_SE,DATA,ALIGN + .section bss_SE,DATA,ALIGN + .section data_SO,DATA + .section bss_SO,DATA + +; SBDATA area definition +; Sets the top address (__SB__) of the SBDATA area +; (it is accessing area to used the SBrelative addressing mode). + .glb __SB__ +__SB__ .equ 400H + +; near RAM area + .section data_NE,DATA,ALIGN + .section bss_NE,DATA,ALIGN + .section data_NO,DATA + .section bss_NO,DATA + +;--------------------------------------------------------------------- +; Stack area +;--------------------------------------------------------------------- +.if __STACKSIZE__ != 0 + .section stack,DATA,ALIGN + .blkb __STACKSIZE__ +.endif + + .section istack,DATA,ALIGN + .blkb __ISTACKSIZE__ + +;--------------------------------------------------------------------- +; heap section +;--------------------------------------------------------------------- +.if __HEAPSIZE__ != 0 + .section heap_NE,DATA,ALIGN + .blkb __HEAPSIZE__ +.endif + +;--------------------------------------------------------------------- +; Initial data of 'data' section +;--------------------------------------------------------------------- + .section data_SEI,ROMDATA + .section data_SOI,ROMDATA + .section data_NEI,ROMDATA + .section data_NOI,ROMDATA + +;--------------------------------------------------------------------- +; variable vector section +;--------------------------------------------------------------------- + .section vector,ROMDATA,ALIGN + +; When you use "#pragma interrupt" with "vect=", +; you need not define interrupt vector. +; +; When you use "#pragma interrupt" without "vect=", +; you must define all interrupt vectors like the following example. +; You define dummy_int for interrupt vector not used. +; +; .lword dummy_int ; vector 0 +; .lword dummy_int ; vector 1 +; .lword dummy_int ; vector 2 +; : +; .lword dummy_int ; vector 63 + +;--------------------------------------------------------------------- +; fixed vector section +;--------------------------------------------------------------------- + .section fvector,ROMDATA + .org 0ffd8H +; reserved + .addr 0FFFFFFH +; OFS2 + .byte 0FFH +UDI: + .lword dummy_int +OVER_FLOW: + .lword dummy_int +BRKI: + .lword dummy_int +ADDRESS_MATCH: + .lword dummy_int +SINGLE_STEP: + .lword dummy_int +WDT: + .lword dummy_int +; reserved + .lword dummy_int +; reserved + .lword dummy_int +RESET: + .lword start + +;===================================================================== +; ID code & Option function select register +;--------------------------------------------------------------------- +; ID code check function + .id "#FFFFFFFFFFFFFF" + +; option function select register + .ofsreg 0FFH + +;--------------------------------------------------------------------- +; far ROM data area +;--------------------------------------------------------------------- +; .section data_FEI,ROMDATA +; .section data_FOI,ROMDATA + +;===================================================================== +; Initialize Macro declaration +;--------------------------------------------------------------------- +N_BZERO .macro TOP_ ,SECT_ + mov.b #00H, R0L + mov.w #(TOP_ & 0FFFFH), A1 + mov.w #sizeof SECT_ , R3 + sstr.b + .endm + +N_BCOPY .macro FROM_,TO_,SECT_ + mov.w #(FROM_ & 0FFFFH),A0 + mov.b #(FROM_ >>16),R1H + mov.w #TO_ ,A1 + mov.w #sizeof SECT_ , R3 + smovf.b + .endm diff --git a/sfr_r8m12a.h b/sfr_r8m12a.h new file mode 100644 index 0000000..5a6d492 --- /dev/null +++ b/sfr_r8m12a.h @@ -0,0 +1,1772 @@ +/***********************************************************************/ +/* */ +/* */ +/* */ +/* DESCRIPTION :define the sfr register. (for C language) */ +/* */ +/* */ +/* This file is generated by Renesas Project Generator. */ +/* */ +/***********************************************************************/ +/************************************************************************ +* +* Device : R8C/M12A +* +* File Name : sfr_r8m12a.h +* +* Abstract : definition of R8C/M12A Group SFR +* +* History : 2.00 ( 2010-12-03 ) [User's Manual: Hardware Rev.1.00] +* : 1.10 ( 2010-06-18 ) [User's Manual: Hardware Rev.0.10] +* : 1.00 ( 2010-02-26 ) [User's Manual: Hardware Rev.0.01] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2010 Renesas Electronics Corporation. +* and Renesas Solutions Corp. +* +*************************************************************************/ + +/******************************************************** +* declare SFR addresses * +********************************************************/ + +#pragma ADDRESS pm0_addr 0010H /* Processor Mode Register 0 */ + +#pragma ADDRESS mstcr_addr 0012H /* Module Standby Control Register */ + +#pragma ADDRESS prcr_addr 0013H /* Protect Register */ + +#pragma ADDRESS hrpr_addr 0016H /* Hardware Reset Protect Register */ + +#pragma ADDRESS exckcr_addr 0020H /* External Clock Control Register */ + +#pragma ADDRESS ococr_addr 0021H /* High-Speed/Low-Speed On-Chip Oscillator Control Register */ + +#pragma ADDRESS sckcr_addr 0022H /* System Clock f Control Register */ + +#pragma ADDRESS phisel_addr 0023H /* System Clock f Select Register */ + +#pragma ADDRESS ckstpr_addr 0024H /* Clock Stop Control Register */ + +#pragma ADDRESS ckrscr_addr 0025H /* Clock Control Register When Returning from Modes */ + +#pragma ADDRESS bakcr_addr 0026H /* Oscillation Stop Detection Register */ + +#pragma ADDRESS risr_addr 0030H /* Watchdog Timer Function Register */ + +#pragma ADDRESS wdtr_addr 0031H /* Watchdog Timer Reset Register */ + +#pragma ADDRESS wdts_addr 0032H /* Watchdog Timer Start Register */ + +#pragma ADDRESS wdtc_addr 0033H /* Watchdog Timer Control Register */ + +#pragma ADDRESS cspr_addr 0034H /* Count Source Protection Mode Register */ + +#pragma ADDRESS wdtir_addr 0035H /* Periodic Timer Interrupt Control Register */ + +#pragma ADDRESS inten_addr 0038H /* External Input Enable Register */ + +#pragma ADDRESS intf0_addr 003AH /* INT Input Filter Select Register 0 */ + +#pragma ADDRESS iscr0_addr 003CH /* INT Input Edge Select Register 0 */ + +#pragma ADDRESS kien_addr 003EH /* Key Input Enable Register */ + +#pragma ADDRESS ilvl0_addr 0040H /* Interrupt Priority Level Register 0 */ + +#pragma ADDRESS ilvl2_addr 0042H /* Interrupt Priority Level Register 2 */ + +#pragma ADDRESS ilvl3_addr 0043H /* Interrupt Priority Level Register 3 */ + +#pragma ADDRESS ilvl4_addr 0044H /* Interrupt Priority Level Register 4 */ + +#pragma ADDRESS ilvl5_addr 0045H /* Interrupt Priority Level Register 5 */ + +#pragma ADDRESS ilvl6_addr 0046H /* Interrupt Priority Level Register 6 */ + +#pragma ADDRESS ilvl7_addr 0047H /* Interrupt Priority Level Register 7 */ + +#pragma ADDRESS ilvl8_addr 0048H /* Interrupt Priority Level Register 8 */ + +#pragma ADDRESS ilvl9_addr 0049H /* Interrupt Priority Level Register 9 */ + +#pragma ADDRESS ilvla_addr 004AH /* Interrupt Priority Level Register A */ + +#pragma ADDRESS ilvlb_addr 004BH /* Interrupt Priority Level Register B */ + +#pragma ADDRESS ilvlc_addr 004CH /* Interrupt Priority Level Register C */ + +#pragma ADDRESS ilvld_addr 004DH /* Interrupt Priority Level Register D */ + +#pragma ADDRESS ilvle_addr 004EH /* Interrupt Priority Level Register E */ + +#pragma ADDRESS irr0_addr 0050H /* Interrupt Monitor Flag Register 0 */ + +#pragma ADDRESS irr1_addr 0051H /* Interrupt Monitor Flag Register 1 */ + +#pragma ADDRESS irr2_addr 0052H /* Interrupt Monitor Flag Register 2 */ + +#pragma ADDRESS irr3_addr 0053H /* External Interrupt Flag Register */ + +#pragma ADDRESS vcac_addr 0058H /* Voltage Monitor Circuit Edge Select Register */ + +#pragma ADDRESS vca2_addr 005AH /* Voltage Detect Register 2 */ + +#pragma ADDRESS vd1ls_addr 005BH /* Voltage Detection 1 Level Select Register */ + +#pragma ADDRESS vw0c_addr 005CH /* Voltage Monitor 0 Circuit Control Register */ + +#pragma ADDRESS vw1c_addr 005DH /* Voltage Monitor 1 Circuit Control Register */ + +#pragma ADDRESS rstfr_addr 005FH /* Reset Source Determination Register */ + +#pragma ADDRESS fr18s0_addr 0064H /* High-Speed On-Chip Oscillator 18.432 MHz Control Register 0 */ + +#pragma ADDRESS fr18s1_addr 0065H /* High-Speed On-Chip Oscillator 18.432 MHz Control Register 1 */ + +#pragma ADDRESS frv1_addr 0067H /* High-Speed On-Chip Oscillator Control Register 1 */ + +#pragma ADDRESS frv2_addr 0068H /* High-Speed On-Chip Oscillator Control Register 2 */ + +#pragma ADDRESS u0mr_addr 0080H /* UART0 Transmit/Receive Mode Register */ + +#pragma ADDRESS u0brg_addr 0081H /* UART0 Bit Rate Register */ + +#pragma ADDRESS u0tbl_addr 0082H /* UART0 Transmit Buffer Register Low */ + +#pragma ADDRESS u0tbh_addr 0083H /* UART0 Transmit Buffer Register Hogh */ + +#pragma ADDRESS u0c0_addr 0084H /* UART0 Transmit/Receive Control Register 0 */ + +#pragma ADDRESS u0c1_addr 0085H /* UART0 Transmit/Receive Control Register 1 */ + +#pragma ADDRESS u0rb_addr 0086H /* UART0 Receive Buffer Register */ + +#pragma ADDRESS u0ir_addr 0088H /* UART0 Interrupt Flag and Enable Register */ + +#pragma ADDRESS ad0_addr 0098H /* A/D Register 0 */ + +#pragma ADDRESS ad1_addr 009AH /* A/D Register 1 */ + +#pragma ADDRESS admod_addr 009CH /* A/D Mode Register */ + +#pragma ADDRESS adinsel_addr 009DH /* A/D Input Select Register */ + +#pragma ADDRESS adcon0_addr 009EH /* A/D Control Register 0 */ + +#pragma ADDRESS adicsr_addr 009FH /* A/D Interrupt Control Status Register */ + +#pragma ADDRESS pd1_addr 00A9H /* Port P1 Direction Register */ + +#pragma ADDRESS pd3_addr 00ABH /* Port P3 Direction Register */ + +#pragma ADDRESS pd4_addr 00ACH /* Port P4 Direction Register */ + +#pragma ADDRESS pda_addr 00ADH /* Port PA Direction Register */ + +#pragma ADDRESS p1_addr 00AFH /* Port P1 Register */ + +#pragma ADDRESS p3_addr 00B1H /* Port P3 Register */ + +#pragma ADDRESS p4_addr 00B2H /* Port P4 Register */ + +#pragma ADDRESS pa_addr 00B3H /* Port PA Register */ + +#pragma ADDRESS pur1_addr 00B5H /* Pull-Up Control Register 1 */ + +#pragma ADDRESS pur3_addr 00B7H /* Pull-Up Control Register 3 */ + +#pragma ADDRESS pur4_addr 00B8H /* Pull-Up Control Register 4 */ + +#pragma ADDRESS pinsr_addr 00B9H /* Port I/O Function Control Register */ + +#pragma ADDRESS drr1_addr 00BBH /* Drive Capacity Control Register 1 */ + +#pragma ADDRESS drr3_addr 00BDH /* Drive Capacity Control Register 3 */ + +#pragma ADDRESS pod1_addr 00C1H /* Open-Drain Control Register 1 */ + +#pragma ADDRESS pod3_addr 00C3H /* Open-Drain Control Register 3 */ + +#pragma ADDRESS pod4_addr 00C4H /* Open-Drain Control Register 4 */ + +#pragma ADDRESS pamcr_addr 00C5H /* Port PA Mode Control Register */ + +#pragma ADDRESS pml1_addr 00C8H /* Port 1 Function Mapping Register 0 */ + +#pragma ADDRESS pmh1_addr 00C9H /* Port 1 Function Mapping Register 1 */ + +#pragma ADDRESS pml3_addr 00CCH /* Port 3 Function Mapping Register 0 */ + +#pragma ADDRESS pmh3_addr 00CDH /* Port 3 Function Mapping Register 1 */ + +#pragma ADDRESS pml4_addr 00CEH /* Port 4 Function Mapping Register 0 */ + +#pragma ADDRESS pmh4_addr 00CFH /* Port 4 Function Mapping Register 1 */ + +#pragma ADDRESS pmh1e_addr 00D1H /* Port 1 Function Mapping Expansion Register */ + +#pragma ADDRESS pmh4e_addr 00D5H /* Port 4 Function Mapping Expansion Register */ + +#pragma ADDRESS trj_addr 00D8H /* Timer RJ Counter Register, Timer RJ Reload Register */ + +#pragma ADDRESS trjcr_addr 00DAH /* Timer RJ Control Register */ + +#pragma ADDRESS trjioc_addr 00DBH /* Timer RJ I/O Control Register */ + +#pragma ADDRESS trjmr_addr 00DCH /* Timer RJ Mode Register */ + +#pragma ADDRESS trjisr_addr 00DDH /* Timer RJ Event Select Register */ + +#pragma ADDRESS trjir_addr 00DEH /* Timer RJ Interrupt Control Register */ + +#pragma ADDRESS trbcr_addr 00E0H /* Timer RB Control Register */ + +#pragma ADDRESS trbocr_addr 00E1H /* Timer RB One-Shot Control Register */ + +#pragma ADDRESS trbioc_addr 00E2H /* Timer RB I/O Control Register */ + +#pragma ADDRESS trbmr_addr 00E3H /* Timer RB Mode Register */ + +#pragma ADDRESS trbpre_addr 00E4H /* Timer RB Prescaler Register */ + +#pragma ADDRESS trbpr_addr 00E5H /* Timer RB Primary Register */ + +#pragma ADDRESS trbsc_addr 00E6H /* Timer RB Secondary Register */ + +#pragma ADDRESS trbir_addr 00E7H /* Timer RB Interrupt Control Register */ + +#pragma ADDRESS trccnt_addr 00E8H /* Timer RC Counter */ + +#pragma ADDRESS trcgra_addr 00EAH /* Timer RC General Register A */ + +#pragma ADDRESS trcgrb_addr 00ECH /* Timer RC General Register B */ + +#pragma ADDRESS trcgrc_addr 00EEH /* Timer RC General Register C */ + +#pragma ADDRESS trcgrd_addr 00F0H /* Timer RC General Register D */ + +#pragma ADDRESS trcmr_addr 00F2H /* Timer RC Mode Register */ + +#pragma ADDRESS trccr1_addr 00F3H /* Timer RC Control Register 1 */ + +#pragma ADDRESS trcier_addr 00F4H /* Timer RC Interrupt Enable Register */ + +#pragma ADDRESS trcsr_addr 00F5H /* Timer RC Status Register */ + +#pragma ADDRESS trcior0_addr 00F6H /* Timer RC I/O Control Register 0 */ + +#pragma ADDRESS trcior1_addr 00F7H /* Timer RC I/O Control Register 1 */ + +#pragma ADDRESS trccr2_addr 00F8H /* Timer RC Control Register 2 */ + +#pragma ADDRESS trcdf_addr 00F9H /* Timer RC Digital Filter Function Select Register */ + +#pragma ADDRESS trcoer_addr 00FAH /* Timer RC Output Enable Register */ + +#pragma ADDRESS trcadcr_addr 00FBH /* Timer RC A/D Conversion Trigger Control Register */ + +#pragma ADDRESS trcopr_addr 00FCH /* Timer RC Waveform Output Manipulation Register */ + +#pragma ADDRESS wcmpr_addr 0180H /* Comparator B Control Register */ + +#pragma ADDRESS wcb1intr_addr 0181H /* Comparator B1 Interrupt Control Register */ + +#pragma ADDRESS wcb3intr_addr 0182H /* Comparator B3 Interrupt Control Register */ + +#pragma ADDRESS fst_addr 01A9H /* Flash Memory Status Register */ + +#pragma ADDRESS fmr0_addr 01AAH /* Flash Memory Control Register 0 */ + +#pragma ADDRESS fmr1_addr 01ABH /* Flash Memory Control Register 1 */ + +#pragma ADDRESS fmr2_addr 01ACH /* Flash Memory Control Register 2 */ + +#pragma ADDRESS frefr_addr 01ADH /* Flash Memory Refresh Control Register */ + +#pragma ADDRESS aiadr0_addr 01C0H /* Address Match Interrupt Register 0 */ + +#pragma ADDRESS aien0_addr 01C3H /* Address Match Interrupt Enable Register 0 */ + +#pragma ADDRESS aiadr1_addr 01C4H /* Address Match Interrupt Register 1 */ + +#pragma ADDRESS aien1_addr 01C7H /* Address Match Interrupt Enable Register 1 */ + +/******************************************************** +* declare SFR union * +********************************************************/ +struct bit_def_b { + unsigned char b0:1; + unsigned char b1:1; + unsigned char b2:1; + unsigned char b3:1; + unsigned char b4:1; + unsigned char b5:1; + unsigned char b6:1; + unsigned char b7:1; +}; + +struct bit_def_w { + unsigned char b0:1; + unsigned char b1:1; + unsigned char b2:1; + unsigned char b3:1; + unsigned char b4:1; + unsigned char b5:1; + unsigned char b6:1; + unsigned char b7:1; + + unsigned char b8:1; + unsigned char b9:1; + unsigned char b10:1; + unsigned char b11:1; + unsigned char b12:1; + unsigned char b13:1; + unsigned char b14:1; + unsigned char b15:1; +}; + +struct bit_def_dw { + unsigned char b0:1; + unsigned char b1:1; + unsigned char b2:1; + unsigned char b3:1; + unsigned char b4:1; + unsigned char b5:1; + unsigned char b6:1; + unsigned char b7:1; + + unsigned char b8:1; + unsigned char b9:1; + unsigned char b10:1; + unsigned char b11:1; + unsigned char b12:1; + unsigned char b13:1; + unsigned char b14:1; + unsigned char b15:1; + + unsigned char b16:1; + unsigned char b17:1; + unsigned char b18:1; + unsigned char b19:1; + unsigned char b20:1; + unsigned char b21:1; + unsigned char b22:1; + unsigned char b23:1; + + unsigned char b24:1; + unsigned char b25:1; + unsigned char b26:1; + unsigned char b27:1; + unsigned char b28:1; + unsigned char b29:1; + unsigned char b30:1; + unsigned char b31:1; +}; + +union byte_def{ + struct bit_def_b bit; + unsigned char byte; +}; + +union word_def{ + struct bit_def_w bit; + struct{ + unsigned char low; /* low 8 bit */ + unsigned char high; /* high 8 bit */ + } byte; + unsigned short word; +}; + +union dword_def{ + struct bit_def_dw bit; + struct{ + unsigned char low; /* low 8 bit */ + unsigned char mid; /* mid 8 bit */ + unsigned char high; /* high 8 bit */ + unsigned char nc; /* non use */ + } byte; + unsigned long dword; +}; +/******************************************************** +* declare SFR bit * +********************************************************/ + +/*------------------------------------------------------ + Processor Mode Register 0 +------------------------------------------------------*/ +union byte_def pm0_addr; +#define pm0 pm0_addr.byte + +#define srst pm0_addr.bit.b3 /* Software reset bit */ + +/*------------------------------------------------------ + Module Standby Control Register +------------------------------------------------------*/ +union byte_def mstcr_addr; +#define mstcr mstcr_addr.byte + +#define msttrj mstcr_addr.bit.b0 /* Timer RJ2 standby bit */ +#define msttrb mstcr_addr.bit.b1 /* Timer RB2 standby bit */ +#define mstad mstcr_addr.bit.b4 /* A/D converter standby bit */ +#define msttrc mstcr_addr.bit.b5 /* Timer RC standby bit */ +#define mstuart mstcr_addr.bit.b6 /* UART0 standby bit */ + +/*------------------------------------------------------ + Protect Register +------------------------------------------------------*/ +union byte_def prcr_addr; +#define prcr prcr_addr.byte + +#define prc0 prcr_addr.bit.b0 /* Protect bit 0 */ +#define prc1 prcr_addr.bit.b1 /* Protect bit 1 */ +#define prc3 prcr_addr.bit.b3 /* Protect bit 3 */ +#define prc4 prcr_addr.bit.b4 /* Protect bit 4 */ + +/*------------------------------------------------------ + Hardware Reset Protect Register +------------------------------------------------------*/ +union byte_def hrpr_addr; +#define hrpr hrpr_addr.byte + +#define pamcre hrpr_addr.bit.b0 /* PAMCR register write enable bit */ + +/*------------------------------------------------------ + External Clock Control Register +------------------------------------------------------*/ +union byte_def exckcr_addr; +#define exckcr exckcr_addr.byte + +#define ckpt0 exckcr_addr.bit.b0 /* P4_6 and P4_7 pin function select bit */ +#define ckpt1 exckcr_addr.bit.b1 /* P4_6 and P4_7 pin function select bit */ +#define xrcut exckcr_addr.bit.b6 /* XIN-XOUT on-chip feedback resistor select bit */ + +/*------------------------------------------------------ + High-Speed/Low-Speed On-Chip Oscillator Control Register +------------------------------------------------------*/ +union byte_def ococr_addr; +#define ococr ococr_addr.byte + +#define hocoe ococr_addr.bit.b0 /* High-speed on-chip oscillator oscillation enable bit */ +#define locodis ococr_addr.bit.b1 /* Low-speed on-chip oscillator oscillation stop bit */ + +/*------------------------------------------------------ + System Clock f Control Register +------------------------------------------------------*/ +union byte_def sckcr_addr; +#define sckcr sckcr_addr.byte + +#define phissel0 sckcr_addr.bit.b0 /* CPU clock division ratio select bit */ +#define phissel1 sckcr_addr.bit.b1 /* CPU clock division ratio select bit */ +#define phissel2 sckcr_addr.bit.b2 /* CPU clock division ratio select bit */ +#define waitm sckcr_addr.bit.b5 /* Wait control bit */ +#define hscksel sckcr_addr.bit.b6 /* High-speed on-chip oscillator/XIN clock select bit */ + +/*------------------------------------------------------ + System Clock f Select Register +------------------------------------------------------*/ +union byte_def phisel_addr; +#define phisel phisel_addr.byte + +#define phisel0 phisel_addr.bit.b0 /* System clock division select bit */ +#define phisel1 phisel_addr.bit.b1 /* System clock division select bit */ +#define phisel2 phisel_addr.bit.b2 /* System clock division select bit */ +#define phisel3 phisel_addr.bit.b3 /* System clock division select bit */ +#define phisel4 phisel_addr.bit.b4 /* System clock division select bit */ +#define phisel5 phisel_addr.bit.b5 /* System clock division select bit */ +#define phisel6 phisel_addr.bit.b6 /* System clock division select bit */ +#define phisel7 phisel_addr.bit.b7 /* System clock division select bit */ + +/*------------------------------------------------------ + Clock Stop Control Register +------------------------------------------------------*/ +union byte_def ckstpr_addr; +#define ckstpr ckstpr_addr.byte + +#define stpm ckstpr_addr.bit.b0 /* All clock stop control bit */ +#define wckstp ckstpr_addr.bit.b1 /* fBASE stop bit in wait mode */ +#define pscstp ckstpr_addr.bit.b2 /* Prescaler stop bit */ +#define scksel ckstpr_addr.bit.b7 /* System base clock select bit */ + +/*------------------------------------------------------ + Clock Control Register When Returning from Modes +------------------------------------------------------*/ +union byte_def ckrscr_addr; +#define ckrscr ckrscr_addr.byte + +#define ckst0 ckrscr_addr.bit.b0 /* Clock oscillator circuit oscillation stabilization state select bit */ +#define ckst1 ckrscr_addr.bit.b1 /* Clock oscillator circuit oscillation stabilization state select bit */ +#define ckst2 ckrscr_addr.bit.b2 /* Clock oscillator circuit oscillation stabilization state select bit */ +#define ckst3 ckrscr_addr.bit.b3 /* Clock oscillator circuit oscillation stabilization state select bit */ +#define phisrs ckrscr_addr.bit.b5 /* CPU clock division select bit when returning from wait mode or stop mode */ +#define waitrs ckrscr_addr.bit.b6 /* System base clock select bit when returning from wait mode */ +#define stoprs ckrscr_addr.bit.b7 /* System base clock select bit when returning from stop mode */ + +/*------------------------------------------------------ + Oscillation Stop Detection Register +------------------------------------------------------*/ +union byte_def bakcr_addr; +#define bakcr bakcr_addr.byte + +#define xinbake bakcr_addr.bit.b0 /* Oscillation stop detection enable bit */ +#define ckswie bakcr_addr.bit.b1 /* Oscillation stop detection interrupt enable bit */ +#define xinhalt bakcr_addr.bit.b2 /* Clock monitor bit */ +#define ckswif bakcr_addr.bit.b3 /* Oscillation stop detection interrupt request flag */ + +/*------------------------------------------------------ + Watchdog Timer Function Register +------------------------------------------------------*/ +union byte_def risr_addr; +#define risr risr_addr.byte + +#define ufif risr_addr.bit.b6 /* WDT underflow detection flag */ +#define ris risr_addr.bit.b7 /* WDT interrupt/reset switch bit */ + +/*------------------------------------------------------ + Watchdog Timer Reset Register +------------------------------------------------------*/ +union byte_def wdtr_addr; +#define wdtr wdtr_addr.byte + +/*------------------------------------------------------ + Watchdog Timer Start Register +------------------------------------------------------*/ +union byte_def wdts_addr; +#define wdts wdts_addr.byte + +/*------------------------------------------------------ + Watchdog Timer Control Register +------------------------------------------------------*/ +union byte_def wdtc_addr; +#define wdtc wdtc_addr.byte + +#define wdtc6 wdtc_addr.bit.b6 /* Watchdog timer count source select bit */ +#define wdtc7 wdtc_addr.bit.b7 /* Watchdog timer count source select bit */ + +/*------------------------------------------------------ + Count Source Protection Mode Register +------------------------------------------------------*/ +union byte_def cspr_addr; +#define cspr cspr_addr.byte + +#define cspro cspr_addr.bit.b7 /* Count source protection mode select bit */ + +/*------------------------------------------------------ + Periodic Timer Interrupt Control Register +------------------------------------------------------*/ +union byte_def wdtir_addr; +#define wdtir wdtir_addr.byte + +#define wdtif wdtir_addr.bit.b6 /* Periodic timer interrupt request flag */ +#define wdtie wdtir_addr.bit.b7 /* Periodic timer interrupt enable bit */ + +/*------------------------------------------------------ + External Input Enable Register +------------------------------------------------------*/ +union byte_def inten_addr; +#define inten inten_addr.byte + +#define int0en inten_addr.bit.b0 /* INT0 input enable bit */ +#define int1en inten_addr.bit.b1 /* INT1 input enable bit */ +#define int2en inten_addr.bit.b2 /* INT2 input enable bit */ +#define int3en inten_addr.bit.b3 /* INT3 input enable bit */ + +/*------------------------------------------------------ + INT Input Filter Select Register 0 +------------------------------------------------------*/ +union byte_def intf0_addr; +#define intf0 intf0_addr.byte + +#define int0f0 intf0_addr.bit.b0 /* INT0 input filter select bit */ +#define int0f1 intf0_addr.bit.b1 /* INT0 input filter select bit */ +#define int1f0 intf0_addr.bit.b2 /* INT1 input filter select bit */ +#define int1f1 intf0_addr.bit.b3 /* INT1 input filter select bit */ +#define int2f0 intf0_addr.bit.b4 /* INT2 input filter select bit */ +#define int2f1 intf0_addr.bit.b5 /* INT2 input filter select bit */ +#define int3f0 intf0_addr.bit.b6 /* INT3 input filter select bit */ +#define int3f1 intf0_addr.bit.b7 /* INT3 input filter select bit */ + +/*------------------------------------------------------ + INT Input Edge Select Register 0 +------------------------------------------------------*/ +union byte_def iscr0_addr; +#define iscr0 iscr0_addr.byte + +#define int0sa iscr0_addr.bit.b0 /* INT0 input edge select bit */ +#define int0sb iscr0_addr.bit.b1 /* INT0 input edge select bit */ +#define int1sa iscr0_addr.bit.b2 /* INT1 input edge select bit */ +#define int1sb iscr0_addr.bit.b3 /* INT1 input edge select bit */ +#define int2sa iscr0_addr.bit.b4 /* INT2 input edge select bit */ +#define int2sb iscr0_addr.bit.b5 /* INT2 input edge select bit */ +#define int3sa iscr0_addr.bit.b6 /* INT3 input edge select bit */ +#define int3sb iscr0_addr.bit.b7 /* INT3 input edge select bit */ + +/*------------------------------------------------------ + Key Input Enable Register +------------------------------------------------------*/ +union byte_def kien_addr; +#define kien kien_addr.byte + +#define ki0en kien_addr.bit.b0 /* KI0 input enable bit */ +#define ki0pl kien_addr.bit.b1 /* KI0 input edge select bit */ +#define ki1en kien_addr.bit.b2 /* KI1 input enable bit */ +#define ki1pl kien_addr.bit.b3 /* KI1 input edge select bit */ +#define ki2en kien_addr.bit.b4 /* KI2 input enable bit */ +#define ki2pl kien_addr.bit.b5 /* KI2 input edge select bit */ +#define ki3en kien_addr.bit.b6 /* KI3 input enable bit */ +#define ki3pl kien_addr.bit.b7 /* KI3 input edge select bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 0 +------------------------------------------------------*/ +union byte_def ilvl0_addr; +#define ilvl0 ilvl0_addr.byte + +#define ilvl00 ilvl0_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl01 ilvl0_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl04 ilvl0_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl05 ilvl0_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 2 +------------------------------------------------------*/ +union byte_def ilvl2_addr; +#define ilvl2 ilvl2_addr.byte + +#define ilvl20 ilvl2_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl21 ilvl2_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl24 ilvl2_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl25 ilvl2_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 3 +------------------------------------------------------*/ +union byte_def ilvl3_addr; +#define ilvl3 ilvl3_addr.byte + +#define ilvl30 ilvl3_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl31 ilvl3_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl34 ilvl3_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl35 ilvl3_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 4 +------------------------------------------------------*/ +union byte_def ilvl4_addr; +#define ilvl4 ilvl4_addr.byte + +#define ilvl40 ilvl4_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl41 ilvl4_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl44 ilvl4_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl45 ilvl4_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 5 +------------------------------------------------------*/ +union byte_def ilvl5_addr; +#define ilvl5 ilvl5_addr.byte + +#define ilvl50 ilvl5_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl51 ilvl5_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl54 ilvl5_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl55 ilvl5_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 6 +------------------------------------------------------*/ +union byte_def ilvl6_addr; +#define ilvl6 ilvl6_addr.byte + +#define ilvl60 ilvl6_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl61 ilvl6_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl64 ilvl6_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl65 ilvl6_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 7 +------------------------------------------------------*/ +union byte_def ilvl7_addr; +#define ilvl7 ilvl7_addr.byte + +#define ilvl70 ilvl7_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl71 ilvl7_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl74 ilvl7_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl75 ilvl7_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 8 +------------------------------------------------------*/ +union byte_def ilvl8_addr; +#define ilvl8 ilvl8_addr.byte + +#define ilvl80 ilvl8_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl81 ilvl8_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl84 ilvl8_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl85 ilvl8_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 9 +------------------------------------------------------*/ +union byte_def ilvl9_addr; +#define ilvl9 ilvl9_addr.byte + +#define ilvl90 ilvl9_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl91 ilvl9_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl94 ilvl9_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl95 ilvl9_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register A +------------------------------------------------------*/ +union byte_def ilvla_addr; +#define ilvla ilvla_addr.byte + +#define ilvla0 ilvla_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvla1 ilvla_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvla4 ilvla_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvla5 ilvla_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register B +------------------------------------------------------*/ +union byte_def ilvlb_addr; +#define ilvlb ilvlb_addr.byte + +#define ilvlb0 ilvlb_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvlb1 ilvlb_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvlb4 ilvlb_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvlb5 ilvlb_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register C +------------------------------------------------------*/ +union byte_def ilvlc_addr; +#define ilvlc ilvlc_addr.byte + +#define ilvlc0 ilvlc_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvlc1 ilvlc_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvlc4 ilvlc_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvlc5 ilvlc_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register D +------------------------------------------------------*/ +union byte_def ilvld_addr; +#define ilvld ilvld_addr.byte + +#define ilvld0 ilvld_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvld1 ilvld_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvld4 ilvld_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvld5 ilvld_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register E +------------------------------------------------------*/ +union byte_def ilvle_addr; +#define ilvle ilvle_addr.byte + +#define ilvle0 ilvle_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvle1 ilvle_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvle4 ilvle_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvle5 ilvle_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Monitor Flag Register 0 +------------------------------------------------------*/ +union byte_def irr0_addr; +#define irr0 irr0_addr.byte + +#define irtj irr0_addr.bit.b0 /* Timer RJ2 interrupt request monitor flag */ +#define irtb irr0_addr.bit.b1 /* Timer RB2 interrupt request monitor flag */ +#define irtc irr0_addr.bit.b2 /* Timer RC interrupt request monitor flag */ +#define irs0t irr0_addr.bit.b4 /* UART0 transmit interrupt request monitor flag */ +#define irs0r irr0_addr.bit.b5 /* UART0 receive interrupt request monitor flag */ + +/*------------------------------------------------------ + Interrupt Monitor Flag Register 1 +------------------------------------------------------*/ +union byte_def irr1_addr; +#define irr1 irr1_addr.byte + +#define irad irr1_addr.bit.b2 /* A/D conversion interrupt request monitor flag */ +#define irfm irr1_addr.bit.b4 /* Flash ready interrupt request monitor flag */ +#define irwd irr1_addr.bit.b5 /* Periodic timer interrupt request monitor flag */ + +/*------------------------------------------------------ + Interrupt Monitor Flag Register 2 +------------------------------------------------------*/ +union byte_def irr2_addr; +#define irr2 irr2_addr.byte + +#define ircmp1 irr2_addr.bit.b2 /* Comparator B1 interrupt request monitor flag */ +#define ircmp3 irr2_addr.bit.b3 /* Comparator B3 interrupt request monitor flag */ + +/*------------------------------------------------------ + External Interrupt Flag Register +------------------------------------------------------*/ +union byte_def irr3_addr; +#define irr3 irr3_addr.byte + +#define iri0 irr3_addr.bit.b0 /* INT0 interrupt request flag */ +#define iri1 irr3_addr.bit.b1 /* INT1 interrupt request flag */ +#define iri2 irr3_addr.bit.b2 /* INT2 interrupt request flag */ +#define iri3 irr3_addr.bit.b3 /* INT3 interrupt request flag */ +#define irki irr3_addr.bit.b5 /* Key input interrupt request flag */ + +/*------------------------------------------------------ + Voltage Monitor Circuit Edge Select Register +------------------------------------------------------*/ +union byte_def vcac_addr; +#define vcac vcac_addr.byte + +#define vcac1 vcac_addr.bit.b1 /* Voltage monitor 1 circuit edge select bit */ + +/*------------------------------------------------------ + Voltage Detect Register 2 +------------------------------------------------------*/ +union byte_def vca2_addr; +#define vca2 vca2_addr.byte + +#define lpe vca2_addr.bit.b0 /* Internal low-power-consumption enable bit */ +#define vc0e vca2_addr.bit.b5 /* Voltage detection 0 enable bit */ +#define vc1e vca2_addr.bit.b6 /* Voltage detection 1 enable bit */ + +/*------------------------------------------------------ + Voltage Detection 1 Level Select Register +------------------------------------------------------*/ +union byte_def vd1ls_addr; +#define vd1ls vd1ls_addr.byte + +#define vd1s1 vd1ls_addr.bit.b1 /* Voltage detection 1 Level select bit */ +#define vd1s2 vd1ls_addr.bit.b2 /* Voltage detection 1 Level select bit */ +#define vd1s3 vd1ls_addr.bit.b3 /* Voltage detection 1 Level select bit */ + +/*------------------------------------------------------ + Voltage Monitor 0 Circuit Control Register +------------------------------------------------------*/ +union byte_def vw0c_addr; +#define vw0c vw0c_addr.byte + +#define vw0c0 vw0c_addr.bit.b0 /* Voltage monitor 0 reset enable bit */ +#define vw0c1 vw0c_addr.bit.b1 /* Voltage monitor 0 digital filter mode select bit */ +#define vw0f0 vw0c_addr.bit.b4 /* Sampling clock select bit */ +#define vw0f1 vw0c_addr.bit.b5 /* Sampling clock select bit */ + +/*------------------------------------------------------ + Voltage Monitor 1 Circuit Control Register +------------------------------------------------------*/ +union byte_def vw1c_addr; +#define vw1c vw1c_addr.byte + +#define vw1c0 vw1c_addr.bit.b0 /* Voltage monitor 1 interrupt enable bit */ +#define vw1c1 vw1c_addr.bit.b1 /* Voltage monitor 1 digital filter mode select bit */ +#define vw1c2 vw1c_addr.bit.b2 /* Voltage change detection flag */ +#define vw1c3 vw1c_addr.bit.b3 /* Voltage detection 1 signal monitor flag */ +#define vw1f0 vw1c_addr.bit.b4 /* Sampling clock select bit */ +#define vw1f1 vw1c_addr.bit.b5 /* Sampling clock select bit */ +#define vw1c7 vw1c_addr.bit.b7 /* Voltage monitor 1 interrupt generation condition select bit */ + +/*------------------------------------------------------ + Reset Source Determination Register +------------------------------------------------------*/ +union byte_def rstfr_addr; +#define rstfr rstfr_addr.byte + +#define cwr rstfr_addr.bit.b0 /* Cold start-up/warm start-up determine flag */ +#define hwr rstfr_addr.bit.b1 /* Hardware reset detect flag */ +#define swr rstfr_addr.bit.b2 /* Software reset detect flag */ +#define wdr rstfr_addr.bit.b3 /* Watchdog timer reset detect flag */ + +/*------------------------------------------------------ + High-Speed On-Chip Oscillator 18.432 MHz Control Register 0 +------------------------------------------------------*/ +union byte_def fr18s0_addr; +#define fr18s0 fr18s0_addr.byte + +/*------------------------------------------------------ + High-Speed On-Chip Oscillator 18.432 MHz Control Register 1 +------------------------------------------------------*/ +union byte_def fr18s1_addr; +#define fr18s1 fr18s1_addr.byte + +/*------------------------------------------------------ + High-Speed On-Chip Oscillator Control Register 1 +------------------------------------------------------*/ +union byte_def frv1_addr; +#define frv1 frv1_addr.byte + +/*------------------------------------------------------ + High-Speed On-Chip Oscillator Control Register 2 +------------------------------------------------------*/ +union byte_def frv2_addr; +#define frv2 frv2_addr.byte + +/*------------------------------------------------------ + UART0 Transmit/Receive Mode Register +------------------------------------------------------*/ +union byte_def u0mr_addr; +#define u0mr u0mr_addr.byte + +#define smd0_u0mr u0mr_addr.bit.b0 /* Serial I/O mode select bit */ +#define smd1_u0mr u0mr_addr.bit.b1 /* Serial I/O mode select bit */ +#define smd2_u0mr u0mr_addr.bit.b2 /* Serial I/O mode select bit */ +#define ckdir_u0mr u0mr_addr.bit.b3 /* Internal/external clock select bit */ +#define stps_u0mr u0mr_addr.bit.b4 /* Stop bit length select bit */ +#define pry_u0mr u0mr_addr.bit.b5 /* Odd/even parity select bit */ +#define prye_u0mr u0mr_addr.bit.b6 /* Parity enable bit */ + +/*------------------------------------------------------ + UART0 Bit Rate Register +------------------------------------------------------*/ +union byte_def u0brg_addr; +#define u0brg u0brg_addr.byte + +/*------------------------------------------------------ + UART0 Transmit Buffer Register Low +------------------------------------------------------*/ +union byte_def u0tbl_addr; +#define u0tbl u0tbl_addr.byte + +/*------------------------------------------------------ + UART0 Transmit Buffer Register High +------------------------------------------------------*/ +union byte_def u0tbh_addr; +#define u0tbh u0tbh_addr.byte + +/*------------------------------------------------------ + UART0 Transmit/Receive Control Register 0 +------------------------------------------------------*/ +union byte_def u0c0_addr; +#define u0c0 u0c0_addr.byte + +#define clk0_u0c0 u0c0_addr.bit.b0 /* U0BRG count source select bit */ +#define clk1_u0c0 u0c0_addr.bit.b1 /* U0BRG count source select bit */ +#define txept_u0c0 u0c0_addr.bit.b3 /* Transmit register empty flag */ +#define dfe_u0c0 u0c0_addr.bit.b4 /* RXD0 digital filter enable bit */ +#define nch_u0c0 u0c0_addr.bit.b5 /* Data output select bit */ +#define ckpol_u0c0 u0c0_addr.bit.b6 /* CLK polarity select bit */ +#define uform_u0c0 u0c0_addr.bit.b7 /* Transfer format select bit */ + +/*------------------------------------------------------ + UART0 Transmit/Receive Control Register 1 +------------------------------------------------------*/ +union byte_def u0c1_addr; +#define u0c1 u0c1_addr.byte + +#define te_u0c1 u0c1_addr.bit.b0 /* Transmit enable bit */ +#define ti_u0c1 u0c1_addr.bit.b1 /* Transmit buffer empty flag */ +#define re_u0c1 u0c1_addr.bit.b2 /* Receive enable bit */ +#define ri_u0c1 u0c1_addr.bit.b3 /* Receive complete flag */ +#define u0irs_u0c1 u0c1_addr.bit.b4 /* UART0 transmit interrupt source select bit */ +#define u0rrm_u0c1 u0c1_addr.bit.b5 /* UART0 continuous receive mode enable bit */ + +/*------------------------------------------------------ + UART0 Receive Buffer Register +------------------------------------------------------*/ +union word_def u0rb_addr; +#define u0rb u0rb_addr.word + +/*------------------------------------------------------ + UART0 Interrupt Flag and Enable Register +------------------------------------------------------*/ +union byte_def u0ir_addr; +#define u0ir u0ir_addr.byte + +#define u0rie u0ir_addr.bit.b2 /* UART0 receive interrupt enable bit */ +#define u0tie u0ir_addr.bit.b3 /* UART0 transmit interrupt enable bit */ +#define u0rif u0ir_addr.bit.b6 /* UART0 receive interrupt flag */ +#define u0tif u0ir_addr.bit.b7 /* UART0 transmit interrupt flag */ + +/*------------------------------------------------------ + A/D Register 0 +------------------------------------------------------*/ +union word_def ad0_addr; +#define ad0 ad0_addr.word /* A/D Register 0 */ + +#define ad0l ad0_addr.byte.low /* A/D Register 0 Low */ +#define ad0h ad0_addr.byte.high /* A/D Register 0 High */ + +/*------------------------------------------------------ + A/D Register 1 +------------------------------------------------------*/ +union word_def ad1_addr; +#define ad1 ad1_addr.word /* A/D Register 1 */ + +#define ad1l ad1_addr.byte.low /* A/D Register 1 Low */ +#define ad1h ad1_addr.byte.high /* A/D Register 1 High */ + +/*------------------------------------------------------ + A/D Mode Register +------------------------------------------------------*/ +union byte_def admod_addr; +#define admod admod_addr.byte + +#define cks0 admod_addr.bit.b0 /* A/D conversion clock select bit */ +#define cks1 admod_addr.bit.b1 /* A/D conversion clock select bit */ +#define cks2 admod_addr.bit.b2 /* A/D conversion clock select bit */ +#define md0 admod_addr.bit.b3 /* A/D operating mode select bit */ +#define md1 admod_addr.bit.b4 /* A/D operating mode select bit */ +#define adcap0 admod_addr.bit.b6 /* A/D conversion trigger select bit */ +#define adcap1 admod_addr.bit.b7 /* A/D conversion trigger select bit */ + +/*------------------------------------------------------ + A/D Input Select Register +------------------------------------------------------*/ +union byte_def adinsel_addr; +#define adinsel adinsel_addr.byte + +#define ch0 adinsel_addr.bit.b0 /* Channel select bit */ +#define adgsel0 adinsel_addr.bit.b6 /* A/D input group select bit */ +#define adgsel1 adinsel_addr.bit.b7 /* A/D input group select bit */ + +/*------------------------------------------------------ + A/D Control Register 0 +------------------------------------------------------*/ +union byte_def adcon0_addr; +#define adcon0 adcon0_addr.byte + +#define adst adcon0_addr.bit.b0 /* A/D conversion start bit */ + +/*------------------------------------------------------ + A/D Interrupt Control Status Register +------------------------------------------------------*/ +union byte_def adicsr_addr; +#define adicsr adicsr_addr.byte + +#define adie adicsr_addr.bit.b6 /* A/D conversion interrupt enable bit */ +#define adf adicsr_addr.bit.b7 /* A/D conversion Interrupt request bit */ + +/*------------------------------------------------------ + Port P1 Direction Register +------------------------------------------------------*/ +union byte_def pd1_addr; +#define pd1 pd1_addr.byte + +#define pd1_0 pd1_addr.bit.b0 /* Port P1_0 direction bit */ +#define pd1_1 pd1_addr.bit.b1 /* Port P1_1 direction bit */ +#define pd1_2 pd1_addr.bit.b2 /* Port P1_2 direction bit */ +#define pd1_3 pd1_addr.bit.b3 /* Port P1_3 direction bit */ +#define pd1_4 pd1_addr.bit.b4 /* Port P1_4 direction bit */ +#define pd1_5 pd1_addr.bit.b5 /* Port P1_5 direction bit */ +#define pd1_6 pd1_addr.bit.b6 /* Port P1_6 direction bit */ +#define pd1_7 pd1_addr.bit.b7 /* Port P1_7 direction bit */ + +/*------------------------------------------------------ + Port P3 Direction Register +------------------------------------------------------*/ +union byte_def pd3_addr; +#define pd3 pd3_addr.byte + +#define pd3_3 pd3_addr.bit.b3 /* Port P3_3 direction bit */ +#define pd3_4 pd3_addr.bit.b4 /* Port P3_4 direction bit */ +#define pd3_5 pd3_addr.bit.b5 /* Port P3_5 direction bit */ +#define pd3_7 pd3_addr.bit.b7 /* Port P3_7 direction bit */ + +/*------------------------------------------------------ + Port P4 Direction Register +------------------------------------------------------*/ +union byte_def pd4_addr; +#define pd4 pd4_addr.byte + +#define pd4_2 pd4_addr.bit.b2 /* Port P4_2 direction bit */ +#define pd4_5 pd4_addr.bit.b5 /* Port P4_5 direction bit */ +#define pd4_6 pd4_addr.bit.b6 /* Port P4_6 direction bit */ +#define pd4_7 pd4_addr.bit.b7 /* Port P4_7 direction bit */ + +/*------------------------------------------------------ + Port PA Direction Register +------------------------------------------------------*/ +union byte_def pda_addr; +#define pda pda_addr.byte + +#define pda_0 pda_addr.bit.b0 /* Port PA_0 direction bit */ + +/*------------------------------------------------------ + Port P1 Register +------------------------------------------------------*/ +union byte_def p1_addr; +#define p1 p1_addr.byte + +#define p1_0 p1_addr.bit.b0 /* Port P1_0 bit */ +#define p1_1 p1_addr.bit.b1 /* Port P1_1 bit */ +#define p1_2 p1_addr.bit.b2 /* Port P1_2 bit */ +#define p1_3 p1_addr.bit.b3 /* Port P1_3 bit */ +#define p1_4 p1_addr.bit.b4 /* Port P1_4 bit */ +#define p1_5 p1_addr.bit.b5 /* Port P1_5 bit */ +#define p1_6 p1_addr.bit.b6 /* Port P1_6 bit */ +#define p1_7 p1_addr.bit.b7 /* Port P1_7 bit */ + +/*------------------------------------------------------ + Port P3 Register +------------------------------------------------------*/ +union byte_def p3_addr; +#define p3 p3_addr.byte + +#define p3_3 p3_addr.bit.b3 /* Port P3_3 bit */ +#define p3_4 p3_addr.bit.b4 /* Port P3_4 bit */ +#define p3_5 p3_addr.bit.b5 /* Port P3_5 bit */ +#define p3_7 p3_addr.bit.b7 /* Port P3_7 bit */ + +/*------------------------------------------------------ + Port P4 Register +------------------------------------------------------*/ +union byte_def p4_addr; +#define p4 p4_addr.byte + +#define p4_2 p4_addr.bit.b2 /* Port P4_2 bit */ +#define p4_5 p4_addr.bit.b5 /* Port P4_5 bit */ +#define p4_6 p4_addr.bit.b6 /* Port P4_6 bit */ +#define p4_7 p4_addr.bit.b7 /* Port P4_7 bit */ + +/*------------------------------------------------------ + Port PA Register +------------------------------------------------------*/ +union byte_def pa_addr; +#define pa pa_addr.byte + +#define pa_0 pa_addr.bit.b0 /* Port PA_0 bit */ + +/*------------------------------------------------------ + Pull-Up Control Register 1 +------------------------------------------------------*/ +union byte_def pur1_addr; +#define pur1 pur1_addr.byte + +#define pu1_0 pur1_addr.bit.b0 /* Port P1_0 pull-up control bit */ +#define pu1_1 pur1_addr.bit.b1 /* Port P1_1 pull-up control bit */ +#define pu1_2 pur1_addr.bit.b2 /* Port P1_2 pull-up control bit */ +#define pu1_3 pur1_addr.bit.b3 /* Port P1_3 pull-up control bit */ +#define pu1_4 pur1_addr.bit.b4 /* Port P1_4 pull-up control bit */ +#define pu1_5 pur1_addr.bit.b5 /* Port P1_5 pull-up control bit */ +#define pu1_6 pur1_addr.bit.b6 /* Port P1_6 pull-up control bit */ +#define pu1_7 pur1_addr.bit.b7 /* Port P1_7 pull-up control bit */ + +/*------------------------------------------------------ + Pull-Up Control Register 3 +------------------------------------------------------*/ +union byte_def pur3_addr; +#define pur3 pur3_addr.byte + +#define pu3_3 pur3_addr.bit.b3 /* Port P3_3 pull-up control bit */ +#define pu3_4 pur3_addr.bit.b4 /* Port P3_4 pull-up control bit */ +#define pu3_5 pur3_addr.bit.b5 /* Port P3_5 pull-up control bit */ +#define pu3_7 pur3_addr.bit.b7 /* Port P3_7 pull-up control bit */ + +/*------------------------------------------------------ + Pull-Up Control Register 4 +------------------------------------------------------*/ +union byte_def pur4_addr; +#define pur4 pur4_addr.byte + +#define pu4_2 pur4_addr.bit.b2 /* Port P4_2 pull-up control bit */ +#define pu4_5 pur4_addr.bit.b5 /* Port P4_5 pull-up control bit */ +#define pu4_6 pur4_addr.bit.b6 /* Port P4_6 pull-up control bit */ +#define pu4_7 pur4_addr.bit.b7 /* Port P4_7 pull-up control bit */ + +/*------------------------------------------------------ + Port I/O Function Control Register +------------------------------------------------------*/ +union byte_def pinsr_addr; +#define pinsr pinsr_addr.byte + +#define trjiosel pinsr_addr.bit.b6 /* TRJIO input signal select bit */ +#define ioinsel pinsr_addr.bit.b7 /* Pin level forced read-out bit */ + +/*------------------------------------------------------ + Drive Capacity Control Register 1 +------------------------------------------------------*/ +union byte_def drr1_addr; +#define drr1 drr1_addr.byte + +#define drr1_2 drr1_addr.bit.b2 /* Port P1_2 drive capacity control bit */ +#define drr1_3 drr1_addr.bit.b3 /* Port P1_3 drive capacity control bit */ +#define drr1_4 drr1_addr.bit.b4 /* Port P1_4 drive capacity control bit */ +#define drr1_5 drr1_addr.bit.b5 /* Port P1_5 drive capacity control bit */ + +/*------------------------------------------------------ + Drive Capacity Control Register 3 +------------------------------------------------------*/ +union byte_def drr3_addr; +#define drr3 drr3_addr.byte + +#define drr3_3 drr3_addr.bit.b3 /* Port P3_3 drive capacity control bit */ +#define drr3_4 drr3_addr.bit.b4 /* Port P3_4 drive capacity control bit */ +#define drr3_5 drr3_addr.bit.b5 /* Port P3_5 drive capacity control bit */ +#define drr3_7 drr3_addr.bit.b7 /* Port P3_7 drive capacity control bit */ + +/*------------------------------------------------------ + Open-Drain Control Register 1 +------------------------------------------------------*/ +union byte_def pod1_addr; +#define pod1 pod1_addr.byte + +#define pod1_0 pod1_addr.bit.b0 /* Port P1_0 open-drain control bit */ +#define pod1_1 pod1_addr.bit.b1 /* Port P1_1 open-drain control bit */ +#define pod1_2 pod1_addr.bit.b2 /* Port P1_2 open-drain control bit */ +#define pod1_3 pod1_addr.bit.b3 /* Port P1_3 open-drain control bit */ +#define pod1_4 pod1_addr.bit.b4 /* Port P1_4 open-drain control bit */ +#define pod1_5 pod1_addr.bit.b5 /* Port P1_5 open-drain control bit */ +#define pod1_6 pod1_addr.bit.b6 /* Port P1_6 open-drain control bit */ +#define pod1_7 pod1_addr.bit.b7 /* Port P1_7 open-drain control bit */ + +/*------------------------------------------------------ + Open-Drain Control Register 3 +------------------------------------------------------*/ +union byte_def pod3_addr; +#define pod3 pod3_addr.byte + +#define pod3_3 pod3_addr.bit.b3 /* Port P3_3 open-drain control bit */ +#define pod3_4 pod3_addr.bit.b4 /* Port P3_4 open-drain control bit */ +#define pod3_5 pod3_addr.bit.b5 /* Port P3_5 open-drain control bit */ +#define pod3_7 pod3_addr.bit.b7 /* Port P3_7 open-drain control bit */ + +/*------------------------------------------------------ + Open-Drain Control Register 4 +------------------------------------------------------*/ +union byte_def pod4_addr; +#define pod4 pod4_addr.byte + +#define pod4_2 pod4_addr.bit.b2 /* Port P4_2 open-drain control bit */ +#define pod4_5 pod4_addr.bit.b5 /* Port P4_5 open-drain control bit */ +#define pod4_6 pod4_addr.bit.b6 /* Port P4_6 open-drain control bit */ +#define pod4_7 pod4_addr.bit.b7 /* Port P4_7 open-drain control bit */ + +/*------------------------------------------------------ + Port PA Mode Control Register +------------------------------------------------------*/ +union byte_def pamcr_addr; +#define pamcr pamcr_addr.byte + +#define poda_0 pamcr_addr.bit.b0 /* Port PA_0 open-drain control bit */ +#define hwrste pamcr_addr.bit.b4 /* Hardware reset enabled bit */ + +/*------------------------------------------------------ + Port 1 Function Mapping Register 0 +------------------------------------------------------*/ +union byte_def pml1_addr; +#define pml1 pml1_addr.byte + +#define p10sel0 pml1_addr.bit.b0 /* Port P1_0 function select bit */ +#define p10sel1 pml1_addr.bit.b1 /* Port P1_0 function select bit */ +#define p11sel0 pml1_addr.bit.b2 /* Port P1_1 function select bit */ +#define p11sel1 pml1_addr.bit.b3 /* Port P1_1 function select bit */ +#define p12sel0 pml1_addr.bit.b4 /* Port P1_2 function select bit */ +#define p12sel1 pml1_addr.bit.b5 /* Port P1_2 function select bit */ +#define p13sel0 pml1_addr.bit.b6 /* Port P1_3 function select bit */ +#define p13sel1 pml1_addr.bit.b7 /* Port P1_3 function select bit */ + +/*------------------------------------------------------ + Port 1 Function Mapping Register 1 +------------------------------------------------------*/ +union byte_def pmh1_addr; +#define pmh1 pmh1_addr.byte + +#define p14sel0 pmh1_addr.bit.b0 /* Port P1_4 function select bit */ +#define p14sel1 pmh1_addr.bit.b1 /* Port P1_4 function select bit */ +#define p15sel0 pmh1_addr.bit.b2 /* Port P1_5 function select bit */ +#define p15sel1 pmh1_addr.bit.b3 /* Port P1_5 function select bit */ +#define p16sel0 pmh1_addr.bit.b4 /* Port P1_6 function select bit */ +#define p16sel1 pmh1_addr.bit.b5 /* Port P1_6 function select bit */ +#define p17sel0 pmh1_addr.bit.b6 /* Port P1_7 function select bit */ +#define p17sel1 pmh1_addr.bit.b7 /* Port P1_7 function select bit */ + +/*------------------------------------------------------ + Port 3 Function Mapping Register 0 +------------------------------------------------------*/ +union byte_def pml3_addr; +#define pml3 pml3_addr.byte + +#define p33sel0 pml3_addr.bit.b6 /* Port P3_3 function select bit */ +#define p33sel1 pml3_addr.bit.b7 /* Port P3_3 function select bit */ + +/*------------------------------------------------------ + Port 3 Function Mapping Register 1 +------------------------------------------------------*/ +union byte_def pmh3_addr; +#define pmh3 pmh3_addr.byte + +#define p34sel0 pmh3_addr.bit.b0 /* Port P3_4 function select bit */ +#define p34sel1 pmh3_addr.bit.b1 /* Port P3_4 function select bit */ +#define p35sel0 pmh3_addr.bit.b2 /* Port P3_5 function select bit */ +#define p35sel1 pmh3_addr.bit.b3 /* Port P3_5 function select bit */ +#define p37sel0 pmh3_addr.bit.b6 /* Port P3_7 function select bit */ +#define p37sel1 pmh3_addr.bit.b7 /* Port P3_7 function select bit */ + +/*------------------------------------------------------ + Port 4 Function Mapping Register 0 +------------------------------------------------------*/ +union byte_def pml4_addr; +#define pml4 pml4_addr.byte + +#define p42sel0 pml4_addr.bit.b4 /* Port P4_2 function select bit */ +#define p42sel1 pml4_addr.bit.b5 /* Port P4_2 function select bit */ + +/*------------------------------------------------------ + Port 4 Function Mapping Register 1 +------------------------------------------------------*/ +union byte_def pmh4_addr; +#define pmh4 pmh4_addr.byte + +#define p45sel0 pmh4_addr.bit.b2 /* Port P4_5 function select bit */ +#define p45sel1 pmh4_addr.bit.b3 /* Port P4_5 function select bit */ +#define p46sel0 pmh4_addr.bit.b4 /* Port P4_6 function select bit */ +#define p46sel1 pmh4_addr.bit.b5 /* Port P4_6 function select bit */ +#define p47sel0 pmh4_addr.bit.b6 /* Port P4_7 function select bit */ +#define p47sel1 pmh4_addr.bit.b7 /* Port P4_7 function select bit */ + +/*------------------------------------------------------ + Port 1 Function Mapping Expansion Register +------------------------------------------------------*/ +union byte_def pmh1e_addr; +#define pmh1e pmh1e_addr.byte + +#define p14sel2 pmh1e_addr.bit.b0 /* The P1_4 pin function is selected in conjunction with bits P14SEL0 to P14SEL1 in the PMH1 register */ +#define p15sel2 pmh1e_addr.bit.b2 /* The P1_5 pin function is selected in conjunction with bits P15SEL0 to P15SEL1 in the PMH1 register */ + +/*------------------------------------------------------ + Port 4 Function Mapping Expansion Register +------------------------------------------------------*/ +union byte_def pmh4e_addr; +#define pmh4e pmh4e_addr.byte + +#define p46sel2 pmh4e_addr.bit.b4 /* The P4_6 pin function is selected in conjunction with bits P46SEL0 to P46SEL1 in the PMH4 register */ + +/*------------------------------------------------------ + Timer RJ Counter Register / Timer RJ Reload Register +------------------------------------------------------*/ +union word_def trj_addr; +#define trj trj_addr.word /* Timer RJ Counter Register, Timer RJ Reload Register */ + +/*------------------------------------------------------ + Timer RJ Control Register +------------------------------------------------------*/ +union byte_def trjcr_addr; +#define trjcr trjcr_addr.byte + +#define tstart_trjcr trjcr_addr.bit.b0 /* Timer RJ count start bit */ +#define tcstf_trjcr trjcr_addr.bit.b1 /* Timer RJ count status flag */ +#define tstop_trjcr trjcr_addr.bit.b2 /* Timer RJ count forced stop bit */ +#define tedgf_trjcr trjcr_addr.bit.b4 /* Active edge judgment flag */ +#define tundf_trjcr trjcr_addr.bit.b5 /* Timer RJ underflow flag */ + +/*------------------------------------------------------ + Timer RJ I/O Control Register +------------------------------------------------------*/ +union byte_def trjioc_addr; +#define trjioc trjioc_addr.byte + +#define tedgsel_trjioc trjioc_addr.bit.b0 /* I/O polarity switch bit */ +#define topcr_trjioc trjioc_addr.bit.b1 /* TRJIO output control bit */ +#define tipf0_trjioc trjioc_addr.bit.b4 /* TRJIO input filter select bit */ +#define tipf1_trjioc trjioc_addr.bit.b5 /* TRJIO input filter select bit */ +#define tiogt0_trjioc trjioc_addr.bit.b6 /* TRJIO count control bit */ +#define tiogt1_trjioc trjioc_addr.bit.b7 /* TRJIO count control bit */ + +/*------------------------------------------------------ + Timer RJ Mode Register +------------------------------------------------------*/ +union byte_def trjmr_addr; +#define trjmr trjmr_addr.byte + +#define tmod0_trjmr trjmr_addr.bit.b0 /* Timer RJ operating mode select bit */ +#define tmod1_trjmr trjmr_addr.bit.b1 /* Timer RJ operating mode select bit */ +#define tmod2_trjmr trjmr_addr.bit.b2 /* Timer RJ operating mode select bit */ +#define tedgpl_trjmr trjmr_addr.bit.b3 /* TRJIO edge polarity select bit */ +#define tck0_trjmr trjmr_addr.bit.b4 /* Timer RJ count source select bit */ +#define tck1_trjmr trjmr_addr.bit.b5 /* Timer RJ count source select bit */ +#define tck2_trjmr trjmr_addr.bit.b6 /* Timer RJ count source select bit */ +#define tckcut_trjmr trjmr_addr.bit.b7 /* Timer RJ count source cutoff bit */ + +/*------------------------------------------------------ + Timer RJ Event Select Register +------------------------------------------------------*/ +union byte_def trjisr_addr; +#define trjisr trjisr_addr.byte + +#define rccpsel0_trjisr trjisr_addr.bit.b0 /* Timer RC output signal select bit */ +#define rccpsel1_trjisr trjisr_addr.bit.b1 /* Timer RC output signal select bit */ +#define rccpsel2_trjisr trjisr_addr.bit.b2 /* Timer RC output signal inversion bit */ + +/*------------------------------------------------------ + Timer RJ Interrupt Control Register +------------------------------------------------------*/ +union byte_def trjir_addr; +#define trjir trjir_addr.byte + +#define trjif_trjir trjir_addr.bit.b6 /* Timer RJ interrupt request flag */ +#define trjie_trjir trjir_addr.bit.b7 /* Timer RJ interrupt enable bit */ + +/*------------------------------------------------------ + Timer RB Control Register +------------------------------------------------------*/ +union byte_def trbcr_addr; +#define trbcr trbcr_addr.byte + +#define tstart_trbcr trbcr_addr.bit.b0 /* Timer RB count start bit */ +#define tcstf_trbcr trbcr_addr.bit.b1 /* Timer RB count status flag */ +#define tstop_trbcr trbcr_addr.bit.b2 /* Timer RB count forced stop bit */ + +/*------------------------------------------------------ + Timer RB One-Shot Control Register +------------------------------------------------------*/ +union byte_def trbocr_addr; +#define trbocr trbocr_addr.byte + +#define tosst_trbocr trbocr_addr.bit.b0 /* Timer RB one-shot start bit */ +#define tossp_trbocr trbocr_addr.bit.b1 /* Timer RB one-shot stop bit */ +#define tosstf_trbocr trbocr_addr.bit.b2 /* Timer RB one-shot status flag */ + +/*------------------------------------------------------ + Timer RB I/O Control Register +------------------------------------------------------*/ +union byte_def trbioc_addr; +#define trbioc trbioc_addr.byte + +#define topl_trbioc trbioc_addr.bit.b0 /* Timer RB output level select bit */ +#define tocnt_trbioc trbioc_addr.bit.b1 /* Timer RB output switch bit */ +#define inostg_trbioc trbioc_addr.bit.b2 /* One-shot trigger control bit */ +#define inoseg_trbioc trbioc_addr.bit.b3 /* One-shot trigger polarity select bit */ + +/*------------------------------------------------------ + Timer RB Mode Register +------------------------------------------------------*/ +union byte_def trbmr_addr; +#define trbmr trbmr_addr.byte + +#define tmod0_trbmr trbmr_addr.bit.b0 /* Timer RB operating mode select bit */ +#define tmod1_trbmr trbmr_addr.bit.b1 /* Timer RB operating mode select bit */ +#define tcnt16_trbmr trbmr_addr.bit.b2 /* Timer RB counter select bit */ +#define twrc_trbmr trbmr_addr.bit.b3 /* Timer RB write control bit */ +#define tck0_trbmr trbmr_addr.bit.b4 /* Timer RB count source select bit */ +#define tck1_trbmr trbmr_addr.bit.b5 /* Timer RB count source select bit */ +#define tck2_trbmr trbmr_addr.bit.b6 /* Timer RB count source select bit */ +#define tckcut_trbmr trbmr_addr.bit.b7 /* Timer RB count source cutoff bit */ + +/*------------------------------------------------------ + Timer RB Prescaler Register +------------------------------------------------------*/ +union byte_def trbpre_addr; +#define trbpre trbpre_addr.byte + +/*------------------------------------------------------ + Timer RB Primary Register +------------------------------------------------------*/ +union byte_def trbpr_addr; +#define trbpr trbpr_addr.byte + +/*------------------------------------------------------ + Timer RB Secondary Register +------------------------------------------------------*/ +union byte_def trbsc_addr; +#define trbsc trbsc_addr.byte + +/*------------------------------------------------------ + Timer RB Interrupt Control Register +------------------------------------------------------*/ +union byte_def trbir_addr; +#define trbir trbir_addr.byte + +#define trbif_trbir trbir_addr.bit.b6 /* Timer RB interrupt request flag */ +#define trbie_trbir trbir_addr.bit.b7 /* Timer RB interrupt enable bit */ + +/*------------------------------------------------------ + Timer RC Counter, General Register A,B,C,D +------------------------------------------------------*/ +union word_def trccnt_addr; +#define trccnt trccnt_addr.word /* Timer RC Counter */ + +union word_def trcgra_addr; +#define trcgra trcgra_addr.word /* Timer RC General Register A */ + +union word_def trcgrb_addr; +#define trcgrb trcgrb_addr.word /* Timer RC General Register B */ + +union word_def trcgrc_addr; +#define trcgrc trcgrc_addr.word /* Timer RC General Register C */ + +union word_def trcgrd_addr; +#define trcgrd trcgrd_addr.word /* Timer RC General Register D */ + +/*------------------------------------------------------ + Timer RC Mode Register +------------------------------------------------------*/ +union byte_def trcmr_addr; +#define trcmr trcmr_addr.byte + +#define pwmb_trcmr trcmr_addr.bit.b0 /* TRCIOB PWM mode select bit */ +#define pwmc_trcmr trcmr_addr.bit.b1 /* TRCIOC PWM mode select bit */ +#define pwmd_trcmr trcmr_addr.bit.b2 /* TRCIOD PWM mode select bit */ +#define pwm2_trcmr trcmr_addr.bit.b3 /* PWM2 mode select bit */ +#define bufea_trcmr trcmr_addr.bit.b4 /* TRCGRC register function select bit */ +#define bufeb_trcmr trcmr_addr.bit.b5 /* TRCGRD register function select bit */ +#define cts_trcmr trcmr_addr.bit.b7 /* TRCCNT count start bit */ + +/*------------------------------------------------------ + Timer RC Control Register 1 +------------------------------------------------------*/ +union byte_def trccr1_addr; +#define trccr1 trccr1_addr.byte + +#define toa_trccr1 trccr1_addr.bit.b0 /* Timer output level select A bit */ +#define tob_trccr1 trccr1_addr.bit.b1 /* Timer output level select B bit */ +#define toc_trccr1 trccr1_addr.bit.b2 /* Timer output level select C bit */ +#define tod_trccr1 trccr1_addr.bit.b3 /* Timer output level select D bit */ +#define cks0_trccr1 trccr1_addr.bit.b4 /* Count source select bit */ +#define cks1_trccr1 trccr1_addr.bit.b5 /* Count source select bit */ +#define cks2_trccr1 trccr1_addr.bit.b6 /* Count source select bit */ +#define cclr_trccr1 trccr1_addr.bit.b7 /* TRCCNT counter clear select bit */ + +/*------------------------------------------------------ + Timer RC Interrupt Enable Register +------------------------------------------------------*/ +union byte_def trcier_addr; +#define trcier trcier_addr.byte + +#define imiea_trcier trcier_addr.bit.b0 /* Input capture/compare match A interrupt enable bit */ +#define imieb_trcier trcier_addr.bit.b1 /* Input capture/compare match B interrupt enable bit */ +#define imiec_trcier trcier_addr.bit.b2 /* Input capture/compare match C interrupt enable bit */ +#define imied_trcier trcier_addr.bit.b3 /* Input capture/compare match D interrupt enable bit */ +#define ovie_trcier trcier_addr.bit.b7 /* Timer overflow interrupt enable bit */ + +/*------------------------------------------------------ + Timer RC Status Register +------------------------------------------------------*/ +union byte_def trcsr_addr; +#define trcsr trcsr_addr.byte + +#define imfa_trcsr trcsr_addr.bit.b0 /* Input capture/compare match A flag */ +#define imfb_trcsr trcsr_addr.bit.b1 /* Input capture/compare match B flag */ +#define imfc_trcsr trcsr_addr.bit.b2 /* Input capture/compare match C flag */ +#define imfd_trcsr trcsr_addr.bit.b3 /* Input capture/compare match D flag */ +#define ovf_trcsr trcsr_addr.bit.b7 /* Timer overflow flag */ + +/*------------------------------------------------------ + Timer RC I/O Control Register 0 +------------------------------------------------------*/ +union byte_def trcior0_addr; +#define trcior0 trcior0_addr.byte + +#define ioa0_trcior0 trcior0_addr.bit.b0 /* TRCGRA control A0 bit */ +#define ioa1_trcior0 trcior0_addr.bit.b1 /* TRCGRA control A1 bit */ +#define ioa2_trcior0 trcior0_addr.bit.b2 /* TRCGRA control A2 bit */ +#define iob0_trcior0 trcior0_addr.bit.b4 /* TRCGRB control B0 bit */ +#define iob1_trcior0 trcior0_addr.bit.b5 /* TRCGRB control B1 bit */ +#define iob2_trcior0 trcior0_addr.bit.b6 /* TRCGRB control B2 bit */ + +/*------------------------------------------------------ + Timer RC I/O Control Register 1 +------------------------------------------------------*/ +union byte_def trcior1_addr; +#define trcior1 trcior1_addr.byte + +#define ioc0_trcior1 trcior1_addr.bit.b0 /* TRCGRC control C0 bit */ +#define ioc1_trcior1 trcior1_addr.bit.b1 /* TRCGRC control C1 bit */ +#define ioc2_trcior1 trcior1_addr.bit.b2 /* TRCGRC control C2 bit */ +#define ioc3_trcior1 trcior1_addr.bit.b3 /* TRCGRC control C3 bit */ +#define iod0_trcior1 trcior1_addr.bit.b4 /* TRCGRD control D0 bit */ +#define iod1_trcior1 trcior1_addr.bit.b5 /* TRCGRD control D1 bit */ +#define iod2_trcior1 trcior1_addr.bit.b6 /* TRCGRD control D2 bit */ +#define iod3_trcior1 trcior1_addr.bit.b7 /* TRCGRD control D3 bit */ + +/*------------------------------------------------------ + Timer RC Control Register 2 +------------------------------------------------------*/ +union byte_def trccr2_addr; +#define trccr2 trccr2_addr.byte + +#define polb_trccr2 trccr2_addr.bit.b0 /* TRCIOB PWM mode output level control bit */ +#define polc_trccr2 trccr2_addr.bit.b1 /* TRCIOC PWM mode output level control bit */ +#define pold_trccr2 trccr2_addr.bit.b2 /* TRCIOD PWM mode output level control bit */ +#define cstp_trccr2 trccr2_addr.bit.b5 /* Count stop bit */ +#define tceg0_trccr2 trccr2_addr.bit.b6 /* TRCTRG input edge select bit */ +#define tceg1_trccr2 trccr2_addr.bit.b7 /* TRCTRG input edge select bit */ + +/*------------------------------------------------------ + Timer RC Digital Filter Function Select Register +------------------------------------------------------*/ +union byte_def trcdf_addr; +#define trcdf trcdf_addr.byte + +#define dfa_trcdf trcdf_addr.bit.b0 /* TRCIOA digital filter function bit */ +#define dfb_trcdf trcdf_addr.bit.b1 /* TRCIOB digital filter function bit */ +#define dfc_trcdf trcdf_addr.bit.b2 /* TRCIOC digital filter function bit */ +#define dfd_trcdf trcdf_addr.bit.b3 /* TRCIOD digital filter function bit */ +#define dftrg_trcdf trcdf_addr.bit.b4 /* TRCTRG digital filter function bit */ +#define dfck0_trcdf trcdf_addr.bit.b6 /* Digital filter clock select bit */ +#define dfck1_trcdf trcdf_addr.bit.b7 /* Digital filter clock select bit */ + +/*------------------------------------------------------ + Timer RC Output Enable Register +------------------------------------------------------*/ +union byte_def trcoer_addr; +#define trcoer trcoer_addr.byte + +#define ea_trcoer trcoer_addr.bit.b0 /* TRCIOA output disable bit */ +#define eb_trcoer trcoer_addr.bit.b1 /* TRCIOB output disable bit */ +#define ec_trcoer trcoer_addr.bit.b2 /* TRCIOC output disable bit */ +#define ed_trcoer trcoer_addr.bit.b3 /* TRCIOD output disable bit */ +#define pto_trcoer trcoer_addr.bit.b7 /* Timer output disable bit */ + +/*------------------------------------------------------ + Timer RC A/D Conversion Trigger Control Register +------------------------------------------------------*/ +union byte_def trcadcr_addr; +#define trcadcr trcadcr_addr.byte + +#define adtrgae_trcadcr trcadcr_addr.bit.b0 /* TRCGRA A/D conversion start trigger enable bit */ +#define adtrgbe_trcadcr trcadcr_addr.bit.b1 /* TRCGRB A/D conversion start trigger enable bit */ +#define adtrgce_trcadcr trcadcr_addr.bit.b2 /* TRCGRC A/D conversion start trigger enable bit */ +#define adtrgde_trcadcr trcadcr_addr.bit.b3 /* TRCGRD A/D conversion start trigger enable bit */ + +/*------------------------------------------------------ + Timer RC Waveform Output Manipulation Register +------------------------------------------------------*/ +union byte_def trcopr_addr; +#define trcopr trcopr_addr.byte + +#define opsel0_trcopr trcopr_addr.bit.b0 /* Waveform output manipulation event select bit */ +#define opsel1_trcopr trcopr_addr.bit.b1 /* Waveform output manipulation event select bit */ +#define opol0_trcopr trcopr_addr.bit.b2 /* Waveform output manipulation period output level select bit */ +#define opol1_trcopr trcopr_addr.bit.b3 /* Waveform output manipulation period output level select bit */ +#define restats_trcopr trcopr_addr.bit.b4 /* Restart method select bit */ +#define ope_trcopr trcopr_addr.bit.b5 /* Waveform output manipulation enable bit */ + +/*------------------------------------------------------ + Comparator B Control Register 0 +------------------------------------------------------*/ +union byte_def wcmpr_addr; +#define wcmpr wcmpr_addr.byte + +#define wcb1m0 wcmpr_addr.bit.b0 /* Comparator B1 operation enable bit */ +#define wcb1out wcmpr_addr.bit.b3 /* Comparator B1 monitor flag */ +#define wcb3m0 wcmpr_addr.bit.b4 /* Comparator B3 operation enable bit */ +#define wcb3out wcmpr_addr.bit.b7 /* Comparator B3 monitor flag */ + +/*------------------------------------------------------ + Comparator B1 Interrupt Control Register +------------------------------------------------------*/ +union byte_def wcb1intr_addr; +#define wcb1intr wcb1intr_addr.byte + +#define wcb1f0 wcb1intr_addr.bit.b0 /* Comparator B1 filter select bit */ +#define wcb1f1 wcb1intr_addr.bit.b1 /* Comparator B1 filter select bit */ +#define wcb1s0 wcb1intr_addr.bit.b4 /* Comparator B1 interrupt edge select bit */ +#define wcb1s1 wcb1intr_addr.bit.b5 /* Comparator B1 interrupt edge select bit */ +#define wcb1inten wcb1intr_addr.bit.b6 /* Comparator B1 interrupt enable signal bit */ +#define wcb1f wcb1intr_addr.bit.b7 /* Comparator B1 interrupt request flag */ + +/*------------------------------------------------------ + Comparator B3 Interrupt Control Register +------------------------------------------------------*/ +union byte_def wcb3intr_addr; +#define wcb3intr wcb3intr_addr.byte + +#define wcb3f0 wcb3intr_addr.bit.b0 /* Comparator B3 filter select bit */ +#define wcb3f1 wcb3intr_addr.bit.b1 /* Comparator B3 filter select bit */ +#define wcb3s0 wcb3intr_addr.bit.b4 /* Comparator B3 interrupt edge select bit */ +#define wcb3s1 wcb3intr_addr.bit.b5 /* Comparator B3 interrupt edge select bit */ +#define wcb3inten wcb3intr_addr.bit.b6 /* Comparator B3 interrupt enable signal bit */ +#define wcb3f wcb3intr_addr.bit.b7 /* Comparator B3 interrupt request flag */ + +/*------------------------------------------------------ + Flash Memory Status Register +------------------------------------------------------*/ +union byte_def fst_addr; +#define fst fst_addr.byte + +#define rdysti fst_addr.bit.b0 /* Flash ready status interrupt request flag */ +#define bsyaei fst_addr.bit.b1 /* Flash access error interrupt request flag */ +#define fst2 fst_addr.bit.b2 /* LBDATA monitor flag */ +#define fst3 fst_addr.bit.b3 /* Program-suspend status flag */ +#define fst4 fst_addr.bit.b4 /* Program error status flag */ +#define fst5 fst_addr.bit.b5 /* Erase error/blank check error status flag */ +#define fst6 fst_addr.bit.b6 /* Erase-suspend status flag */ +#define fst7 fst_addr.bit.b7 /* Ready/busy status flag */ + +/*------------------------------------------------------ + Flash Memory Control Register 0 +------------------------------------------------------*/ +union byte_def fmr0_addr; +#define fmr0 fmr0_addr.byte + +#define fmr01 fmr0_addr.bit.b1 /* CPU rewrite mode select bit */ +#define fmr02 fmr0_addr.bit.b2 /* EW1 mode select bit */ +#define fmstp fmr0_addr.bit.b3 /* Flash memory stop bit */ +#define cmdrst fmr0_addr.bit.b4 /* Erase/write sequence reset bit */ +#define cmderie fmr0_addr.bit.b5 /* Erase/write error, blank check error, command error interrupt enable bit */ +#define bsyaeie fmr0_addr.bit.b6 /* Flash access error interrupt enable bit */ +#define rdystie fmr0_addr.bit.b7 /* Flash ready status interrupt enable bit */ + +/*------------------------------------------------------ + Flash Memory Control Register 1 +------------------------------------------------------*/ +union byte_def fmr1_addr; +#define fmr1 fmr1_addr.byte + +#define wtfmstp fmr1_addr.bit.b2 /* Flash memory stop bit in wait mode */ +#define fmr13 fmr1_addr.bit.b3 /* Lock bit disable select bit */ +#define fmr16 fmr1_addr.bit.b6 /* Data flash block A rewrite disable bit */ +#define fmr17 fmr1_addr.bit.b7 /* Data flash block B rewrite disable bit */ + +/*------------------------------------------------------ + Flash Memory Control Register 2 +------------------------------------------------------*/ +union byte_def fmr2_addr; +#define fmr2 fmr2_addr.byte + +#define fmr20 fmr2_addr.bit.b0 /* Suspend enable bit */ +#define fmr21 fmr2_addr.bit.b1 /* Suspend request bit */ +#define fmr22 fmr2_addr.bit.b2 /* Interrupt request suspend request enable bit */ +#define fmr27 fmr2_addr.bit.b7 /* Low-current-consumption read mode enable bit */ + +/*------------------------------------------------------ + Flash Memory Refresh Control Register +------------------------------------------------------*/ +union byte_def frefr_addr; +#define frefr frefr_addr.byte + +#define ref0 frefr_addr.bit.b0 /* Periodic refresh interval control bit */ +#define ref1 frefr_addr.bit.b1 /* Periodic refresh interval control bit */ +#define ref2 frefr_addr.bit.b2 /* Periodic refresh interval control bit */ +#define ref3 frefr_addr.bit.b3 /* Periodic refresh interval control bit */ +#define ref4 frefr_addr.bit.b4 /* Periodic refresh interval control bit */ +#define ref5 frefr_addr.bit.b5 /* Periodic refresh interval control bit */ + +/*------------------------------------------------------ + Address Match Interrupt Register 0 +------------------------------------------------------*/ +union dword_def aiadr0_addr; +#define aiadr0 aiadr0_addr.dword /* Address Match Interrupt Register 0 */ + +#define aiadr0l aiadr0_addr.byte.low /* Address Match Interrupt Register 0 Low */ +#define aiadr0m aiadr0_addr.byte.mid /* Address Match Interrupt Register 0 Middle */ +#define aiadr0h aiadr0_addr.byte.high /* Address Match Interrupt Register 0 High */ + +/*------------------------------------------------------ + Address Match Interrupt Enable Register 0 +------------------------------------------------------*/ +union byte_def aien0_addr; +#define aien0 aien0_addr.byte + +#define aien00 aien0_addr.bit.b0 /* Address match interrupt enable 0 bit */ + +/*------------------------------------------------------ + Address Match Interrupt Register 1 +------------------------------------------------------*/ +union dword_def aiadr1_addr; +#define aiadr1 aiadr1_addr.dword /* Address Match Interrupt Register 1 */ + +#define aiadr1l aiadr1_addr.byte.low /* Address Match Interrupt Register 1 Low */ +#define aiadr1m aiadr1_addr.byte.mid /* Address Match Interrupt Register 1 Middle */ +#define aiadr1h aiadr1_addr.byte.high /* Address Match Interrupt Register 1 High */ + +/*------------------------------------------------------ + Address Match Interrupt Enable Register 1 +------------------------------------------------------*/ +union byte_def aien1_addr; +#define aien1 aien1_addr.byte + +#define aien10 aien1_addr.bit.b0 /* Address match interrupt enable 1 bit */ + + diff --git a/sfr_r8m12a.inc b/sfr_r8m12a.inc new file mode 100644 index 0000000..8f71ecc --- /dev/null +++ b/sfr_r8m12a.inc @@ -0,0 +1,1286 @@ +;------------------------------------------------------------------------ +; | +; | +; | +; DESCRIPTION :define the sfr register. (for Assembler language) | +; | +; | +; This file is generated by Renesas Project Generator. | +; | +;------------------------------------------------------------------------ +;/*********************************************************************** +;* +;* Device : R8C/M12A +;* +;* File Name : sfr_r8m12a.inc +;* +;* Abstract : definition of R8C/M12A Group SFR +;* +;* History : 2.00 ( 2010-12-03 ) [User's Manual: Hardware Rev.1.00] +;* : 1.10 ( 2010-06-24 ) [User's Manual: Hardware Rev.0.10] +;* : 1.00 ( 2010-02-26 ) [User's Manual: Hardware Rev.0.01] +;* +;* NOTE : THIS IS A TYPICAL EXAMPLE. +;* +;* Copyright (C) 2010 Renesas Electronics Corporation. +;* and Renesas Solutions Corp. +;* +;************************************************************************/ +; +;------------------------------------------------------- +; Processor Mode Register 0 +;------------------------------------------------------- +pm0 .equ 0010h +; +srst .btequ 3,pm0 ; Software reset bit +; +;------------------------------------------------------- +; Module Standby Control Register +;------------------------------------------------------- +mstcr .equ 0012h +; +msttrj .btequ 0,mstcr ; Timer RJ2 standby bit +msttrb .btequ 1,mstcr ; Timer RB2 standby bit +mstad .btequ 4,mstcr ; A/D converter standby bit +msttrc .btequ 5,mstcr ; Timer RC standby bit +mstuart .btequ 6,mstcr ; UART0 standby bit +; +;------------------------------------------------------- +; Protect Register +;------------------------------------------------------- +prcr .equ 0013h +; +prc0 .btequ 0,prcr ; Protect bit 0 +prc1 .btequ 1,prcr ; Protect bit 1 +prc3 .btequ 3,prcr ; Protect bit 3 +prc4 .btequ 4,prcr ; Protect bit 4 +; +;------------------------------------------------------- +; Hardware Reset Protect Register +;------------------------------------------------------- +hrpr .equ 0016h +; +pamcre .btequ 0,hrpr ; PAMCR register write enable bit +; +;------------------------------------------------------- +; External Clock Control Register +;------------------------------------------------------- +exckcr .equ 0020h +; +ckpt0 .btequ 0,exckcr ; P4_6 and P4_7 pin function select bit +ckpt1 .btequ 1,exckcr ; P4_6 and P4_7 pin function select bit +xrcut .btequ 6,exckcr ; XIN-XOUT on-chip feedback resistor select bit +; +;------------------------------------------------------- +; High-Speed/Low-Speed On-Chip Oscillator Control Register +;------------------------------------------------------- +ococr .equ 0021h +; +hocoe .btequ 0,ococr ; High-speed on-chip oscillator oscillation enable bit +locodis .btequ 1,ococr ; Low-speed on-chip oscillator oscillation stop bit +; +;------------------------------------------------------- +; System Clock f Control Register +;------------------------------------------------------- +sckcr .equ 0022h +; +phissel0 .btequ 0,sckcr ; CPU clock division ratio select bit +phissel1 .btequ 1,sckcr ; CPU clock division ratio select bit +phissel2 .btequ 2,sckcr ; CPU clock division ratio select bit +waitm .btequ 5,sckcr ; Wait control bit +hscksel .btequ 6,sckcr ; High-speed on-chip oscillator/XIN clock select bit +; +;------------------------------------------------------- +; System Clock f Select Register +;------------------------------------------------------- +phisel .equ 0023h +; +phisel0 .btequ 0,phisel ; System clock division select bit select bit +phisel1 .btequ 1,phisel ; System clock division select bit select bit +phisel2 .btequ 2,phisel ; System clock division select bit select bit +phisel3 .btequ 3,phisel ; System clock division select bit select bit +phisel4 .btequ 4,phisel ; System clock division select bit select bit +phisel5 .btequ 5,phisel ; System clock division select bit select bit +phisel6 .btequ 6,phisel ; System clock division select bit select bit +phisel7 .btequ 7,phisel ; System clock division select bit select bit +; +;------------------------------------------------------- +; Clock Stop Control Register +;------------------------------------------------------- +ckstpr .equ 0024h +; +stpm .btequ 0,ckstpr ; All clock stop control bit +wckstp .btequ 1,ckstpr ; fBASE stop bit in wait mode +pscstp .btequ 2,ckstpr ; Prescaler stop bit +scksel .btequ 7,ckstpr ; System base clock select bit +; +;------------------------------------------------------- +; Clock Control Register When Returning from Modes +;------------------------------------------------------- +ckrscr .equ 0025h +; +ckst0 .btequ 0,ckrscr ; Clock oscillator circuit oscillation stabilization state select bit +ckst1 .btequ 1,ckrscr ; Clock oscillator circuit oscillation stabilization state select bit +ckst2 .btequ 2,ckrscr ; Clock oscillator circuit oscillation stabilization state select bit +ckst3 .btequ 3,ckrscr ; Clock oscillator circuit oscillation stabilization state select bit +phisrs .btequ 5,ckrscr ; CPU clock division select bit when returning from wait mode or stop mode +waitrs .btequ 6,ckrscr ; System base clock select bit when returning from wait mode +stoprs .btequ 7,ckrscr ; System base clock select bit when returning from stop mode +; +;------------------------------------------------------- +; Oscillation Stop Detection Register +;------------------------------------------------------- +bakcr .equ 0026h +; +xinbake .btequ 0,bakcr ; Oscillation stop detection enable bit +ckswie .btequ 1,bakcr ; Oscillation stop detection interrupt enable bit +xinhalt .btequ 2,bakcr ; Clock monitor bit +ckswif .btequ 3,bakcr ; Oscillation stop detection interrupt request flag +; +;------------------------------------------------------- +; Watchdog Timer Function Register +;------------------------------------------------------- +risr .equ 0030h +; +ufif .btequ 6,risr ; WDT underflow detection flag +ris .btequ 7,risr ; WDT interrupt/reset switch bit +; +;------------------------------------------------------- +; Watchdog Timer Reset Register +;------------------------------------------------------- +wdtr .equ 0031h +; +;------------------------------------------------------- +; Watchdog Timer Start Register +;------------------------------------------------------- +wdts .equ 0032h +; +;------------------------------------------------------- +; Watchdog Timer Control Register +;------------------------------------------------------- +wdtc .equ 0033h +; +wdtc6 .btequ 6,wdtc ; Watchdog timer count source select bit +wdtc7 .btequ 7,wdtc ; Watchdog timer count source select bit +; +;------------------------------------------------------- +; Count Source Protection Mode Register +;------------------------------------------------------- +cspr .equ 0034h +; +cspro .btequ 7,cspr ; Count source protection mode select bit +; +;------------------------------------------------------- +; Periodic Timer Interrupt Control Register +;------------------------------------------------------- +wdtir .equ 0035h +; +wdtif .btequ 6,wdtir ; Periodic timer interrupt request flag +wdtie .btequ 7,wdtir ; Periodic timer interrupt enable bit +; +;------------------------------------------------------- +; External Input Enable Register +;------------------------------------------------------- +inten .equ 0038h +; +int0en .btequ 0,inten ; INT0 input enable bit +int1en .btequ 1,inten ; INT1 input enable bit +int2en .btequ 2,inten ; INT2 input enable bit +int3en .btequ 3,inten ; INT3 input enable bit +; +;------------------------------------------------------- +; INT Input Filter Select Register 0 +;------------------------------------------------------- +intf0 .equ 003Ah +; +int0f0 .btequ 0,intf0 ; INT0 input filter select bit +int0f1 .btequ 1,intf0 ; INT0 input filter select bit +int1f0 .btequ 2,intf0 ; INT1 input filter select bit +int1f1 .btequ 3,intf0 ; INT1 input filter select bit +int2f0 .btequ 4,intf0 ; INT2 input filter select bit +int2f1 .btequ 5,intf0 ; INT2 input filter select bit +int3f0 .btequ 6,intf0 ; INT3 input filter select bit +int3f1 .btequ 7,intf0 ; INT3 input filter select bit +; +;------------------------------------------------------- +; INT Input Edge Select Register 0 +;------------------------------------------------------- +iscr0 .equ 003Ch +; +int0sa .btequ 0,iscr0 ; INT0 input edge select bit +int0sb .btequ 1,iscr0 ; INT0 input edge select bit +int1sa .btequ 2,iscr0 ; INT1 input edge select bit +int1sb .btequ 3,iscr0 ; INT1 input edge select bit +int2sa .btequ 4,iscr0 ; INT2 input edge select bit +int2sb .btequ 5,iscr0 ; INT2 input edge select bit +int3sa .btequ 6,iscr0 ; INT3 input edge select bit +int3sb .btequ 7,iscr0 ; INT3 input edge select bit +; +;------------------------------------------------------- +; Key Input Enable Register +;------------------------------------------------------- +kien .equ 003Eh +; +ki0en .btequ 0,kien ; KI0 input enable bit +ki0pl .btequ 1,kien ; KI0 input edge select bit +ki1en .btequ 2,kien ; KI1 input enable bit +ki1pl .btequ 3,kien ; KI1 input edge select bit +ki2en .btequ 4,kien ; KI2 input enable bit +ki2pl .btequ 5,kien ; KI2 input edge select bit +ki3en .btequ 6,kien ; KI3 input enable bit +ki3pl .btequ 7,kien ; KI3 input edge select bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 0 +;------------------------------------------------------- +ilvl0 .equ 0040h +; +ilvl00 .btequ 0,ilvl0 ; Interrupt priority level setting bit +ilvl01 .btequ 1,ilvl0 ; Interrupt priority level setting bit +ilvl04 .btequ 4,ilvl0 ; Interrupt priority level setting bit +ilvl05 .btequ 5,ilvl0 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 2 +;------------------------------------------------------- +ilvl2 .equ 0042h +; +ilvl20 .btequ 0,ilvl2 ; Interrupt priority level setting bit +ilvl21 .btequ 1,ilvl2 ; Interrupt priority level setting bit +ilvl24 .btequ 4,ilvl2 ; Interrupt priority level setting bit +ilvl25 .btequ 5,ilvl2 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 3 +;------------------------------------------------------- +ilvl3 .equ 0043h +; +ilvl30 .btequ 0,ilvl3 ; Interrupt priority level setting bit +ilvl31 .btequ 1,ilvl3 ; Interrupt priority level setting bit +ilvl34 .btequ 4,ilvl3 ; Interrupt priority level setting bit +ilvl35 .btequ 5,ilvl3 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 4 +;------------------------------------------------------- +ilvl4 .equ 0044h +; +ilvl40 .btequ 0,ilvl4 ; Interrupt priority level setting bit +ilvl41 .btequ 1,ilvl4 ; Interrupt priority level setting bit +ilvl44 .btequ 4,ilvl4 ; Interrupt priority level setting bit +ilvl45 .btequ 5,ilvl4 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 5 +;------------------------------------------------------- +ilvl5 .equ 0045h +; +ilvl50 .btequ 0,ilvl5 ; Interrupt priority level setting bit +ilvl51 .btequ 1,ilvl5 ; Interrupt priority level setting bit +ilvl54 .btequ 4,ilvl5 ; Interrupt priority level setting bit +ilvl55 .btequ 5,ilvl5 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 6 +;------------------------------------------------------- +ilvl6 .equ 0046h +; +ilvl60 .btequ 0,ilvl6 ; Interrupt priority level setting bit +ilvl61 .btequ 1,ilvl6 ; Interrupt priority level setting bit +ilvl64 .btequ 4,ilvl6 ; Interrupt priority level setting bit +ilvl65 .btequ 5,ilvl6 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 7 +;------------------------------------------------------- +ilvl7 .equ 0047h +; +ilvl70 .btequ 0,ilvl7 ; Interrupt priority level setting bit +ilvl71 .btequ 1,ilvl7 ; Interrupt priority level setting bit +ilvl74 .btequ 4,ilvl7 ; Interrupt priority level setting bit +ilvl75 .btequ 5,ilvl7 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 8 +;------------------------------------------------------- +ilvl8 .equ 0048h +; +ilvl80 .btequ 0,ilvl8 ; Interrupt priority level setting bit +ilvl81 .btequ 1,ilvl8 ; Interrupt priority level setting bit +ilvl84 .btequ 4,ilvl8 ; Interrupt priority level setting bit +ilvl85 .btequ 5,ilvl8 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 9 +;------------------------------------------------------- +ilvl9 .equ 0049h +; +ilvl90 .btequ 0,ilvl9 ; Interrupt priority level setting bit +ilvl91 .btequ 1,ilvl9 ; Interrupt priority level setting bit +ilvl94 .btequ 4,ilvl9 ; Interrupt priority level setting bit +ilvl95 .btequ 5,ilvl9 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register A +;------------------------------------------------------- +ilvla .equ 004Ah +; +ilvla0 .btequ 0,ilvla ; Interrupt priority level setting bit +ilvla1 .btequ 1,ilvla ; Interrupt priority level setting bit +ilvla4 .btequ 4,ilvla ; Interrupt priority level setting bit +ilvla5 .btequ 5,ilvla ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register B +;------------------------------------------------------- +ilvlb .equ 004Bh +; +ilvlb0 .btequ 0,ilvlb ; Interrupt priority level setting bit +ilvlb1 .btequ 1,ilvlb ; Interrupt priority level setting bit +ilvlb4 .btequ 4,ilvlb ; Interrupt priority level setting bit +ilvlb5 .btequ 5,ilvlb ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register C +;------------------------------------------------------- +ilvlc .equ 004Ch +; +ilvlc0 .btequ 0,ilvlc ; Interrupt priority level setting bit +ilvlc1 .btequ 1,ilvlc ; Interrupt priority level setting bit +ilvlc4 .btequ 4,ilvlc ; Interrupt priority level setting bit +ilvlc5 .btequ 5,ilvlc ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register D +;------------------------------------------------------- +ilvld .equ 004Dh +; +ilvld0 .btequ 0,ilvld ; Interrupt priority level setting bit +ilvld1 .btequ 1,ilvld ; Interrupt priority level setting bit +ilvld4 .btequ 4,ilvld ; Interrupt priority level setting bit +ilvld5 .btequ 5,ilvld ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register E +;------------------------------------------------------- +ilvle .equ 004Eh +; +ilvle0 .btequ 0,ilvle ; Interrupt priority level setting bit +ilvle1 .btequ 1,ilvle ; Interrupt priority level setting bit +ilvle4 .btequ 4,ilvle ; Interrupt priority level setting bit +ilvle5 .btequ 5,ilvle ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Monitor Flag Register 0 +;------------------------------------------------------- +irr0 .equ 0050h +; +irtj .btequ 0,irr0 ; Timer RJ2 interrupt request monitor flag +irtb .btequ 1,irr0 ; Timer RB2 interrupt request monitor flag +irtc .btequ 2,irr0 ; Timer RC interrupt request monitor flag +irs0t .btequ 4,irr0 ; UART0 transmit interrupt request monitor flag +irs0r .btequ 5,irr0 ; UART0 receive interrupt request monitor flag +; +;------------------------------------------------------- +; Interrupt Monitor Flag Register 1 +;------------------------------------------------------- +irr1 .equ 0051h +; +irad .btequ 2,irr1 ; A/D conversion interrupt request monitor flag +irfm .btequ 4,irr1 ; Flash ready interrupt request monitor flag +irwd .btequ 5,irr1 ; Periodic timer interrupt request monitor flag +; +;------------------------------------------------------- +; Interrupt Monitor Flag Register 2 +;------------------------------------------------------- +irr2 .equ 0052h +; +ircmp1 .btequ 2,irr2 ; Comparator B1 interrupt request monitor flag +ircmp3 .btequ 3,irr2 ; Comparator B3 interrupt request monitor flag +; +;------------------------------------------------------- +; External Interrupt Flag Register +;------------------------------------------------------- +irr3 .equ 0053h +; +iri0 .btequ 0,irr3 ; INT0 interrupt request flag +iri1 .btequ 1,irr3 ; INT1 interrupt request flag +iri2 .btequ 2,irr3 ; INT2 interrupt request flag +iri3 .btequ 3,irr3 ; INT3 interrupt request flag +irki .btequ 5,irr3 ; Key input interrupt request flag +; +;------------------------------------------------------- +; Voltage Monitor Circuit Edge Select Register +;------------------------------------------------------- +vcac .equ 0058h +; +vcac1 .btequ 1,vcac ; Voltage monitor 1 circuit edge select bit +; +;------------------------------------------------------- +; Voltage Detect Register 2 +;------------------------------------------------------- +vca2 .equ 005Ah +; +lpe .btequ 0,vca2 ; Internal low-power-consumption enable bit +vc0e .btequ 5,vca2 ; Voltage detection 0 enable bit +vc1e .btequ 6,vca2 ; Voltage detection 1 enable bit +; +;------------------------------------------------------- +; Voltage Detection 1 Level Select Register +;------------------------------------------------------- +vd1ls .equ 005Bh +; +vd1s1 .btequ 1,vd1ls ; Voltage detection 1 Level select bit +vd1s2 .btequ 2,vd1ls ; Voltage detection 1 Level select bit +vd1s3 .btequ 3,vd1ls ; Voltage detection 1 Level select bit +; +;------------------------------------------------------- +; Voltage Monitor 0 Circuit Control Register +;------------------------------------------------------- +vw0c .equ 005Ch +; +vw0c0 .btequ 0,vw0c ; Voltage monitor 0 reset enable bit +vw0c1 .btequ 1,vw0c ; Voltage monitor 0 digital filter mode select bit +vw0f0 .btequ 4,vw0c ; Sampling clock select bit +vw0f1 .btequ 5,vw0c ; Sampling clock select bit +; +;------------------------------------------------------- +; Voltage Monitor 1 Circuit Control Register +;------------------------------------------------------- +vw1c .equ 005Dh +; +vw1c0 .btequ 0,vw1c ; Voltage monitor 1 interrupt enable bit +vw1c1 .btequ 1,vw1c ; Voltage monitor 1 digital filter mode select bit +vw1c2 .btequ 2,vw1c ; Voltage change detection flag +vw1c3 .btequ 3,vw1c ; Voltage detection 1 signal monitor flag +vw1f0 .btequ 4,vw1c ; Sampling clock select bit +vw1f1 .btequ 5,vw1c ; Sampling clock select bit +vw1c7 .btequ 7,vw1c ; Voltage monitor 1 interrupt generation condition select bit +; +;------------------------------------------------------- +; Reset Source Determination Register +;------------------------------------------------------- +rstfr .equ 005Fh +; +cwr .btequ 0,rstfr ; Cold start-up/warm start-up determine flag +hwr .btequ 1,rstfr ; Hardware reset detect flag +swr .btequ 2,rstfr ; Software reset detect flag +wdr .btequ 3,rstfr ; Watchdog timer reset detect flag +; +;------------------------------------------------------- +; High-Speed On-Chip Oscillator 18.432 MHz Control Register 0 +;------------------------------------------------------- +fr18s0 .equ 0064h +; +;------------------------------------------------------- +; High-Speed On-Chip Oscillator 18.432 MHz Control Register 1 +;------------------------------------------------------- +fr18s1 .equ 0065h +; +;------------------------------------------------------- +; High-Speed On-Chip Oscillator Control Register 1 +;------------------------------------------------------- +frv1 .equ 0067h +; +;------------------------------------------------------- +; High-Speed On-Chip Oscillator Control Register 2 +;------------------------------------------------------- +frv2 .equ 0068h +; +;------------------------------------------------------- +; UART0 Transmit/Receive Mode Register +;------------------------------------------------------- +u0mr .equ 0080h +; +smd0_u0mr .btequ 0,u0mr ; Serial I/O mode select bit +smd1_u0mr .btequ 1,u0mr ; Serial I/O mode select bit +smd2_u0mr .btequ 2,u0mr ; Serial I/O mode select bit +ckdir_u0mr .btequ 3,u0mr ; Internal/external clock select bit +stps_u0mr .btequ 4,u0mr ; Stop bit length select bit +pry_u0mr .btequ 5,u0mr ; Odd/even parity select bit +prye_u0mr .btequ 6,u0mr ; Parity enable bit +; +;------------------------------------------------------- +; UART0 Bit Rate Register +;------------------------------------------------------- +u0brg .equ 0081h +; +;------------------------------------------------------- +; UART0 Transmit Buffer Register Low +;------------------------------------------------------- +u0tbl .equ 0082h +; +;------------------------------------------------------- +; UART0 Transmit Buffer Register High +;------------------------------------------------------- +u0tbh .equ 0083h +; +;------------------------------------------------------- +; UART0 Transmit/Receive Control Register 0 +;------------------------------------------------------- +u0c0 .equ 0084h +; +clk0_u0c0 .btequ 0,u0c0 ; U0BRG count source select bit +clk1_u0c0 .btequ 1,u0c0 ; U0BRG count source select bit +txept_u0c0 .btequ 3,u0c0 ; Transmit register empty flag +dfe_u0c0 .btequ 4,u0c0 ; RXD0 digital filter enable bit +nch_u0c0 .btequ 5,u0c0 ; Data output select bit +ckpol_u0c0 .btequ 6,u0c0 ; CLK polarity select bit +uform_u0c0 .btequ 7,u0c0 ; Transfer format select bit +; +;------------------------------------------------------- +; UART0 Transmit/Receive Control Register 1 +;------------------------------------------------------- +u0c1 .equ 0085h +; +te_u0c1 .btequ 0,u0c1 ; Transmit enable bit +ti_u0c1 .btequ 1,u0c1 ; Transmit buffer empty flag +re_u0c1 .btequ 2,u0c1 ; Receive enable bit +ri_u0c1 .btequ 3,u0c1 ; Receive complete flag +u0irs_u0c1 .btequ 4,u0c1 ; UART0 transmit interrupt source select bit +u0rrm_u0c1 .btequ 5,u0c1 ; UART0 continuous receive mode enable bit +; +;------------------------------------------------------- +; UART0 Receive Buffer Register +;------------------------------------------------------- +u0rb .equ 0086h +; +;------------------------------------------------------- +; UART0 Interrupt Flag and Enable Register +;------------------------------------------------------- +u0ir .equ 0088h +; +u0rie .btequ 2,u0ir ; UART0 receive interrupt enable bit +u0tie .btequ 3,u0ir ; UART0 transmit interrupt enable bit +u0rif .btequ 6,u0ir ; UART0 receive interrupt flag +u0tif .btequ 7,u0ir ; UART0 transmit interrupt flag +; +;------------------------------------------------------- +; A/D Register 0 +;------------------------------------------------------- +ad0 .equ 0098h +; +ad0l .equ ad0 ; Low +ad0h .equ ad0+1 ; High +; +;------------------------------------------------------- +; A/D Register 1 +;------------------------------------------------------- +ad1 .equ 009Ah +; +ad1l .equ ad1 ; Low +ad1h .equ ad1+1 ; High +; +;------------------------------------------------------- +; A/D Mode Register +;------------------------------------------------------- +admod .equ 009Ch +; +cks0 .btequ 0,admod ; A/D conversion clock select bit +cks1 .btequ 1,admod ; A/D conversion clock select bit +cks2 .btequ 2,admod ; A/D conversion clock select bit +md0 .btequ 3,admod ; A/D operating mode select bit +md1 .btequ 4,admod ; A/D operating mode select bit +adcap0 .btequ 6,admod ; A/D conversion trigger select bit +adcap1 .btequ 7,admod ; A/D conversion trigger select bit +; +;------------------------------------------------------- +; A/D Input Select Register +;------------------------------------------------------- +adinsel .equ 009Dh +; +ch0 .btequ 0,adinsel ; Channel select bit +adgsel0 .btequ 6,adinsel ; A/D input group select bit +adgsel1 .btequ 7,adinsel ; A/D input group select bit +; +;------------------------------------------------------- +; A/D Control Register 0 +;------------------------------------------------------- +adcon0 .equ 009Eh +; +adst .btequ 0,adcon0 ; A/D conversion start bit +; +;------------------------------------------------------- +; A/D Interrupt Control Status Register +;------------------------------------------------------- +adicsr .equ 009Fh +; +adie .btequ 6,adicsr ; A/D conversion interrupt enable bit +adf .btequ 7,adicsr ; A/D conversion Interrupt request bit +; +;------------------------------------------------------- +; Port P1 Direction Register +;------------------------------------------------------- +pd1 .equ 00A9h +; +pd1_0 .btequ 0,pd1 ; Port P1_0 direction bit +pd1_1 .btequ 1,pd1 ; Port P1_1 direction bit +pd1_2 .btequ 2,pd1 ; Port P1_2 direction bit +pd1_3 .btequ 3,pd1 ; Port P1_3 direction bit +pd1_4 .btequ 4,pd1 ; Port P1_4 direction bit +pd1_5 .btequ 5,pd1 ; Port P1_5 direction bit +pd1_6 .btequ 6,pd1 ; Port P1_6 direction bit +pd1_7 .btequ 7,pd1 ; Port P1_7 direction bit +; +;------------------------------------------------------- +; Port P3 Direction Register +;------------------------------------------------------- +pd3 .equ 00ABh +; +pd3_3 .btequ 3,pd3 ; Port P3_3 direction bit +pd3_4 .btequ 4,pd3 ; Port P3_4 direction bit +pd3_5 .btequ 5,pd3 ; Port P3_5 direction bit +pd3_7 .btequ 7,pd3 ; Port P3_7 direction bit +; +;------------------------------------------------------- +; Port P4 Direction Register +;------------------------------------------------------- +pd4 .equ 00ACh +; +pd4_2 .btequ 2,pd4 ; Port P4_2 direction bit +pd4_5 .btequ 5,pd4 ; Port P4_5 direction bit +pd4_6 .btequ 6,pd4 ; Port P4_6 direction bit +pd4_7 .btequ 7,pd4 ; Port P4_7 direction bit +; +;------------------------------------------------------- +; Port PA Direction Register +;------------------------------------------------------- +pda .equ 00ADh +; +pda_0 .btequ 0,pda ; Port PA_0 direction bit +; +;------------------------------------------------------- +; Port P1 Register +;------------------------------------------------------- +p1 .equ 00AFh +; +p1_0 .btequ 0,p1 ; Port P1_0 bit +p1_1 .btequ 1,p1 ; Port P1_1 bit +p1_2 .btequ 2,p1 ; Port P1_2 bit +p1_3 .btequ 3,p1 ; Port P1_3 bit +p1_4 .btequ 4,p1 ; Port P1_4 bit +p1_5 .btequ 5,p1 ; Port P1_5 bit +p1_6 .btequ 6,p1 ; Port P1_6 bit +p1_7 .btequ 7,p1 ; Port P1_7 bit +; +;------------------------------------------------------- +; Port P3 Register +;------------------------------------------------------- +p3 .equ 00B1h +; +p3_3 .btequ 3,p3 ; Port P3_3 bit +p3_4 .btequ 4,p3 ; Port P3_4 bit +p3_5 .btequ 5,p3 ; Port P3_5 bit +p3_7 .btequ 7,p3 ; Port P3_7 bit +; +;------------------------------------------------------- +; Port P4 Register +;------------------------------------------------------- +p4 .equ 00B2h +; +p4_2 .btequ 2,p4 ; Port P4_2 bit +p4_5 .btequ 5,p4 ; Port P4_5 bit +p4_6 .btequ 6,p4 ; Port P4_6 bit +p4_7 .btequ 7,p4 ; Port P4_7 bit +; +;------------------------------------------------------- +; Port PA Register +;------------------------------------------------------- +pa .equ 00B3h +; +pa_0 .btequ 0,pa ; Port PA_0 bit +; +;------------------------------------------------------- +; Pull-Up Control Register 1 +;------------------------------------------------------- +pur1 .equ 00B5h +; +pu1_0 .btequ 0,pur1 ; Port P1_0 pull-up control bit +pu1_1 .btequ 1,pur1 ; Port P1_1 pull-up control bit +pu1_2 .btequ 2,pur1 ; Port P1_2 pull-up control bit +pu1_3 .btequ 3,pur1 ; Port P1_3 pull-up control bit +pu1_4 .btequ 4,pur1 ; Port P1_4 pull-up control bit +pu1_5 .btequ 5,pur1 ; Port P1_5 pull-up control bit +pu1_6 .btequ 6,pur1 ; Port P1_6 pull-up control bit +pu1_7 .btequ 7,pur1 ; Port P1_7 pull-up control bit +; +;------------------------------------------------------- +; Pull-Up Control Register 3 +;------------------------------------------------------- +pur3 .equ 00B7h +; +pu3_3 .btequ 3,pur3 ; Port P3_3 pull-up control bit +pu3_4 .btequ 4,pur3 ; Port P3_4 pull-up control bit +pu3_5 .btequ 5,pur3 ; Port P3_5 pull-up control bit +pu3_7 .btequ 7,pur3 ; Port P3_7 pull-up control bit +; +;------------------------------------------------------- +; Pull-Up Control Register 4 +;------------------------------------------------------- +pur4 .equ 00B8h +; +pu4_2 .btequ 2,pur4 ; Port P4_2 pull-up control bit +pu4_5 .btequ 5,pur4 ; Port P4_5 pull-up control bit +pu4_6 .btequ 6,pur4 ; Port P4_6 pull-up control bit +pu4_7 .btequ 7,pur4 ; Port P4_7 pull-up control bit +; +;------------------------------------------------------- +; Port I/O Function Control Register +;------------------------------------------------------- +pinsr .equ 00B9h +; +trjiosel .btequ 6,pinsr ; TRJIO input signal select bit +ioinsel .btequ 7,pinsr ; Pin level force read-out bit +; +;------------------------------------------------------- +; Drive Capacity Control Register 1 +;------------------------------------------------------- +drr1 .equ 00BBh +; +drr1_2 .btequ 2,drr1 ; Port P1_2 drive capacity control bit +drr1_3 .btequ 3,drr1 ; Port P1_3 drive capacity control bit +drr1_4 .btequ 4,drr1 ; Port P1_4 drive capacity control bit +drr1_5 .btequ 5,drr1 ; Port P1_5 drive capacity control bit +; +;------------------------------------------------------- +; Drive Capacity Control Register 3 +;------------------------------------------------------- +drr3 .equ 00BDh +; +drr3_3 .btequ 3,drr3 ; Port P3_3 drive capacity control bit +drr3_4 .btequ 4,drr3 ; Port P3_4 drive capacity control bit +drr3_5 .btequ 5,drr3 ; Port P3_5 drive capacity control bit +drr3_7 .btequ 7,drr3 ; Port P3_7 drive capacity control bit +; +;------------------------------------------------------- +; Open-Drain Control Register 1 +;------------------------------------------------------- +pod1 .equ 00C1h +; +pod1_0 .btequ 0,pod1 ; Port P1_0 open-drain control bit +pod1_1 .btequ 1,pod1 ; Port P1_1 open-drain control bit +pod1_2 .btequ 2,pod1 ; Port P1_2 open-drain control bit +pod1_3 .btequ 3,pod1 ; Port P1_3 open-drain control bit +pod1_4 .btequ 4,pod1 ; Port P1_4 open-drain control bit +pod1_5 .btequ 5,pod1 ; Port P1_5 open-drain control bit +pod1_6 .btequ 6,pod1 ; Port P1_6 open-drain control bit +pod1_7 .btequ 7,pod1 ; Port P1_7 open-drain control bit +; +;------------------------------------------------------- +; Open-Drain Control Register 3 +;------------------------------------------------------- +pod3 .equ 00C3h +; +pod3_3 .btequ 3,pod3 ; Port P3_3 open-drain control bit +pod3_4 .btequ 4,pod3 ; Port P3_4 open-drain control bit +pod3_5 .btequ 5,pod3 ; Port P3_5 open-drain control bit +pod3_7 .btequ 7,pod3 ; Port P3_7 open-drain control bit +; +;------------------------------------------------------- +; Open-Drain Control Register 4 +;------------------------------------------------------- +pod4 .equ 00C4h +; +pod4_2 .btequ 2,pod4 ; Port P4_2 open-drain control bi +pod4_5 .btequ 5,pod4 ; Port P4_5 open-drain control bi +pod4_6 .btequ 6,pod4 ; Port P4_6 open-drain control bi +pod4_7 .btequ 7,pod4 ; Port P4_7 open-drain control bi +; +;------------------------------------------------------- +; Port PA Mode Control Register +;------------------------------------------------------- +pamcr .equ 00C5h +; +poda_0 .btequ 0,pamcr ; Port PA_0 open-drain control bit +hwrste .btequ 4,pamcr ; Hardware reset enabled bit +; +;------------------------------------------------------- +; Port 1 Function Mapping Register 0 +;------------------------------------------------------- +pml1 .equ 00C8h +; +p10sel0 .btequ 0,pml1 ; Port P1_0 function select bit +p10sel1 .btequ 1,pml1 ; Port P1_0 function select bit +p11sel0 .btequ 2,pml1 ; Port P1_1 function select bit +p11sel1 .btequ 3,pml1 ; Port P1_1 function select bit +p12sel0 .btequ 4,pml1 ; Port P1_2 function select bit +p12sel1 .btequ 5,pml1 ; Port P1_2 function select bit +p13sel0 .btequ 6,pml1 ; Port P1_3 function select bit +p13sel1 .btequ 7,pml1 ; Port P1_3 function select bit +; +;------------------------------------------------------- +; Port 1 Function Mapping Register 1 +;------------------------------------------------------- +pmh1 .equ 00C9h +; +p14sel0 .btequ 0,pmh1 ; Port P1_4 function select bit +p14sel1 .btequ 1,pmh1 ; Port P1_4 function select bit +p15sel0 .btequ 2,pmh1 ; Port P1_5 function select bit +p15sel1 .btequ 3,pmh1 ; Port P1_5 function select bit +p16sel0 .btequ 4,pmh1 ; Port P1_6 function select bit +p16sel1 .btequ 5,pmh1 ; Port P1_6 function select bit +p17sel0 .btequ 6,pmh1 ; Port P1_7 function select bit +p17sel1 .btequ 7,pmh1 ; Port P1_7 function select bit +; +;------------------------------------------------------- +; Port 3 Function Mapping Register 0 +;------------------------------------------------------- +pml3 .equ 00CCh +; +p33sel0 .btequ 6,pml3 ; Port P3_3 function select bit +p33sel1 .btequ 7,pml3 ; Port P3_3 function select bit +; +;------------------------------------------------------- +; Port 3 Function Mapping Register 1 +;------------------------------------------------------- +pmh3 .equ 00CDh +; +p34sel0 .btequ 0,pmh3 ; Port P3_4 function select bit +p34sel1 .btequ 1,pmh3 ; Port P3_4 function select bit +p35sel0 .btequ 2,pmh3 ; Port P3_5 function select bit +p35sel1 .btequ 3,pmh3 ; Port P3_5 function select bit +p37sel0 .btequ 6,pmh3 ; Port P3_7 function select bit +p37sel1 .btequ 7,pmh3 ; Port P3_7 function select bit +; +;------------------------------------------------------- +; Port 4 Function Mapping Register 0 +;------------------------------------------------------- +pml4 .equ 00CEh +; +p42sel0 .btequ 4,pml4 ; Port P4_2 function select bit +p42sel1 .btequ 5,pml4 ; Port P4_2 function select bit +; +;------------------------------------------------------- +; Port 4 Function Mapping Register 1 +;------------------------------------------------------- +pmh4 .equ 00CFh +; +p45sel0 .btequ 2,pmh4 ; Port P4_5 function select bit +p45sel1 .btequ 3,pmh4 ; Port P4_5 function select bit +p46sel0 .btequ 4,pmh4 ; Port P4_6 function select bit +p46sel1 .btequ 5,pmh4 ; Port P4_6 function select bit +p47sel0 .btequ 6,pmh4 ; Port P4_7 function select bit +p47sel1 .btequ 7,pmh4 ; Port P4_7 function select bit +; +;------------------------------------------------------- +; Port 1 Function Mapping Expansion Register +;------------------------------------------------------- +pmh1e .equ 00D1h +; +p14sel2 .btequ 0,pmh1e ; The P1_4 pin function is selected in conjunction with bits P14SEL0 to P14SEL1 in the PMH1 register +p15sel2 .btequ 2,pmh1e ; The P1_5 pin function is selected in conjunction with bits P15SEL0 to P15SEL1 in the PMH1 register +; +;------------------------------------------------------- +; Port 4 Function Mapping Expansion Register +;------------------------------------------------------- +pmh4e .equ 00D5h +; +p46sel2 .btequ 4,pmh4e ; The P4_6 pin function is selected in conjunction with bits P46SEL0 to P46SEL1 in the PMH4 register +; +;------------------------------------------------------- +; Timer RJ Counter Register, Timer RJ Reload Register +;------------------------------------------------------- +trj .equ 00D8h +; +;------------------------------------------------------- +; Timer RJ Control Register +;------------------------------------------------------- +trjcr .equ 00DAh +; +tstart_trjcr .btequ 0,trjcr ; Timer RJ count start bit +tcstf_trjcr .btequ 1,trjcr ; Timer RJ count status flag +tstop_trjcr .btequ 2,trjcr ; Timer RJ count forced stop bit +tedgf_trjcr .btequ 4,trjcr ; Active edge judgment flag +tundf_trjcr .btequ 5,trjcr ; Timer RJ underflow flag +; +;------------------------------------------------------- +; Timer RJ I/O Control Register +;------------------------------------------------------- +trjioc .equ 00DBh +; +tedgsel_trjioc .btequ 0,trjioc ; I/O polarity switch bit +topcr_trjioc .btequ 1,trjioc ; TRJIO output control bit +tipf0_trjioc .btequ 4,trjioc ; TRJIO input filter select bit +tipf1_trjioc .btequ 5,trjioc ; TRJIO input filter select bit +tiogt0_trjioc .btequ 6,trjioc ; TRJIO count control bit +tiogt1_trjioc .btequ 7,trjioc ; TRJIO count control bit +; +;------------------------------------------------------- +; Timer RJ Mode Register +;------------------------------------------------------- +trjmr .equ 00DCh +; +tmod0_trjmr .btequ 0,trjmr ; Timer RJ operating mode select bit +tmod1_trjmr .btequ 1,trjmr ; Timer RJ operating mode select bit +tmod2_trjmr .btequ 2,trjmr ; Timer RJ operating mode select bit +tedgpl_trjmr .btequ 3,trjmr ; TRJIO edge polarity select bit +tck0_trjmr .btequ 4,trjmr ; Timer RJ count source select bit +tck1_trjmr .btequ 5,trjmr ; Timer RJ count source select bit +tck2_trjmr .btequ 6,trjmr ; Timer RJ count source select bit +tckcut_trjmr .btequ 7,trjmr ; Timer RJ count source cutoff bit +; +;------------------------------------------------------- +; Timer RJ Event Select Register +;------------------------------------------------------- +trjisr .equ 00DDh +; +rccpsel0_trjisr .btequ 0,trjisr ; Timer RC output signal select bit +rccpsel1_trjisr .btequ 1,trjisr ; Timer RC output signal select bit +rccpsel2_trjisr .btequ 2,trjisr ; Timer RC output signal inversion bit +; +;------------------------------------------------------- +; Timer RJ Interrupt Control Register +;------------------------------------------------------- +trjir .equ 00DEh +; +trjif_trjir .btequ 6,trjir ; Timer RJ interrupt request flag +trjie_trjir .btequ 7,trjir ; Timer RJ interrupt enable bit +; +;------------------------------------------------------- +; Timer RB Control Register +;------------------------------------------------------- +trbcr .equ 00E0h +; +tstart_trbcr .btequ 0,trbcr ; Timer RB count start bit +tcstf_trbcr .btequ 1,trbcr ; Timer RB count status flag +tstop_trbcr .btequ 2,trbcr ; Timer RB count forced stop bit +; +;------------------------------------------------------- +; Timer RB One-Shot Control Register +;------------------------------------------------------- +trbocr .equ 00E1h +; +tosst_trbocr .btequ 0,trbocr ; Timer RB one-shot start bit +tossp_trbocr .btequ 1,trbocr ; Timer RB one-shot stop bit +tosstf_trbocr .btequ 2,trbocr ; Timer RB one-shot status flag +; +;------------------------------------------------------- +; Timer RB I/O Control Register +;------------------------------------------------------- +trbioc .equ 00E2h +; +topl_trbioc .btequ 0,trbioc ; Timer RB output level select bit +tocnt_trbioc .btequ 1,trbioc ; Timer RB output switch bit +inostg_trbioc .btequ 2,trbioc ; One-shot trigger control bit +inoseg_trbioc .btequ 3,trbioc ; One-shot trigger polarity select bit +; +;------------------------------------------------------- +; Timer RB Mode Register +;------------------------------------------------------- +trbmr .equ 00E3h +; +tmod0_trbmr .btequ 0,trbmr ; Timer RB operating mode select bit +tmod1_trbmr .btequ 1,trbmr ; Timer RB operating mode select bit +tcnt16_trbmr .btequ 2,trbmr ; Timer RB counter select bit +twrc_trbmr .btequ 3,trbmr ; Timer RB write control bit +tck0_trbmr .btequ 4,trbmr ; Timer RB count source select bit +tck1_trbmr .btequ 5,trbmr ; Timer RB count source select bit +tck2_trbmr .btequ 6,trbmr ; Timer RB count source select bit +tckcut_trbmr .btequ 7,trbmr ; Timer RB count source cutoff bit +; +;------------------------------------------------------- +; Timer RB Prescaler Register +;------------------------------------------------------- +trbpre .equ 00E4h +; +;------------------------------------------------------- +; Timer RB Primary Register +;------------------------------------------------------- +trbpr .equ 00E5h +; +;------------------------------------------------------- +; Timer RB Secondary Register +;------------------------------------------------------- +trbsc .equ 00E6h +; +;------------------------------------------------------- +; Timer RB Interrupt Control Register +;------------------------------------------------------- +trbir .equ 00E7h +; +trbif_trbir .btequ 6,trbir ; Timer RB interrupt request flag +trbie_trbir .btequ 7,trbir ; Timer RB interrupt enable bit +; +;------------------------------------------------------- +; Timer RC Counter +;------------------------------------------------------- +trccnt .equ 00E8h +; +;------------------------------------------------------- +; Timer RC General Register A +;------------------------------------------------------- +trcgra .equ 00EAh +; +;------------------------------------------------------- +; Timer RC General Register B +;------------------------------------------------------- +trcgrb .equ 00ECh +; +;------------------------------------------------------- +; Timer RC General Register C +;------------------------------------------------------- +trcgrc .equ 00EEh +; +;------------------------------------------------------- +; Timer RC General Register D +;------------------------------------------------------- +trcgrd .equ 00F0h +; +;------------------------------------------------------- +; Timer RC Mode Register +;------------------------------------------------------- +trcmr .equ 00F2h +; +pwmb_trcmr .btequ 0,trcmr ; TRCIOB PWM mode select bit +pwmc_trcmr .btequ 1,trcmr ; TRCIOC PWM mode select bit +pwmd_trcmr .btequ 2,trcmr ; TRCIOD PWM mode select bit +pwm2_trcmr .btequ 3,trcmr ; PWM2 mode select bit +bufea_trcmr .btequ 4,trcmr ; TRCGRC register function select bit +bufeb_trcmr .btequ 5,trcmr ; TRCGRD register function select bit +cts_trcmr .btequ 7,trcmr ; TRCCNT count start bit +; +;------------------------------------------------------- +; Timer RC Control Register 1 +;------------------------------------------------------- +trccr1 .equ 00F3h +; +toa_trccr1 .btequ 0,trccr1 ; Timer output level select A bit +tob_trccr1 .btequ 1,trccr1 ; Timer output level select B bit +toc_trccr1 .btequ 2,trccr1 ; Timer output level select C bit +tod_trccr1 .btequ 3,trccr1 ; Timer output level select D bit +cks0_trccr1 .btequ 4,trccr1 ; Count source select bit +cks1_trccr1 .btequ 5,trccr1 ; Count source select bit +cks2_trccr1 .btequ 6,trccr1 ; Count source select bit +cclr_trccr1 .btequ 7,trccr1 ; TRCCNT counter clear select bit +; +;------------------------------------------------------- +; Timer RC Interrupt Enable Register +;------------------------------------------------------- +trcier .equ 00F4h +; +imiea_trcier .btequ 0,trcier ; Input capture/compare match A interrupt enable bit +imieb_trcier .btequ 1,trcier ; Input capture/compare match B interrupt enable bit +imiec_trcier .btequ 2,trcier ; Input capture/compare match C interrupt enable bit +imied_trcier .btequ 3,trcier ; Input capture/compare match D interrupt enable bit +ovie_trcier .btequ 7,trcier ; Timer overflow interrupt enable bit +; +;------------------------------------------------------- +; Timer RC Status Register +;------------------------------------------------------- +trcsr .equ 00F5h +; +imfa_trcsr .btequ 0,trcsr ; Input capture/compare match A flag +imfb_trcsr .btequ 1,trcsr ; Input capture/compare match B flag +imfc_trcsr .btequ 2,trcsr ; Input capture/compare match C flag +imfd_trcsr .btequ 3,trcsr ; Input capture/compare match D flag +ovf_trcsr .btequ 7,trcsr ; Timer overflow flag +; +;------------------------------------------------------- +; Timer RC I/O Control Register 0 +;------------------------------------------------------- +trcior0 .equ 00F6h +; +ioa0_trcior0 .btequ 0,trcior0 ; TRCGRA control A0 bit +ioa1_trcior0 .btequ 1,trcior0 ; TRCGRA control A1 bit +ioa2_trcior0 .btequ 2,trcior0 ; TRCGRA control A2 bit +iob0_trcior0 .btequ 4,trcior0 ; TRCGRB control B0 bit +iob1_trcior0 .btequ 5,trcior0 ; TRCGRB control B1 bit +iob2_trcior0 .btequ 6,trcior0 ; TRCGRB control B2 bit +; +;------------------------------------------------------- +; Timer RC I/O Control Register 1 +;------------------------------------------------------- +trcior1 .equ 00F7h +; +ioc0_trcior1 .btequ 0,trcior1 ; TRCGRC control C0 bit +ioc1_trcior1 .btequ 1,trcior1 ; TRCGRC control C1 bit +ioc2_trcior1 .btequ 2,trcior1 ; TRCGRC control C2 bit +ioc3_trcior1 .btequ 3,trcior1 ; TRCGRC control C3 bit +iod0_trcior1 .btequ 4,trcior1 ; TRCGRD control D0 bit +iod1_trcior1 .btequ 5,trcior1 ; TRCGRD control D1 bit +iod2_trcior1 .btequ 6,trcior1 ; TRCGRD control D2 bit +iod3_trcior1 .btequ 7,trcior1 ; TRCGRD control D3 bit +; +;------------------------------------------------------- +; Timer RC Control Register 2 +;------------------------------------------------------- +trccr2 .equ 00F8h +; +polb_trccr2 .btequ 0,trccr2 ; TRCIOB PWM mode output level control bit +polc_trccr2 .btequ 1,trccr2 ; TRCIOC PWM mode output level control bit +pold_trccr2 .btequ 2,trccr2 ; TRCIOD PWM mode output level control bit +cstp_trccr2 .btequ 5,trccr2 ; Count stop bit +tceg0_trccr2 .btequ 6,trccr2 ; TRCTRG input edge select bit +tceg1_trccr2 .btequ 7,trccr2 ; TRCTRG input edge select bit +; +;------------------------------------------------------- +; Timer RC Digital Filter Function Select Register +;------------------------------------------------------- +trcdf .equ 00F9h +; +dfa_trcdf .btequ 0,trcdf ; TRCIOA digital filter function bit +dfb_trcdf .btequ 1,trcdf ; TRCIOB digital filter function bit +dfc_trcdf .btequ 2,trcdf ; TRCIOC digital filter function bit +dfd_trcdf .btequ 3,trcdf ; TRCIOD digital filter function bit +dftrg_trcdf .btequ 4,trcdf ; TRCTRG digital filter function bit +dfck0_trcdf .btequ 6,trcdf ; Digital filter clock select bit +dfck1_trcdf .btequ 7,trcdf ; Digital filter clock select bit +; +;------------------------------------------------------- +; Timer RC Output Enable Register +;------------------------------------------------------- +trcoer .equ 00FAh +; +ea_trcoer .btequ 0,trcoer ; TRCIOA output disable bit +eb_trcoer .btequ 1,trcoer ; TRCIOB output disable bit +ec_trcoer .btequ 2,trcoer ; TRCIOC output disable bit +ed_trcoer .btequ 3,trcoer ; TRCIOD output disable bit +pto_trcoer .btequ 7,trcoer ; Timer output disable bit +; +;------------------------------------------------------- +; Timer RC A/D Conversion Trigger Control Register +;------------------------------------------------------- +trcadcr .equ 00FBh +; +adtrgae_trcadcr .btequ 0,trcadcr ; TRCGRA A/D conversion start trigger enable bit +adtrgbe_trcadcr .btequ 1,trcadcr ; TRCGRB A/D conversion start trigger enable bit +adtrgce_trcadcr .btequ 2,trcadcr ; TRCGRC A/D conversion start trigger enable bit +adtrgde_trcadcr .btequ 3,trcadcr ; TRCGRD A/D conversion start trigger enable bit +; +;------------------------------------------------------- +; Timer RC Waveform Output Manipulation Register +;------------------------------------------------------- +trcopr .equ 00FCh +; +opsel0_trcopr .btequ 0,trcopr ; Waveform output manipulation event select bit +opsel1_trcopr .btequ 1,trcopr ; Waveform output manipulation event select bit +opol0_trcopr .btequ 2,trcopr ; Waveform output manipulation period output level select bit +opol1_trcopr .btequ 3,trcopr ; Waveform output manipulation period output level select bit +restats_trcopr .btequ 4,trcopr ; Restart method select bit +ope_trcopr .btequ 5,trcopr ; Waveform output manipulation enable bit +; +;------------------------------------------------------- +; Comparator B Control Register +;------------------------------------------------------- +wcmpr .equ 0180h +; +wcb1m0 .btequ 0,wcmpr ; Comparator B1 operation enable bit +wcb1out .btequ 3,wcmpr ; Comparator B1 monitor flag +wcb3m0 .btequ 4,wcmpr ; Comparator B3 operation enable bit +wcb3out .btequ 7,wcmpr ; Comparator B3 monitor flag +; +;------------------------------------------------------- +; Comparator B1 Interrupt Control Register +;------------------------------------------------------- +wcb1intr .equ 0181h +; +wcb1f0 .btequ 0,wcb1intr ; Comparator B1 filter select bit +wcb1f1 .btequ 1,wcb1intr ; Comparator B1 filter select bit +wcb1s0 .btequ 4,wcb1intr ; Comparator B1 interrupt edge select bit +wcb1s1 .btequ 5,wcb1intr ; Comparator B1 interrupt edge select bit +wcb1inten .btequ 6,wcb1intr ; Comparator B1 interrupt enable signal bit +wcb1f .btequ 7,wcb1intr ; Comparator B1 interrupt request flag +; +;------------------------------------------------------- +; Comparator B3 Interrupt Control Register +;------------------------------------------------------- +wcb3intr .equ 0182h +; +wcb3f0 .btequ 0,wcb3intr ; Comparator B3 filter select bit +wcb3f1 .btequ 1,wcb3intr ; Comparator B3 filter select bit +wcb3s0 .btequ 4,wcb3intr ; Comparator B3 interrupt edge select bit +wcb3s1 .btequ 5,wcb3intr ; Comparator B3 interrupt edge select bit +wcb3inten .btequ 6,wcb3intr ; Comparator B3 interrupt enable signal bit +wcb3f .btequ 7,wcb3intr ; Comparator B3 interrupt request flag +; +;------------------------------------------------------- +; Flash Memory Status Register +;------------------------------------------------------- +fst .equ 01A9h +; +rdysti .btequ 0,fst ; Flash ready status interrupt request flag +bsyaei .btequ 1,fst ; Flash access error interrupt request flag +fst2 .btequ 2,fst ; LBDATA monitor flag +fst3 .btequ 3,fst ; Program-suspend status flag +fst4 .btequ 4,fst ; Program error status flag +fst5 .btequ 5,fst ; Erase error/blank check error status flag +fst6 .btequ 6,fst ; Erase-suspend status flag +fst7 .btequ 7,fst ; Ready/busy status flag +; +;------------------------------------------------------- +; Flash Memory Control Register 0 +;------------------------------------------------------- +fmr0 .equ 01AAh +; +fmr01 .btequ 1,fmr0 ; CPU rewrite mode select bit +fmr02 .btequ 2,fmr0 ; EW1 mode select bit +fmstp .btequ 3,fmr0 ; Flash memory stop bit +cmdrst .btequ 4,fmr0 ; Erase/write sequence reset bit +cmderie .btequ 5,fmr0 ; Erase/write error, blank check error, command error interrupt enable bit +bsyaeie .btequ 6,fmr0 ; Flash access error interrupt enable bit +rdystie .btequ 7,fmr0 ; Flash ready status interrupt enable bit +; +;------------------------------------------------------- +; Flash Memory Control Register 1 +;------------------------------------------------------- +fmr1 .equ 01ABh +; +wtfmstp .btequ 2,fmr1 ; Flash memory stop bit in wait mode +fmr13 .btequ 3,fmr1 ; Lock bit disable select bit +fmr16 .btequ 6,fmr1 ; Data flash block A rewrite disable bit +fmr17 .btequ 7,fmr1 ; Data flash block B rewrite disable bit +; +;------------------------------------------------------- +; Flash Memory Control Register 2 +;------------------------------------------------------- +fmr2 .equ 01ACh +; +fmr20 .btequ 0,fmr2 ; Suspend enable bit +fmr21 .btequ 1,fmr2 ; Suspend request bit +fmr22 .btequ 2,fmr2 ; Interrupt request suspend request enable bit +fmr27 .btequ 7,fmr2 ; Low-current-consumption read mode enable bit +; +;------------------------------------------------------- +; Flash Memory Refresh Control Register +;------------------------------------------------------- +frefr .equ 01ADh +; +ref0 .btequ 0,frefr ; Periodic refresh interval control bit +ref1 .btequ 1,frefr ; Periodic refresh interval control bit +ref2 .btequ 2,frefr ; Periodic refresh interval control bit +ref3 .btequ 3,frefr ; Periodic refresh interval control bit +ref4 .btequ 4,frefr ; Periodic refresh interval control bit +ref5 .btequ 5,frefr ; Periodic refresh interval control bit +; +;------------------------------------------------------- +; Address Match Interrupt Register 0 +;------------------------------------------------------- +aiadr0 .equ 01C0h +; +aiadr0l .equ aiadr0 ; Low +aiadr0m .equ aiadr0+1 ; Middle +aiadr0h .equ aiadr0+2 ; High +; +;------------------------------------------------------- +; Address Match Interrupt Enable Register 0 +;------------------------------------------------------- +aien0 .equ 01C3h +; +aien00 .btequ 0,aien0 ; Address match interrupt enable 0 bit +; +;------------------------------------------------------- +; Address Match Interrupt Register 1 +;------------------------------------------------------- +aiadr1 .equ 01C4h +; +aiadr1l .equ aiadr1 ; Low +aiadr1m .equ aiadr1+1 ; Middle +aiadr1h .equ aiadr1+2 ; High +; +;------------------------------------------------------- +; Address Match Interrupt Enable Register 1 +;------------------------------------------------------- +aien1 .equ 01C7h +; +aien10 .btequ 0,aien1 ; Address match interrupt enable 1 bit +; diff --git a/src.original/DefaultSession.hsf b/src.original/DefaultSession.hsf new file mode 100644 index 0000000..85a1a56 --- /dev/null +++ b/src.original/DefaultSession.hsf @@ -0,0 +1,106 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.3" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"{0CE21862-D122-40C7-8480-3B1EC1503AF0}ZipcCtrlViews" "0" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" "" +"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointFlag" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointStatus" "-1 " +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBrowseDirectory" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlSplitterPosition" "242" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "1" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlWindowProperties" "17" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineWndInstanceKey0" "{WK_00000001_CmdLine}" +"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileDir" "" +"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileName" "" +"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" +[LANGUAGE] +"Japanese" +[CONFIG_INFO_VD1] +1 +[CONFIG_INFO_VD2] +0 +[CONFIG_INFO_VD3] +0 +[CONFIG_INFO_VD4] +0 +[WINDOW_POSITION_STATE_DATA_VD1] +"{WK_00000001_CmdLine}" "WINDOW" 59422 0 1 "0.17" 180 60 0 350 200 17 0 "32771|32772|32778|<>|32773|32774|<>|32820|<>|32801|32824" "0.0" +"{WK_00000001_MAPSCT}X1keybordDefaultSession" "WINDOW" 59422 0 0 "1.00" 557 283 103 795 557 2053 0 "32812|<>|32813|32814|<>|32816|<>|32822|32821|<>|32796|32797|<>|32833|<>|32825|32829|<>|32852" "29.5" +"{WK_00000001_MAPSYM}X1keybordDefaultSession" "WINDOW" 59422 0 0 "1.00" 516 327 127 802 516 2053 0 "32833|<>|32826|32828|<>|32852" "50.0" +"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 180 518 256 350 200 18 0 "36756|36757|36758|36759|<>|36746|36747|<>|39531|<>|39500|39534|<>|36687" "0.0" +"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 180 518 256 350 200 18 0 "" "0.0" +"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 2 0 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 2 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 1 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000010_TOOLS}" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 1 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000026_MACRO}" "TOOLBAR 0" 59419 1 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000028_RTOSDEBUG}" "TOOLBAR 0" 59419 2 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[WINDOW_Z_ORDER] +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\main.c" +[TARGET_NAME] +"" "" 1632504443 +[STATUSBAR_STATEINFO_VD1] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD2] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD3] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_STATEINFO_VD4] +"MasterShowState" 1 +"ApplicationShowState" 1 +"DebuggerShowState" 1 +[STATUSBAR_DEBUGGER_PANESTATE_VD1] +[STATUSBAR_DEBUGGER_PANESTATE_VD2] +[STATUSBAR_DEBUGGER_PANESTATE_VD3] +[STATUSBAR_DEBUGGER_PANESTATE_VD4] +[DEBUGGER_OPTIONS] +"" +[DOWNLOAD_MODULES] +[CONNECT_ON_GO] +"FALSE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[REMOVE_BREAKPOINTS_ON_DOWNLOAD] +"FALSE" +[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION] +"FALSE" +[LIMIT_DISASSEMBLY_MEMORY_ACCESS] +"FALSE" +[DISABLE_MEMORY_ACCESS_DURING_EXECUTION] +"FALSE" +[DEBUGGER_OPTIONS_PROPERTIES] +"1" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"" +[FLASH_DETAILS] +"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/src.original/Readme.txt b/src.original/Readme.txt new file mode 100644 index 0000000..c974f7c --- /dev/null +++ b/src.original/Readme.txt @@ -0,0 +1,19 @@ +-------- PROJECT GENERATOR -------- +PROJECT NAME : X1keybord +PROJECT DIRECTORY : C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord +CPU SERIES : R8C/Tiny +CPU GROUP : M12A +TOOLCHAIN NAME : Renesas M16C Standard Toolchain +TOOLCHAIN VERSION : 6.00.00 +GENERATION FILES : + C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\X1keybord.c + main program file. + C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\nc_define.inc + interrupt program. +START UP FILES : + C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\ncrt0.a30 + C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\sfr_r8m12a.h + C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\sfr_r8m12a.inc + C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\sect30.inc + +DATE & TIME : 2014/07/16 3:13:49 diff --git a/src.original/X1keybord.Hbp b/src.original/X1keybord.Hbp new file mode 100644 index 0000000..2414749 --- /dev/null +++ b/src.original/X1keybord.Hbp @@ -0,0 +1,2 @@ +[Setting] +ToolChain=0 diff --git a/src.original/X1keybord.hwp b/src.original/X1keybord.hwp new file mode 100644 index 0000000..b619fe8 --- /dev/null +++ b/src.original/X1keybord.hwp @@ -0,0 +1,232 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.8" +[PROJECT_DETAILS] +"X1keybord" "C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord" "C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\X1keybord.hwp" "M16C" "Renesas M16C Standard" "Application" "R8C/Tiny" "R8C/M12A" +[INFORMATION] +"vWFNg񂪂܂" +[TOOL_CHAIN] +"Renesas M16C Standard Toolchain" "6.00.00" +[CONFIGURATIONS] +"Debug" "C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\Debug" +"Release" "C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\Release" +[BUILD_PHASES] +"Renesas M16C Assembler" 1 +"Renesas M16C C/C++ Compiler" 1 +"Renesas M16C C/C++ Library Generator" 1 +"Renesas M16C Configurator" 1 +"Renesas M16C ConfiguratorR8C" 1 +"Renesas OptLinker" 1 +[TOOL_ENVIRONMENT] +[EXTENSIONS] +"Absolute file" "ABS" +"Absolute list file" "ALS" +"Assembler error tag file" "ATG" +"Assembly include file" "INC" +"Assembly source file" "A30" +"Binary file" "BIN" +"Branch Information file" "JIN" +"C header file" "H" +"C source file" "C" +"C++ header file" "HPP" +"C++ source file" "CC" +"C++ source file" "CP" +"C++ source file" "CPP" +"Calling information file" "CAL" +"Configuration file" "CFG" +"Cross reference file" "XRF" +"Hex file" "HEX" +"ID file" "ID" +"IEEE695 Absolute file" "X30" +"Inspector Information file" "UTL" +"Library file" "LIB" +"Library information file" "LBP" +"Library list file" "LLS" +"Linkage error tag file" "LTG" +"Linkage map file" "MAP" +"List file" "LST" +"MISRA report file" "CSV" +"MISRA rule file" "RDE" +"Object file" "OBJ" +"Preprocessed C source file" "I" +"Profile file" "PRO" +"Relocatable file" "R30" +"Relocatable file" "REL" +"S-Record file" "MOT" +"Stack information file" "SNI" +"Systemcall file" "MRC" +[FILE_GROUPS] +"Absolute file" "BIN" "NONE" "" +"Absolute list file" "TEXT" "EDITOR" "" +"Assembler error tag file" "TEXT" "EDITOR" "" +"Assembly include file" "TEXT" "EDITOR" "" +"Assembly source file" "TEXT" "EDITOR" "" +"Binary file" "BIN" "NONE" "" +"Branch Information file" "TEXT" "EDITOR" "" +"C header file" "TEXT" "EDITOR" "" +"C source file" "TEXT" "EDITOR" "" +"C++ header file" "TEXT" "EDITOR" "" +"C++ source file" "TEXT" "EDITOR" "" +"Calling information file" "BIN" "NONE" "" +"Configuration file" "TEXT" "EDITOR" "" +"Cross reference file" "TEXT" "EDITOR" "" +"Hex file" "TEXT" "EDITOR" "" +"ID file" "TEXT" "EDITOR" "" +"IEEE695 Absolute file" "BIN" "NONE" "" +"Inspector Information file" "BIN" "NONE" "" +"Library file" "BIN" "NONE" "" +"Library information file" "TEXT" "EDITOR" "" +"Library list file" "TEXT" "EDITOR" "" +"Linkage error tag file" "TEXT" "EDITOR" "" +"Linkage map file" "TEXT" "EDITOR" "" +"List file" "TEXT" "EDITOR" "" +"MISRA report file" "TEXT" "EDITOR" "" +"MISRA rule file" "TEXT" "EDITOR" "" +"Object file" "BIN" "NONE" "" +"Preprocessed C source file" "TEXT" "EDITOR" "" +"Profile file" "BIN" "NONE" "" +"Relocatable file" "BIN" "NONE" "" +"S-Record file" "TEXT" "EDITOR" "" +"Stack information file" "BIN" "NONE" "" +"Systemcall file" "TEXT" "EDITOR" "" +[ASSOCIATED_APPLICATIONS] +[TOOLCHAIN_PHASE] +"Renesas M16C Assembler" +"Renesas M16C C/C++ Compiler" +"Renesas M16C C/C++ Library Generator" +"Renesas M16C Configurator" +"Renesas M16C ConfiguratorR8C" +"Renesas OptLinker" +[UTILITY_PHASE] +[CUSTOM_PHASES] +[CUSTOM_PHASE_INPUT_GROUP] +[CUSTOM_PHASE_OUTPUT_SYNTAX] +[BUILD_ORDER] +"Renesas M16C C/C++ Library Generator" 1 +"Renesas M16C C/C++ Compiler" 1 +"Renesas M16C Assembler" 1 +"Renesas OptLinker" 1 +"Renesas M16C ConfiguratorR8C" 0 +"Renesas M16C Configurator" 0 +[BUILD_PHASE_DETAILS] +"Renesas M16C Assembler" "Assembly source file" 1 +"Renesas M16C C/C++ Compiler" "C source file|C++ source file" 1 +"Renesas M16C C/C++ Library Generator" "" 0 +"Renesas M16C Configurator" "Configuration file" 0 +"Renesas M16C ConfiguratorR8C" "Configuration file" 0 +"Renesas OptLinker" "Object file|Library file|Relocatable file" 0 +[BUILD_FILE_ORDER_Assembly source file] +"Renesas M16C Assembler" 1 +[BUILD_FILE_ORDER_C source file] +"Renesas M16C C/C++ Compiler" 1 +[BUILD_FILE_ORDER_C++ source file] +"Renesas M16C C/C++ Compiler" 1 +[SCRAP] +"Project Generator Setup File" "" +[MAPPINGS] +"Assembly source file" "Renesas M16C Assembler" "Renesas M16C C/C++ Compiler" +"Library file" "Renesas OptLinker" "Renesas M16C C/C++ Library Generator" +"Object file" "Renesas OptLinker" "Renesas M16C Assembler" +"Object file" "Renesas OptLinker" "Renesas M16C C/C++ Compiler" +[PROJECT_FILES] +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\iodefine.h" "User" "C header file" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\keyconv.c" "User" "C source file" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\keyconv.h" "User" "C header file" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\keytable.h" "User" "C header file" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\main.c" "User" "C source file" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\ncrt0.a30" "User" "Assembly source file" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\ps2.c" "User" "C source file" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\ps2.h" "User" "C header file" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\timer.c" "User" "C source file" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\timer.h" "User" "C header file" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\x1key.c" "User" "C source file" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\x1key.h" "User" "C header file" 2 +[FOLDER] +"Assembly source file" "Assembly source file" +"C header file" "C header file" +"C source file" "C source file" +[GENERAL_DATA_PROJECT] +"USE_CUSTOM_LINKAGE_ORDER" "1" +[ON_DEMAND_COMPONENTS_LOADED] +[SYNC_SESSION_NAMES] +[SESSIONS] +"DefaultSession" "C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\DefaultSession.hsf" 0 +[GENERAL_DATA_SESSION_DefaultSession] +[OPTIONS_Debug_Renesas M16C Assembler] +"Assembly source file" "0c08a6ad3a0afc10" 4 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\ncrt0.a30" "0c08a6ad3a0afc10" 4 +[OPTIONS_Debug_Renesas M16C C/C++ Compiler] +"C source file" "0c08a6ad3a0afc10" 2 +"C++ source file" "0d255f408a0afc10" 3 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\keyconv.c" "0005bc57566afc10" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\main.c" "0f26a3f24a0afc10" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\ps2.c" "0697e34f775afc10" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\timer.c" "05a40b30775afc10" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\x1key.c" "02c4a5fd475afc10" 2 +[OPTIONS_Debug_Renesas M16C C/C++ Library Generator] +"Single Shot" "0c08a6ad3a0afc10" 1 +[OPTIONS_Debug_Renesas M16C Configurator] +"Single Shot" "0005bc57566afc10" 6 +[OPTIONS_Debug_Renesas M16C ConfiguratorR8C] +"Single Shot" "0005bc57566afc10" 6 +[OPTIONS_Debug_Renesas OptLinker] +"Single Shot" "0fa00d57566afc10" 5 +[OPTIONS_Debug] +"" 0 +"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] " 6 +"[V|VERSION|1] [S|DEFINE|__UART0__] [S|LANG|CPP] [S|OUTPUT|OBJECTCODE] [B|INSPECTOR|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [S|MISRA|ALL] [B|SILENT|1] [S|CPU|R8C] +" 3 +"[V|VERSION|1] [S|LIST|LM] [B|INSPECTOR|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DISABLES_MESSAGE|1] [S|CPU|R8C] " 4 +"[V|VERSION|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [S|CPU|R8C] [B|NOFLOAT|1] [S|MODE|BUILD/CHANGED]" 1 +"[V|VERSION|1] [S|OUTPUT|OBJECTCODE] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|INSPECTOR|1] [B|SILENT|1] [S|CPU|R8C] [S|DEFINE|__UART0__] " 2 +"[V|VERSION|6] [B|OPTIMIZE|0] [B|DEBUG|1] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|OTHER|^"-change_message=information=1100,1322,1410^"] [S|FORM|STYPE] [B|TOTAL_SIZE|1] [B|STACK|1] [S|START|data_SE,bss_SE,data_SO,bss_SO,data_NE,bss_NE,data_NO,bss_NO,stack,istack,heap_NE(400)|interrupt,rom_NE,rom_NO,data_SEI,data_SOI,data_NEI,data_NOI,switch_table,C$VTBL,program(e000)|vector(fed8)]" 5 +[EXCLUDED_FILES_Debug] +[LINKAGE_ORDER_Debug] +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\Debug\ncrt0.r30" +[GENERAL_DATA_CONFIGURATION_Debug] +[OPTIONS_Release_Renesas M16C Assembler] +"Assembly source file" "07cdf9d0e95afc10" 4 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\ncrt0.a30" "07cdf9d0e95afc10" 4 +[OPTIONS_Release_Renesas M16C C/C++ Compiler] +"C source file" "0f9e27549d9afc10" 2 +"C++ source file" "0f9e27549d9afc10" 3 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\keyconv.c" "0f9e27549d9afc10" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\main.c" "0f9e27549d9afc10" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\ps2.c" "0f9e27549d9afc10" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\timer.c" "0f9e27549d9afc10" 2 +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\x1key.c" "0f9e27549d9afc10" 2 +[OPTIONS_Release_Renesas M16C C/C++ Library Generator] +"Single Shot" "07cdf9d0e95afc10" 1 +[OPTIONS_Release_Renesas M16C Configurator] +"Single Shot" "0005bc57566afc10" 6 +[OPTIONS_Release_Renesas M16C ConfiguratorR8C] +"Single Shot" "0005bc57566afc10" 6 +[OPTIONS_Release_Renesas OptLinker] +"Single Shot" "00024c3dd5aafc10" 5 +[OPTIONS_Release] +"" 0 +"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] " 6 +"[V|VERSION|1] [B|INSPECTOR|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [S|LIST|L|M] [B|DISABLES_MESSAGE|1] [S|CPU|R8C] +" 4 +"[V|VERSION|1] [S|DEFINE|__UART0__] [S|LANG|CPP] [S|OUTPUT|OBJECTCODE] [B|INSPECTOR|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [S|OPTIMIZE|5] [B|OR|1] [S|MISRA|ALL] [B|SILENT|1] [S|CPU|R8C] +" 3 +"[V|VERSION|1] [S|DEFINE|__UART0__] [S|LANG|C] [S|OUTPUT|OBJECTCODE] [B|INSPECTOR|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [S|OPTIMIZE|5] [B|OR|1] [S|MISRA|ALL] [B|SILENT|1] [S|CPU|R8C] +" 2 +"[V|VERSION|1] [S|MODE|BUILD/CHANGED] [S|EXISTOUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|NOFLOAT|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [S|OPTIMIZE|3] [S|OPTIMIZERS|OR] [S|CPU|R8C] +" 1 +"[V|VERSION|6] [S|FORM|STYPE] [S|BYTE_COUNT_VALUE|FF] [B|DEBUG|0] [S|CRC|NONE|00000000] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|SHOW|METHODCUSTOM|] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [I|SPACE|^"FF^"] [S|OPTIMIZEITEMS|ALL] [S|START|data_SE,bss_SE,data_SO,bss_SO,data_NE,bss_NE,data_NO,bss_NO,stack,istack,heap_NE(0400)|program_dataflash,flash_data_NE,flash_data_NO(03000)|interrupt,rom_NE,rom_NO,data_SEI,data_SOI,data_NEI,data_NOI,switch_table,C$VTBL,program(0F800)|vector(0FED8)] [B|STACK|1] [B|TOTAL_SIZE|1] [S|OTHER|^"-change_message=information=1100,1322,1410^"] +" 5 +[EXCLUDED_FILES_Release] +[LINKAGE_ORDER_Release] +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\Release\ncrt0.r30" +[GENERAL_DATA_CONFIGURATION_Release] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +[SESSION_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +"MEMORY_MAPPING_OPTIONS" "" +[GENERAL_DATA_CONFIGURATION_SESSION_Release_DefaultSession] +[SESSION_DATA_CONFIGURATION_SESSION_Release_DefaultSession] +"MEMORY_MAPPING_OPTIONS" "" +[EXT_DEBUGGER_INFO] +0 "" "" "" "" +[END] diff --git a/src.original/X1keybord.hws b/src.original/X1keybord.hws new file mode 100644 index 0000000..bd7c981 --- /dev/null +++ b/src.original/X1keybord.hws @@ -0,0 +1,40 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"11.0" +[WORKSPACE_DETAILS] +"X1keybord" "C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord" "C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord.hws" "M16C" "Renesas M16C Standard" +[SHARED_WORKSPACE_CONTROL_STATUS] +"" "" "" +"" "" "" +[PROJECTS] +"X1keybord" "C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord" "C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\X1keybord.hwp" 0 +[INFORMATION] +"[NXy[X񂪂܂" +[SCRAP] +[PROJECT_DEPENDENCY] +[WORKSPACE_PROPERTIES] +[HELP_FILES] +[GENERAL_DATA_PROJECT] +[USERMENUTOOLS] +[CUSTOMPLACEHOLDERS] +[MAKEFILE_BUILD_INFO] +"$(WORKSPDIR)\make\$(PROJECTNAME)_$(CONFIGNAME).mak" "" "$(WORKSPDIR)\make" 0 0 0 +[VD_CONFIGURATION_OPTIONS] +"ACTIVE_DESKTOP" "0" +[VD_CONFIGURATIONS] +"0" "Default1" "1" +"1" "Default2" "1" +"2" "Default3" "1" +"3" "Default4" "1" +[OPTIONS_DEBUG_TAB] +0 0 0 0 0 +[VCS] +"" "" "" 0 +[VCS_PROJECT] +[MAKEFILE_ENV_STRINGS] +[MAKEFILE_ENV_FLAGS] +1 0 0 +[MAKEFILE_CLEAN_INFO] +"" +[END] diff --git a/src.original/X1keybord.nav b/src.original/X1keybord.nav new file mode 100644 index 0000000..97cf07e Binary files /dev/null and b/src.original/X1keybord.nav differ diff --git a/src.original/X1keybord.tps b/src.original/X1keybord.tps new file mode 100644 index 0000000..a66c798 --- /dev/null +++ b/src.original/X1keybord.tps @@ -0,0 +1,26 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.1" +[SESSIONS_] +"DefaultSession" +[CONFIGURATIONS] +"Debug" +"Release" +[CURRENT_CONFIGURATION] +"Release" +[CURRENT_SESSION] +"DefaultSession" +[GENERAL_DATA_PROJECT] +[GENERAL_DATA_CONFIGURATION_Debug] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Debug] +"DefaultSession" +[GENERAL_DATA_CONFIGURATION_Release] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_Release] +"DefaultSession" +[GENERAL_DATA_SESSION_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Release_DefaultSession] +[END] diff --git a/src.original/X1keybord.tws b/src.original/X1keybord.tws new file mode 100644 index 0000000..c5c4d2c --- /dev/null +++ b/src.original/X1keybord.tws @@ -0,0 +1,15 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.2" +[CURRENT_PROJECT] +"X1keybord" +[GENERAL_DATA] +[BREAKPOINTS] +[OPEN_WORKSPACE_FILES] +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\main.c" +[WORKSPACE_FILE_STATES] +"C:\Users\uts\SkyDrive\Documents\HEW\R8C_X1keybord\X1keybord\main.c" -8 -31 903 466 1 0 +[LOADED_PROJECTS] +"X1keybord" +[END] diff --git a/src.original/iodefine.h b/src.original/iodefine.h new file mode 100644 index 0000000..c2d144c --- /dev/null +++ b/src.original/iodefine.h @@ -0,0 +1,23 @@ +/* + PS/2 L[{[h SHARP X1 ɂ‚Ȃ + I/O s̒`ق + + 2014N722 쐬 + + http://kyoutan.jpn.org/ + + ۏ؂łB + ꂪ쐬͗prɐ݂܂BpE񏤗pɂ炸RɎgpĒč\܂B + ɕAAzzA肵ĂǂƂƂłB + AsvłB +*/ + +#define PS2DATA p3_3 +#define X1KEYOUT p3_7 + +#define TRUE 1 +#define FALSE 0 +#define NULL 0 + +#define DI() asm("FCLR I") // 荞݋֎~ +#define EI() asm("FSET I") // 荞݋ diff --git a/src.original/keyconv.c b/src.original/keyconv.c new file mode 100644 index 0000000..86a3d6c --- /dev/null +++ b/src.original/keyconv.c @@ -0,0 +1,234 @@ +/* + PS/2 L[{[h SHARP X1 ɂ‚Ȃ + L[R[hϊ + + 2014N723쐬 + + http://kyoutan.jpn.org/ + + ۏ؂łB + ꂪ쐬͗prɐ݂܂BpE񏤗pɂ炸RɎgpĒč\܂B + ɕAAzzA肵ĂǂƂƂłB + AsvłB +*/ + +#include "keyconv.h" +#include "keytable.h" +#include "ps2.h" +#include "x1key.h" + +volatile unsigned short x1shift=0xFF; // X1 Vtgԕۑ 0ŗL +#define TENKEY ((unsigned char)(1<<7)) +#define PRESS ((unsigned char)(1<<6)) +#define REPEAT ((unsigned char)(1<<5)) +#define GRAPH ((unsigned char)(1<<4)) +#define CAPS ((unsigned char)(1<<3)) +#define KANA ((unsigned char)(1<<2)) +#define SHIFT ((unsigned char)(1<<1)) +#define CTRL ((unsigned char)(1<<0)) + + +volatile unsigned char ps2ex=0; // PS2L[{[h gL[tO +#define EXKEY ((unsigned char)(1<<0)) +#define RELEASE ((unsigned char)(1<<1)) +#define PAUSE_BREAK ((unsigned char)(1<<2)) + + +unsigned char codeconv(unsigned char data); +unsigned char checkbreak(void); +unsigned char x1code(unsigned char data); +void x1trans(unsigned char data); + + +void keyconv(void) +{ + unsigned char data; + + data=ps2get(); // PS/2L[{[hM܂ő҂āA1oCgǂݍ + switch(data) + { + case 0xE0: // gL[ + ps2ex|=EXKEY; // gL[tOZbg + break; + + case 0xF0: // + ps2ex|=RELEASE; // tOZbg + break; + + default: + // PS/2 ̃R[hR[hɕϊ + if(0xE1==data) data=checkbreak(); // PAUSE/BREAK L[̔ + + if(0==(ps2ex & EXKEY)) + { // ʏL[ + if(0x8Fdata))||(0x5A ret)) ret-=0x20; // At@xbg啶 + return ret; + } + if((KANA | GRAPH | CTRL )==status) // CAPS+SHIFT + { + unsigned char ret; + ret=CHR_TBL1[data]; + if((0x40 < ret)&&(0x5b > ret)) ret+=0x20; // At@xbg + return ret; + } + + status&=(GRAPH | KANA | SHIFT | CTRL); + + if((GRAPH | KANA | CTRL )==status) return CHR_TBL1[data]; // SHIFT + if((GRAPH | KANA | SHIFT)==status) return CHR_TBL3[data]; // CTRL + if((KANA | SHIFT | CTRL )==status) return CHR_TBL2[data]; // GRAPH + if(( SHIFT | CTRL )==status) return CHR_TBL2[data]; // GRAPH+KANA + if((GRAPH | SHIFT | CTRL )==status) return CHR_TBL4[data]; // KANA + if((GRAPH | CTRL )==status) return CHR_TBL5[data]; // KANA+SHIFT + + return CHR_TBL0[data]; // VtgȂ +} \ No newline at end of file diff --git a/src.original/keyconv.h b/src.original/keyconv.h new file mode 100644 index 0000000..7066cce --- /dev/null +++ b/src.original/keyconv.h @@ -0,0 +1,15 @@ +/* + PS/2 L[{[h SHARP X1 ɂ‚Ȃ + L[R[hϊ + + 2014N723쐬 + + http://kyoutan.jpn.org/ + + ۏ؂łB + ꂪ쐬͗prɐ݂܂BpE񏤗pɂ炸RɎgpĒč\܂B + ɕAAzzA肵ĂǂƂƂłB + AsvłB +*/ + +void keyconv(void); \ No newline at end of file diff --git a/src.original/keytable.h b/src.original/keytable.h new file mode 100644 index 0000000..29a7505 --- /dev/null +++ b/src.original/keytable.h @@ -0,0 +1,287 @@ +/* + PS/2 - SHARP X1 L[R[hϊe[u + + X1 L[{[h̎ĂȂ̂ŁAX1̃L[R[h + X1 G~[^ Xmillennium v0.26 T-tune STEP 1.43 (http://www.x1center.org/emu.html) + Ɋ܂܂ Input.cpp ̃e[ugp܂B + + + 2014N723쐬 + + http://kyoutan.jpn.org/ + + ۏ؂łB + ꂪ쐬͗prɐ݂܂BpE񏤗pɂ炸RɎgpĒč\܂B + ɕAAzzA肵ĂǂƂƂłB + AsvłB +*/ + + +typedef const unsigned char BYTE; + +#pragma section rom flash_data // ϊe[u̓f[^tbVɔzu +/* ~~~ ~~~~~~~~~~ + | +-- DɕtZNV̖OB + | ̖O_NE _NO ̔zutāA + | rh-J̃ZNV̐ݒŊJnAhXw肷 + | isect30.inc t@CҏWKv͖j + +--------- ZNViprogramAromAdataAbss ̂ꂩj + + +zuAZNVɂ‚ẮA +l16bV[Y,R8C t@~ C/C++RpC[U[Y}jA 2 RpC̊{IȎg +2.2.3 zũJX^}CY a. ZNV̍\ ɏڂĂB + +i}jÁuHigh-performancd Embedded Workshop (HEW)vƈꏏɃCXg[ +uManual NavigatorvŌ邱Ƃłj +*/ + + + +// PS/2 106 L[{[hR[hւ̕ϊe[u +// PS/2 ̃R[hX1̃R[hɒڕϊƁAX1̃e[u傫ȂĂ܂̂ +// R[hɕϊ +BYTE KEY106[0x100] = +{ +// 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F +// 0x00 F9 F5 F3 F1 F2 F12 F10 F8 F6 F4 TAB Sp + 0x00,0x43,0x00,0x3F,0x3D,0x3B,0x3C,0x58,0x00,0x44,0x42,0x40,0x3E,0x0F,0x29,0x00, +// 0x10 ALT SH L Ђ CTRL Q 1 Z S A W 2 WIN + 0x00,0x38,0x2A,0x55,0x1D,0x10,0x02,0x00,0x00,0x00,0x2C,0x1F,0x1E,0x11,0x03,0x00, +// 0x20 C X D E 4 3 WIN SP V F T R 5 APL + 0x00,0x2E,0x2D,0x20,0x12,0x05,0x04,0x00,0x00,0x39,0x2F,0x21,0x14,0x13,0x06,0x00, +// 0x30 N B H G Y 6 M J U 7 8 + 0x00,0x31,0x30,0x23,0x22,0x15,0x07,0x00,0x00,0x00,0x32,0x24,0x16,0x08,0x09,0x00, +// 0x40 , K I O 0 9 . / L ; P - + 0x00,0x33,0x25,0x17,0x18,0x0B,0x0A,0x00,0x00,0x34,0x35,0x26,0x27,0x19,0x0C,0x00, +// 0x50 : @ ^ CAPS SH R ENT [ ] + 0x00,0x59,0x28,0x00,0x1A,0x0d,0x00,0x00,0x3A,0x36,0x1C,0x1B,0x00,0x2B,0x00,0x00, +// 0x60 ϊ BS 1 \ 4 7 + 0x00,0x00,0x00,0x00,0x5E,0x00,0x0E,0x56,0x00,0x4F,0x5A,0x4B,0x47,0x00,0x00,0x00, +// 0x70 0 . 2 5 6 8 ESC NUM F11 + 3 - * 9 ScLk + 0x52,0x53,0x50,0x4C,0x4D,0x48,0x01,0x00,0x57,0x4E,0x51,0x4A,0x37,0x49,0x00,0x00, +// 0x80 BRK F7 + 0x45,0x00,0x00,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + +// gL[ +// 0x60 END HOME + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x5F,0x00,0xCB,0xC7,0x00,0x00,0x00, +// 0x70 INS DEL PgDn PgUp + 0xD2,0xD3,0xD0,0x00,0xCD,0xC8,0x00,0x00,0x00,0x00,0x5C,0x00,0x00,0x5B,0x00,0x00, + + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +// PAUSE/BREAK E1 14 77 E1 F0 14 F0 77 0x80 +// PRINT SCREEN E0 12 E0 7C [SH L]+[*(TEN KEY)] +}; +/* ^[R[h \ + 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F + 0x00 ESC 1 2 3 4 5 6 7 8 9 0 - ^ BS TAB + 0x10 Q W E R T Y U I O P @ [ ENT CTRL A S + 0x20 D F G H J K L ; : S SH L ] Z X C V + 0x30 B N M , . / SH R * ALT SP CAPS F1 F2 F3 F4 F5 + 0x40 F6 F7 F8 F9 F10 BRK 7 8 9 - 4 5 6 + 1 + 0x50 2 3 0 . F11 F12 \ PgUp PgDn = ϊ END + 0x60 + 0x70 + 0x80 + 0x90 + 0xA0 + 0xB0 + 0xC0 HOME + 0xD0 INS DEL +*/ + +#define GRAPH_CODE1 0x56 // +#define GRAPH_CODE2 0x38 // ALT +#define CAPS_CODE 0x3A // CAPS +#define KANA_CODE 0x55 // J^Ji^Ђ炪 +#define SHIFTL_CODE 0x2A // SHIFT +#define SHIFTR_CODE 0x36 // ESHIFT +#define CTRL_CODE 0x1D // CTRL +#define UP_CODE 0xC8 // +#define DOWN_CODE 0xD0 // +#define LEFT_CODE 0xCB // +#define RIGHT_CODE 0xCD // +#define INS_CODE 0xD2 // INS +#define DEL_CODE 0xD3 // DEL +#define HOME_CODE 0xC7 // HOME + +BYTE BREAK_CODE[8]={0xE1,0x14,0x77,0xE1,0xF0,0x14,0xF0,0x77}; // BREAK L[̃R[h + + +// R[h X1 ̃L[R[h (ASCII) ւ̕ϊe[u +// Xmillennium v0.26 T-tune STEP 1.43 Input.cpp Rs[܂ + +// BASE +BYTE CHR_TBL0[]={ +/* -- , ESC, P, Q, R, S, T, U, 0x00 */ + 0x00,0x1b, '1', '2', '3', '4', '5', '6', +/* V, W, X, O, |, O, BS, TAB, 0x08 */ + '7', '8', '9', '0', '-', '^',0x08,0x09, +/* p, v, d, q, s, x, t, h, 0x10 */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', +/* n, o, , m, Ent,Ctrl, `, r, 0x18 */ + 'o', 'p', '@', '[',0x0d,0x00, 'a', 's', +/* c, e, f, g, i, j, k, G, 0x20 */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', +/* F, S,SftL, n, y, w, b, u, 0x28 */ + ':',0x00,0x00, ']', 'z', 'x', 'c', 'v', +/* a, m, l, C, D, ^,SftR, [*], 0x30 */ + 'b', 'n', 'm', ',', '.', '/',0x00,0x2a, +/* Alt, SPC, Cap, f.1, f.2, f.3, f.4, f.5, 0x38 */ + 0x00, ' ',0x00, 'q', 'r', 's', 't', 'u', +/* f.6, f.7, f.8, f.9,f.10,Paus,ScrL, [7], 0x40 */ + 0xec,0xeb,0xe2,0xe1,0x00,0x13,0x00, '7', +/* [8], [9], [-], [4], [5], [6], [+], [1], 0x48 */ + '8', '9', '-', '4', '5', '6', '+', '1', +/* [2], [3], [0], [.], ???, ???, ???,f.11, 0x50 */ + '2', '3', '0', '.',0x00,0x00,0x00,0x00, +/*f.12, _ , \ ,RLUP,RLDN,<>,XFER, END, 0x58 */ + 0x00,0x00,'\\',0x0e,0x0f, '=',0xfe,0x11, +}; + +// SHIFT +BYTE CHR_TBL1[]={ +/* -- , ESC, P, Q, R, S, T, U, 0x00 */ + 0x00,0x1b, '!',0x22, '#', '$',0x25, '&', +/* V, W, X, O, |, O, BS, TAB, 0x08 */ + 0x27, '(', ')', '0', '=',0x60,0x12,0x09, +/* p, v, d, q, s, x, t, h, 0x10 */ + 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', +/* n, o, , m, Ent,Ctrl, `, r, 0x18 */ + 'O', 'P',0x7e, '{',0x0d,0x00, 'A', 'S', +/* c, e, f, g, i, j, k, G, 0x20 */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', '+', +/* F, S,SftL, n, y, w, b, u, 0x28 */ + 0x2a,0x00,0x00, '}', 'Z', 'X', 'C', 'V', +/* a, m, l, C, D, ^,SftR, [*], 0x30 */ + 'B', 'N', 'M', '<', '>',0x3f,0x00,0x2a, +/* Alt, SPC, Cap, f.1, f.2, f.3, f.4, f.5, 0x38 */ + 0x00, ' ',0x00, 'v', 'w', 'x', 'y', 'z', +/* f.6, f.7, f.8, f.9,f.10,Paus, ???, [7], 0x40 */ + 0x00,0x00,0x00,0x00,0x00,0x03,0x00, '7', +/* [8], [9], [-], [4], [5], [6], [+], [1], 0x48 */ + '8', '9', '-', '4', '5', '6', '+', '1', +/* [2], [3], [0], [.], ???, ???, ???,f.11, 0x50 */ + '2', '3', '0', '.',0x00,0x00,0x00,0x00, +/*f.12, _ , \ ,RLUP,RLDN,<>,XFER, END, 0x58 */ + 0x00, '_', '|',0x0e,0x0f, '=',0xfe,0x11, +}; + +// GRPH (Alt) +BYTE CHR_TBL2[]={ +/* -- , ESC, P, Q, R, S, T, U, 0x00 */ + 0x00,0x00,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6, +/* V, W, X, O, |, O, BS, TAB, 0x08 */ + 0xf7,0xf8,0xf9,0xfa,0x8c,0x8b,0x00,0x00, +/* p, v, d, q, s, x, t, h, 0x10 */ + 0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, +/* n, o, , m, Ent,Ctrl, `, r, 0x18 */ + 0xf0,0x8d,0x8a,0xfc,0x00,0x00,0x7f,0xe9, +/* c, e, f, g, i, j, k, G, 0x20 */ + 0xea,0xeb,0xec,0xed,0xee,0xef,0x8e,0x89, +/* F, S,SftL, n, y, w, b, u, 0x28 */ + 0xfd,0x00,0x00,0xe8,0x80,0x81,0x82,0x83, +/* a, m, l, C, D, ^,SftR, [*], 0x30 */ + 0x84,0x85,0x86,0x87,0x88,0xfe,0x00,0x9b, +/* Alt, SPC, Cap, f.1, f.2, f.3, f.4, f.5, 0x38 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/* f.6, f.7, f.8, f.9,f.10,Paus, ???, [7], 0x40 */ + 0x00,0x00,0x00,0x00,0x00,0x13,0x00,0x9a, +/* [8], [9], [-], [4], [5], [6], [+], [1], 0x48 */ + 0x93,0x97,0x9c,0x95,0x96,0x94,0x9d,0x99, +/* [2], [3], [0], [.], ???, ???, ???,f.11, 0x50 */ + 0x92,0x98,0x8f,0x91,0x00,0x00,0x00,0x00, +/*f.12, _ , \ ,RLUP,RLDN,<>,XFER, END, 0x58 */ + 0x00,0xff,0xfb,0x0e,0x0f,0x90,0xfe,0x11, +}; + +// CTRL +BYTE CHR_TBL3[]={ +/* -- , ESC, P, Q, R, S, T, U, 0x00 */ + 0x00,0x1b, '1', '2', '3', '4', '5', '6', +/* V, W, X, O, |, O, BS, TAB, 0x08 */ + '7', '8', '9', '0',0x00,0x1e,0x08,0x09, +/* p, v, d, q, s, x, t, h, 0x10 */ + 0x11,0x17,0x05,0x12,0x14,0x19,0x15,0x09, +/* n, o, , m, Ent,Ctrl, `, r, 0x18 */ + 0x0f,0x10, '@',0x1b,0x0d,0x00,0x01,0x13, +/* c, e, f, g, i, j, k, G, 0x20 */ + 0x04,0x06,0x07,0x08,0x0a,0x0b,0x0c, ';', +/* F, S,SftL, n, y, w, b, u, 0x28 */ + ':',0x00,0x1c,0x1d,0x1a,0x18,0x03,0x16, +/* a, m, l, C, D, ^,SftR, [*], 0x30 */ + 0x02,0x0e,0x0d,0x00,0x00,0x00,0x00,0x2a, +/* Alt, SPC, Cap, f.1, f.2, f.3, f.4, f.5, 0x38 */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/* f.6, f.7, f.8, f.9,f.10,Paus, ???, [7], 0x40 */ + 0xec,0xeb,0xe2,0xe1,0x00,0x03,0x00, '7', +/* [8], [9], [-], [4], [5], [6], [+], [1], 0x48 */ + '8', '9', '-', '4', '5', '6', '+', '1', +/* [2], [3], [0], [.], ???, ???, ???,f.11, 0x50 */ + '2', '3', '0', '.',0x00,0x00,0x00,0x00, +/*f.12, _ , \ ,RLUP,RLDN,<>,XFER, END, 0x58 */ + 0x00,0x00,0x1c,0x0e,0x0f, '=',0xfe,0x11, +}; + +// +BYTE CHR_TBL4[]={ +/* -- , ESC, P, Q, R, S, T, U, 0x00 */ + 0x00,0x1b, '', '', '', '', '', '', +/* V, W, X, O, |, O, BS, TAB, 0x08 */ + '', '', '', '', '', '',0x08,0x09, +/* p, v, d, q, s, x, t, h, 0x10 */ + '', '', '', '', '', '', '', '', +/* n, o, , m, Ent,Ctrl, `, r, 0x18 */ + '', '', '', '',0x0d,0x00, '', '', +/* c, e, f, g, i, j, k, G, 0x20 */ + '', '', '', '', '', '', '', '', +/* F, S,SftL, n, y, w, b, u, 0x28 */ + '',0x00,0x00, '', '', '', '', '', +/* a, m, l, C, D, ^,SftR, [*], 0x30 */ + '', '', '', '', '', '',0x00,0x2a, +/* Alt, SPC, Cap, f.1, f.2, f.3, f.4, f.5, 0x38 */ + 0x00,0x20,0x00, 'q', 'r', 's', 't', 'u', +/* f.6, f.7, f.8, f.9,f.10,Paus, ???, [7], 0x40 */ + 0xec,0xeb,0xe2,0xe1,0x00,0x13,0x00, '7', +/* [8], [9], [-], [4], [5], [6], [+], [1], 0x48 */ + '8', '9', '-', '4', '5', '6', '+', '1', +/* [2], [3], [0], [.], ???, ???, ???,f.11, 0x50 */ + '2', '3', '0', '.',0x00,0x00,0x00,0x00, +/*f.12, _ , \ ,RLUP,RLDN,<>,XFER, END, 0x58 */ + 0x00, '', '',0x0e,0x0f, '=',0xfe,0x11, +}; + +// + +BYTE CHR_TBL5[]={ +/* -- , ESC, P, Q, R, S, T, U, 0x00 */ + 0x00,0x1b, '', '', '', '', '', '', +/* V, W, X, O, |, O, BS, TAB, 0x08 */ + '', '', '', '', '', '',0x12,0x09, +/* p, v, d, q, s, x, t, h, 0x10 */ + '', '', '', '', '', '', '', '', +/* n, o, , m, Ent,Ctrl, `, r, 0x18 */ + '', '', '', '',0x0d,0x00, '', '', +/* c, e, f, g, i, j, k, G, 0x20 */ + '', '', '', '', '', '', '', '', +/* F, S,SftL, n, y, w, b, u, 0x28 */ + '',0x00,0x00, '', '', '', '', '', +/* a, m, l, C, D, ^,SftR, [*], 0x30 */ + '', '', '', '', '', '',0x00,0x2a, +/* Alt, SPC, Cap, f.1, f.2, f.3, f.4, f.5, 0x38 */ + 0x00, ' ',0x00, 'v', 'w', 'x', 'y', 'z', +/* f.6, f.7, f.8, f.9,f.10,Paus, ???, [7], 0x40 */ + 0x00,0x00,0x00,0x00,0x00,0x03,0x00, '7', +/* [8], [9], [-], [4], [5], [6], [+], [1], 0x48 */ + '8', '9', '-', '4', '5', '6', '+', '1', +/* [2], [3], [0], [.], ???, ???, ???,f.11, 0x50 */ + '2', '3', '0', '.',0x00,0x00,0x00,0x00, +/*f.12, _ , \ ,RLUP,RLDN,<>,XFER, END, 0x58 */ + 0x00, '', '',0x0e,0x0f, '=',0xfe,0x11, +}; + +#pragma section rom rom // 萔ZNV̔zuʏromɖ߂ \ No newline at end of file diff --git a/src.original/main.c b/src.original/main.c new file mode 100644 index 0000000..de2c446 --- /dev/null +++ b/src.original/main.c @@ -0,0 +1,165 @@ +/* + PS/2 L[{[h SHARP X1 ɂ‚Ȃ + + Renesas R8C/M12A p + W vOROM:2KB f[^tbV:2KB RAM:256B Ɏ܂܂B + + 2014N716 쐬 + + + http://kyoutan.jpn.org/ + + ۏ؂łB + X1̃L[{[hLĂȂ̂ŁA삪̂悭킩܂B + eXg X1 turbo III ōs܂AT˂ɓĂ悤łB + + ꂪ쐬͗prɐ݂܂BpE񏤗pɂ炸RɎgpĒč\܂B + ɕAAzzA肵ĂǂƂƂłB + AsvłB +*/ + +#include "sfr_r8m12a.h" +#include "iodefine.h" +#include "x1key.h" +#include "ps2.h" +#include "timer.h" +#include "keyconv.h" + +void main(void); +void osc_init(void); +void io_init(void); + +void main(void) +{ + DI(); // 荞݋֎~ + osc_init(); + io_init(); + timer_start(); + EI(); // 荞݋ + +/* + // PS/2 [heXg + while(TRUE) + { + puth2(ps2get()); + //puth2(PS2RPOS); + //puth2(PS2WPOS); + } +*/ + +/* + // X1 oeXg + { + unsigned short a=0; + unsigned char b=0x20; + + while(TRUE) + { + if(10 < (TIMER-a)) // 1b + { + a=TIMER; + + X1_send(((unsigned short)0b10111111 << 8) + b);// + X1_send(((unsigned short)0b11111111 << 8) + 0x00);// + + if(0x7F==b) + { + b=0x20; + } + else + { + b++; + } + } + } + } +*/ + + while(TRUE) + { + keyconv(); + } +} + +void osc_init(void) +{ + // IV[^[ɐ؂ւ + prc0=1; // NbNWX^ANZX + ococr=0b00000001; // I`bvIV[^[U ᑬU + { + unsigned char a; + for(a=0; a<255; a++) asm("nop"); // ŃIV[^[̔U肷̂҂ĂƂ̂œKɎԑ҂ + } + sckcr=0b01000000; // XIN/IV[^[IōI CPUNbN + ckstpr=0b10000000; // VXeNbNᑬ/IōI + phisel=0x00; // VXeNbN + frv1=fr18s0; // I`bvIV[^[18.432MHzɒ + frv2=fr18s1; + prc0=0; // NbNWX^ANZX֎~ +} + +void io_init(void) +{ + // I/O |[g + // P1_0 + // P1_1 + // P1_2 + // P1_3 + // P1_4 TXD ݁EʐMp + // P1_5 RXD ʐMp (TRJIO) + // P1_6 RXD ݗp (TRJO) + // P1_7 + + // P3_3 PS/2 DATA + // P3_4 + // P3_5 + // P3_7 TRJO X1KEYOUT + + // P4_2 + // P4_5 INT0 PS/2 CLK + // P4_6 (TRJIO X1KEYOUT TRJO̔]o gȂ) + // P4_7 + + // PA_0 + + X1KEYOUT=1; + p1_4=1; // TXD + + // |[ǧ 1:o + pd1=0b10011111; // P1_5 P1_6 RXD + pd3=0b11110111; // P3_7 TRJO X1KEYOUT o | P3_3 PS/2 DATA + pd4=0b11011111; // P4_5 INT0 PS/2 CLK + + // vAbv 1: + pur1=0b01100000; + pur3=0b00001000; + pur4=0b00100000; + + // I[vhCo 1: + pod1=0b00000000; + pod3=0b00001000; + pod4=0b00100000; + + x1key_init(); + ps2key_init(); + timer_init(); + + // 荞ݗD惌x + ilvlb=0x01; // TIMER RJ 1 + ilvlc=0x01; // TIMER RB 1 + ilvle=0x20; // INT0 2 TIMER RJ Dx + // 荞݉ 20TCNƌ\B + + asm("LDIPL #0"); // vZbT荞ݗD惌x0i̒lx̊荞݂󂯕tj + + // |[g}bsO + pml1 =0b00000000; + pmh1 =0b00000101; // P1_4:TXD P1_5:RXD + pmh1e=0b00000000; + pml3 =0b00000000; + pmh3 =0b10000000; // P3_7 TRJO X1KEYOUT + pml4 =0b00000000; + pmh4 =0b00000100; // P4_5 INT0 PS/2 CLK + pmh4e=0b00010000; + pamcr=0b00010001; // PA̓Zbg +} diff --git a/src.original/nc_define.inc b/src.original/nc_define.inc new file mode 100644 index 0000000..ec059e2 --- /dev/null +++ b/src.original/nc_define.inc @@ -0,0 +1,15 @@ +;------------------------------------------------------------------------ +; | +; FILE :nc_define.inc | +; DATE :Wed, Jul 16, 2014 | +; DESCRIPTION :interrupt program. | +; CPU GROUP :M12A | +; | +; This file is generated by Renesas Project Generator (Ver.4.19). | +; NOTE:THIS IS A TYPICAL EXAMPLE. | +;------------------------------------------------------------------------ +; Macro Symbol definition +__STANDARD_IO__ .equ 0 ; STANDARD I/O flag definition +__HEAPSIZE__ .equ 0H ; HEEP SIZE definition +__STACKSIZE__ .equ 080H ; STACK SIZE definition +__ISTACKSIZE__ .equ 080H ; INTERRUPT STACK SIZE definition diff --git a/src.original/ncrt0.a30 b/src.original/ncrt0.a30 new file mode 100644 index 0000000..7ec0276 --- /dev/null +++ b/src.original/ncrt0.a30 @@ -0,0 +1,139 @@ +;---------------------------------------------------------------------- +; | +; | +; | +; DESCRIPTION : Startup Program. (for Assembler language) | +; | +; | +; This file is generated by Renesas Project Generator. | +; | +;---------------------------------------------------------------------- +;/********************************************************************* +;* +;* Device : R8C Family +;* +;* File Name : ncrt0.a30 +;* +;* Abstract : Startup Program +;* +;* History : 1.01 (2006-11-22) +;* +;* NOTE : THIS IS A TYPICAL EXAMPLE. +;* +;* Copyright (C) 2006 Renesas Electronics Corporation. +;* and Renesas Solutions Corp. +;* +;*********************************************************************/ +;--------------------------------------------------------------------- +; include files +;--------------------------------------------------------------------- + .list OFF + .include nc_define.inc + .include sect30.inc + .list ON + +;===================================================================== +; Interrupt section start +;--------------------------------------------------------------------- + .glb start + .section interrupt,CODE,ALIGN + .insf start,G,0 +start: +;--------------------------------------------------------------------- +; after reset,this program will start +;--------------------------------------------------------------------- + ldc #((topof istack)+(sizeof istack)),isp ;set istack pointer + mov.b #02h,0ah + mov.b #00h,04h ;set processer mode + mov.b #00h,0ah +.if __STACKSIZE__ != 0 + ldc #0080h,flg + ldc #((topof stack)+(sizeof stack)),sp ;set stack pointer +.else + ldc #0000h,flg +.endif + ldc #__SB__,sb ;set sb register + + ; If the destination is INTBL or INTBH, + ; make sure that bytes are transferred in succession. + ldc #((topof vector)>>16)&0FFFFh,INTBH + ldc #(topof vector)&0FFFFh,INTBL + +;===================================================================== +; NEAR area initialize. +;--------------------------------------------------------------------- +; bss zero clear +;--------------------------------------------------------------------- + N_BZERO (topof bss_SE),bss_SE + N_BZERO (topof bss_SO),bss_SO + N_BZERO (topof bss_NE),bss_NE + N_BZERO (topof bss_NO),bss_NO + +;--------------------------------------------------------------------- +; initialize data section +;--------------------------------------------------------------------- + N_BCOPY (topof data_SEI),(topof data_SE),data_SE + N_BCOPY (topof data_SOI),(topof data_SO),data_SO + N_BCOPY (topof data_NEI),(topof data_NE),data_NE + N_BCOPY (topof data_NOI),(topof data_NO),data_NO + +;===================================================================== +; heap area initialize +;--------------------------------------------------------------------- +.if __HEAPSIZE__ != 0 + .glb __mnext + .glb __msize + mov.w #((topof heap_NE)&0FFFFH),__mnext + mov.w #(__HEAPSIZE__&0FFFFH),__msize +.endif + +;===================================================================== +; Initialize standard I/O +;--------------------------------------------------------------------- +.if __STANDARD_IO__ == 1 + .glb __init + .call __init,G + jsr.a __init +.endif + +;===================================================================== +; Call main() function +;--------------------------------------------------------------------- + ldc #0h,fb ; for debuger + +; Remove the comment when you use global class object +; Sections C$INIT will be generated +; .glb __CALL_INIT +; .call __CALL_INIT,G +; jsr.a __CALL_INIT + + .glb _main + .call _main,G + jsr.a _main + +;===================================================================== +; exit() function +;--------------------------------------------------------------------- + .glb _exit + .glb $exit + .glb __exit_loop +_exit: +$exit: + +; Remove the comment when you use global class object +; Sections C$INIT will be generated +; .glb __CALL_END +; .call __CALL_END,G +; jsr.a __CALL_END + +__exit_loop: ; End program + jmp __exit_loop + .einsf +;===================================================================== +; dummy interrupt function +;--------------------------------------------------------------------- + .glb dummy_int +dummy_int: + reit + + .end diff --git a/src.original/ps2.c b/src.original/ps2.c new file mode 100644 index 0000000..a9cadf6 --- /dev/null +++ b/src.original/ps2.c @@ -0,0 +1,176 @@ +/* + PS/2 L[{[h SHARP X1 ɂ‚Ȃ + PS/2 L[{[h̎M + + NbN̗1rbg“ǂނȂ̂ŁAȒPłB + X^[grbg 1 + f[^rbg 8 + peBrbg 1 + Xgbvrbg 1 + + v11rbg peB + ĂL[R[h http://kyoutan.jpn.org/uts/pc/pic/x68key/ ɏ܂B + + + + 2014N722 쐬 + + http://kyoutan.jpn.org/ + + ۏ؂łB + ꂪ쐬͗prɐ݂܂BpE񏤗pɂ炸RɎgpĒč\܂B + ɕAAzzA肵ĂǂƂƂłB + AsvłB +*/ + +#include "sfr_r8m12a.h" +#include "ps2.h" +#include "iodefine.h" + +volatile unsigned short PS2TIMER=0; // PS2M^CAEg^C}[ +volatile unsigned char PS2BUFF[PS2BUFFSIZE]; // PS2Mobt@ +volatile unsigned char PS2RPOS=0; // PS2ǂݏoʒu +volatile unsigned char PS2WPOS=0; // PS2݈ʒu + +void ps2key_init(void) +{ + /* INT0 Oݏ */ + //INT0 PS/2 CLOCK + intf0=0b00000001; // INT0 f1tB^gp 1*3/18.432=0.16us + iscr0=0b00000000; // INT0 GbW + inten=0b00000001; // INT0 ͋ + { + unsigned char a; + for(a=(6*8); a!=0; a--) asm("nop"); // Ǝԑ҂ + } + // PMLi PMHi ISCR0 INTEN KIEN WX^Ɗ荞ݗvtO 1ɂȂ邱Ƃ + // ƃ}jAɏĂ̂ŃtONA + while(1==iri0) iri0=0; +} + +// O INT0 +// PS/2 CLOCK ̗Ŋ荞݂āA1rbgƒf[^荞 +#pragma INTERRUPT INT_int0 (vect=29) +void INT_int0(void) +{ + static unsigned short bit=1; + static unsigned short data=0; + static unsigned char parity=0; + + // M쒆Ŏ~܂ĂԃNAčŏM + if((bit != 1) && (PS2TIMEOUT < PS2TIMER)) + { + bit=1; + data=0; + parity=0; + } + + // ʃrbg1rbgŽM + if(0!=PS2DATA) + { + // 1 + data+=bit; + parity++; + } + + if(0b100_0000_0000==bit) // 11bit ǂ iX^[grbg1 f[^rbg8 peB1 Xgbv1j + { + parity--; // Xgbvrbg + if(0!=(parity & 1)) // peB`FbN 1Ȃ琳 + { + // M + if((PS2BUFFSIZE-1) > ps2size())//obt@ɋ󂫂邩H + { + PS2BUFF[PS2WPOS]=((data >> 1) & 0xFF); + + if((PS2BUFFSIZE-1) > PS2WPOS) + { + PS2WPOS++; + } + else + { + PS2WPOS=0; + } + } + else + { + // obt@t + } + } + else + { + // peBG[ + } + + bit=1; + data=0; + parity=0; + } + else + { + if((1==bit)&&(data!=0)) + { //X^[grbg[Ȃ ԃZbg + bit=1; + data=0; + parity=0; + } + else + { // ̃rbgǂޏ + bit=(bit<<1); + PS2TIMER=0; // ^CAEg^C}[NA + } + } + + while(1==iri0) iri0=0; // IɊ荞݃tONÂŁA̍sĂ +} + +// obt@̗Lf[^Ԃ +unsigned char ps2size(void) +{ + signed int size; + + size=(signed int)PS2WPOS-PS2RPOS; + if(0>size) + { + size=PS2BUFFSIZE+size; + } + + return size; + // size=5 wpos=2 rpos=3 4 +} + +// Mobt@NA +void ps2clear(void) +{ + PS2WPOS=0; + PS2RPOS=0; + PS2BUFF[PS2RPOS]=0; +} + +// obt@1byteǂ +unsigned char ps2read(void) +{ + unsigned char data=0; + + if(PS2WPOS!=PS2RPOS) // obt@Ƀf[^͂邩ȁH + { + data=PS2BUFF[PS2RPOS]; + + if((PS2BUFFSIZE-1) > PS2RPOS) + { + PS2RPOS++; + } + else + { + PS2RPOS=0; + } + } + return data; +} + +// M܂ő҂1byteǂ +unsigned char ps2get(void) +{ + while(0==ps2size()); //obt@Ƀf[^܂ő҂ + return ps2read(); +} diff --git a/src.original/ps2.h b/src.original/ps2.h new file mode 100644 index 0000000..e96bb77 --- /dev/null +++ b/src.original/ps2.h @@ -0,0 +1,27 @@ +/* + PS/2 L[{[h SHARP X1 ɂ‚Ȃ + PS/2 L[{[h̎M + + 2014N722 쐬 + + http://kyoutan.jpn.org/ + + ۏ؂łB + ꂪ쐬͗prɐ݂܂BpE񏤗pɂ炸RɎgpĒč\܂B + ɕAAzzA肵ĂǂƂƂłB + AsvłB +*/ + +#define PS2TIMEOUT 30 // PS2 ^CAEg 30*100[ms] = 3[s] +#define PS2BUFFSIZE 0x10 + +extern volatile unsigned short PS2TIMER; // PS2M^CAEg^C}[ +//extern volatile unsigned char PS2BUFF[PS2BUFFSIZE]; // PS2Mobt@ +//extern volatile unsigned char PS2RPOS; // PS2ǂݏoʒu +//extern volatile unsigned char PS2WPOS; // PS2݈ʒu + +void ps2key_init(void); +unsigned char ps2size(void); +void ps2clear(void); +unsigned char ps2read(void); +unsigned char ps2get(void); diff --git a/src.original/ps2.txt b/src.original/ps2.txt new file mode 100644 index 0000000..a9cadf6 --- /dev/null +++ b/src.original/ps2.txt @@ -0,0 +1,176 @@ +/* + PS/2 L[{[h SHARP X1 ɂ‚Ȃ + PS/2 L[{[h̎M + + NbN̗1rbg“ǂނȂ̂ŁAȒPłB + X^[grbg 1 + f[^rbg 8 + peBrbg 1 + Xgbvrbg 1 + + v11rbg peB + ĂL[R[h http://kyoutan.jpn.org/uts/pc/pic/x68key/ ɏ܂B + + + + 2014N722 쐬 + + http://kyoutan.jpn.org/ + + ۏ؂łB + ꂪ쐬͗prɐ݂܂BpE񏤗pɂ炸RɎgpĒč\܂B + ɕAAzzA肵ĂǂƂƂłB + AsvłB +*/ + +#include "sfr_r8m12a.h" +#include "ps2.h" +#include "iodefine.h" + +volatile unsigned short PS2TIMER=0; // PS2M^CAEg^C}[ +volatile unsigned char PS2BUFF[PS2BUFFSIZE]; // PS2Mobt@ +volatile unsigned char PS2RPOS=0; // PS2ǂݏoʒu +volatile unsigned char PS2WPOS=0; // PS2݈ʒu + +void ps2key_init(void) +{ + /* INT0 Oݏ */ + //INT0 PS/2 CLOCK + intf0=0b00000001; // INT0 f1tB^gp 1*3/18.432=0.16us + iscr0=0b00000000; // INT0 GbW + inten=0b00000001; // INT0 ͋ + { + unsigned char a; + for(a=(6*8); a!=0; a--) asm("nop"); // Ǝԑ҂ + } + // PMLi PMHi ISCR0 INTEN KIEN WX^Ɗ荞ݗvtO 1ɂȂ邱Ƃ + // ƃ}jAɏĂ̂ŃtONA + while(1==iri0) iri0=0; +} + +// O INT0 +// PS/2 CLOCK ̗Ŋ荞݂āA1rbgƒf[^荞 +#pragma INTERRUPT INT_int0 (vect=29) +void INT_int0(void) +{ + static unsigned short bit=1; + static unsigned short data=0; + static unsigned char parity=0; + + // M쒆Ŏ~܂ĂԃNAčŏM + if((bit != 1) && (PS2TIMEOUT < PS2TIMER)) + { + bit=1; + data=0; + parity=0; + } + + // ʃrbg1rbgŽM + if(0!=PS2DATA) + { + // 1 + data+=bit; + parity++; + } + + if(0b100_0000_0000==bit) // 11bit ǂ iX^[grbg1 f[^rbg8 peB1 Xgbv1j + { + parity--; // Xgbvrbg + if(0!=(parity & 1)) // peB`FbN 1Ȃ琳 + { + // M + if((PS2BUFFSIZE-1) > ps2size())//obt@ɋ󂫂邩H + { + PS2BUFF[PS2WPOS]=((data >> 1) & 0xFF); + + if((PS2BUFFSIZE-1) > PS2WPOS) + { + PS2WPOS++; + } + else + { + PS2WPOS=0; + } + } + else + { + // obt@t + } + } + else + { + // peBG[ + } + + bit=1; + data=0; + parity=0; + } + else + { + if((1==bit)&&(data!=0)) + { //X^[grbg[Ȃ ԃZbg + bit=1; + data=0; + parity=0; + } + else + { // ̃rbgǂޏ + bit=(bit<<1); + PS2TIMER=0; // ^CAEg^C}[NA + } + } + + while(1==iri0) iri0=0; // IɊ荞݃tONÂŁA̍sĂ +} + +// obt@̗Lf[^Ԃ +unsigned char ps2size(void) +{ + signed int size; + + size=(signed int)PS2WPOS-PS2RPOS; + if(0>size) + { + size=PS2BUFFSIZE+size; + } + + return size; + // size=5 wpos=2 rpos=3 4 +} + +// Mobt@NA +void ps2clear(void) +{ + PS2WPOS=0; + PS2RPOS=0; + PS2BUFF[PS2RPOS]=0; +} + +// obt@1byteǂ +unsigned char ps2read(void) +{ + unsigned char data=0; + + if(PS2WPOS!=PS2RPOS) // obt@Ƀf[^͂邩ȁH + { + data=PS2BUFF[PS2RPOS]; + + if((PS2BUFFSIZE-1) > PS2RPOS) + { + PS2RPOS++; + } + else + { + PS2RPOS=0; + } + } + return data; +} + +// M܂ő҂1byteǂ +unsigned char ps2get(void) +{ + while(0==ps2size()); //obt@Ƀf[^܂ő҂ + return ps2read(); +} diff --git a/src.original/sect30.inc b/src.original/sect30.inc new file mode 100644 index 0000000..c951df5 --- /dev/null +++ b/src.original/sect30.inc @@ -0,0 +1,157 @@ +;---------------------------------------------------------------------- +; | +; | +; | +; DESCRIPTION : Section definition. (for Assembler language) | +; | +; | +; This file is generated by Renesas Project Generator. | +; | +;---------------------------------------------------------------------- +;/********************************************************************* +;* +;* Device : R8C/Mx +;* +;* File Name : sect30.inc +;* +;* Abstract : Section definition +;* +;* History : 1.00 (2011-02-01) +;* +;* NOTE : THIS IS A TYPICAL EXAMPLE. +;* +;* Copyright (C) 2011 Renesas Electronics Corporation. and +;* Renesas Solutions Corp. All rights reserved. +;* +;*********************************************************************/ + +;===================================================================== +; +; Definition of section +; +;--------------------------------------------------------------------- +; Near RAM data area +;--------------------------------------------------------------------- +; SBDATA area + .section data_SE,DATA,ALIGN + .section bss_SE,DATA,ALIGN + .section data_SO,DATA + .section bss_SO,DATA + +; SBDATA area definition +; Sets the top address (__SB__) of the SBDATA area +; (it is accessing area to used the SBrelative addressing mode). + .glb __SB__ +__SB__ .equ 400H + +; near RAM area + .section data_NE,DATA,ALIGN + .section bss_NE,DATA,ALIGN + .section data_NO,DATA + .section bss_NO,DATA + +;--------------------------------------------------------------------- +; Stack area +;--------------------------------------------------------------------- +.if __STACKSIZE__ != 0 + .section stack,DATA,ALIGN + .blkb __STACKSIZE__ +.endif + + .section istack,DATA,ALIGN + .blkb __ISTACKSIZE__ + +;--------------------------------------------------------------------- +; heap section +;--------------------------------------------------------------------- +.if __HEAPSIZE__ != 0 + .section heap_NE,DATA,ALIGN + .blkb __HEAPSIZE__ +.endif + +;--------------------------------------------------------------------- +; Initial data of 'data' section +;--------------------------------------------------------------------- + .section data_SEI,ROMDATA + .section data_SOI,ROMDATA + .section data_NEI,ROMDATA + .section data_NOI,ROMDATA + +;--------------------------------------------------------------------- +; variable vector section +;--------------------------------------------------------------------- + .section vector,ROMDATA,ALIGN + +; When you use "#pragma interrupt" with "vect=", +; you need not define interrupt vector. +; +; When you use "#pragma interrupt" without "vect=", +; you must define all interrupt vectors like the following example. +; You define dummy_int for interrupt vector not used. +; +; .lword dummy_int ; vector 0 +; .lword dummy_int ; vector 1 +; .lword dummy_int ; vector 2 +; : +; .lword dummy_int ; vector 63 + +;--------------------------------------------------------------------- +; fixed vector section +;--------------------------------------------------------------------- + .section fvector,ROMDATA + .org 0ffd8H +; reserved + .addr 0FFFFFFH +; OFS2 + .byte 0FFH +UDI: + .lword dummy_int +OVER_FLOW: + .lword dummy_int +BRKI: + .lword dummy_int +ADDRESS_MATCH: + .lword dummy_int +SINGLE_STEP: + .lword dummy_int +WDT: + .lword dummy_int +; reserved + .lword dummy_int +; reserved + .lword dummy_int +RESET: + .lword start + +;===================================================================== +; ID code & Option function select register +;--------------------------------------------------------------------- +; ID code check function + .id "#FFFFFFFFFFFFFF" + +; option function select register + .ofsreg 0FFH + +;--------------------------------------------------------------------- +; far ROM data area +;--------------------------------------------------------------------- +; .section data_FEI,ROMDATA +; .section data_FOI,ROMDATA + +;===================================================================== +; Initialize Macro declaration +;--------------------------------------------------------------------- +N_BZERO .macro TOP_ ,SECT_ + mov.b #00H, R0L + mov.w #(TOP_ & 0FFFFH), A1 + mov.w #sizeof SECT_ , R3 + sstr.b + .endm + +N_BCOPY .macro FROM_,TO_,SECT_ + mov.w #(FROM_ & 0FFFFH),A0 + mov.b #(FROM_ >>16),R1H + mov.w #TO_ ,A1 + mov.w #sizeof SECT_ , R3 + smovf.b + .endm diff --git a/src.original/sfr_r8m12a.h b/src.original/sfr_r8m12a.h new file mode 100644 index 0000000..5a6d492 --- /dev/null +++ b/src.original/sfr_r8m12a.h @@ -0,0 +1,1772 @@ +/***********************************************************************/ +/* */ +/* */ +/* */ +/* DESCRIPTION :define the sfr register. (for C language) */ +/* */ +/* */ +/* This file is generated by Renesas Project Generator. */ +/* */ +/***********************************************************************/ +/************************************************************************ +* +* Device : R8C/M12A +* +* File Name : sfr_r8m12a.h +* +* Abstract : definition of R8C/M12A Group SFR +* +* History : 2.00 ( 2010-12-03 ) [User's Manual: Hardware Rev.1.00] +* : 1.10 ( 2010-06-18 ) [User's Manual: Hardware Rev.0.10] +* : 1.00 ( 2010-02-26 ) [User's Manual: Hardware Rev.0.01] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2010 Renesas Electronics Corporation. +* and Renesas Solutions Corp. +* +*************************************************************************/ + +/******************************************************** +* declare SFR addresses * +********************************************************/ + +#pragma ADDRESS pm0_addr 0010H /* Processor Mode Register 0 */ + +#pragma ADDRESS mstcr_addr 0012H /* Module Standby Control Register */ + +#pragma ADDRESS prcr_addr 0013H /* Protect Register */ + +#pragma ADDRESS hrpr_addr 0016H /* Hardware Reset Protect Register */ + +#pragma ADDRESS exckcr_addr 0020H /* External Clock Control Register */ + +#pragma ADDRESS ococr_addr 0021H /* High-Speed/Low-Speed On-Chip Oscillator Control Register */ + +#pragma ADDRESS sckcr_addr 0022H /* System Clock f Control Register */ + +#pragma ADDRESS phisel_addr 0023H /* System Clock f Select Register */ + +#pragma ADDRESS ckstpr_addr 0024H /* Clock Stop Control Register */ + +#pragma ADDRESS ckrscr_addr 0025H /* Clock Control Register When Returning from Modes */ + +#pragma ADDRESS bakcr_addr 0026H /* Oscillation Stop Detection Register */ + +#pragma ADDRESS risr_addr 0030H /* Watchdog Timer Function Register */ + +#pragma ADDRESS wdtr_addr 0031H /* Watchdog Timer Reset Register */ + +#pragma ADDRESS wdts_addr 0032H /* Watchdog Timer Start Register */ + +#pragma ADDRESS wdtc_addr 0033H /* Watchdog Timer Control Register */ + +#pragma ADDRESS cspr_addr 0034H /* Count Source Protection Mode Register */ + +#pragma ADDRESS wdtir_addr 0035H /* Periodic Timer Interrupt Control Register */ + +#pragma ADDRESS inten_addr 0038H /* External Input Enable Register */ + +#pragma ADDRESS intf0_addr 003AH /* INT Input Filter Select Register 0 */ + +#pragma ADDRESS iscr0_addr 003CH /* INT Input Edge Select Register 0 */ + +#pragma ADDRESS kien_addr 003EH /* Key Input Enable Register */ + +#pragma ADDRESS ilvl0_addr 0040H /* Interrupt Priority Level Register 0 */ + +#pragma ADDRESS ilvl2_addr 0042H /* Interrupt Priority Level Register 2 */ + +#pragma ADDRESS ilvl3_addr 0043H /* Interrupt Priority Level Register 3 */ + +#pragma ADDRESS ilvl4_addr 0044H /* Interrupt Priority Level Register 4 */ + +#pragma ADDRESS ilvl5_addr 0045H /* Interrupt Priority Level Register 5 */ + +#pragma ADDRESS ilvl6_addr 0046H /* Interrupt Priority Level Register 6 */ + +#pragma ADDRESS ilvl7_addr 0047H /* Interrupt Priority Level Register 7 */ + +#pragma ADDRESS ilvl8_addr 0048H /* Interrupt Priority Level Register 8 */ + +#pragma ADDRESS ilvl9_addr 0049H /* Interrupt Priority Level Register 9 */ + +#pragma ADDRESS ilvla_addr 004AH /* Interrupt Priority Level Register A */ + +#pragma ADDRESS ilvlb_addr 004BH /* Interrupt Priority Level Register B */ + +#pragma ADDRESS ilvlc_addr 004CH /* Interrupt Priority Level Register C */ + +#pragma ADDRESS ilvld_addr 004DH /* Interrupt Priority Level Register D */ + +#pragma ADDRESS ilvle_addr 004EH /* Interrupt Priority Level Register E */ + +#pragma ADDRESS irr0_addr 0050H /* Interrupt Monitor Flag Register 0 */ + +#pragma ADDRESS irr1_addr 0051H /* Interrupt Monitor Flag Register 1 */ + +#pragma ADDRESS irr2_addr 0052H /* Interrupt Monitor Flag Register 2 */ + +#pragma ADDRESS irr3_addr 0053H /* External Interrupt Flag Register */ + +#pragma ADDRESS vcac_addr 0058H /* Voltage Monitor Circuit Edge Select Register */ + +#pragma ADDRESS vca2_addr 005AH /* Voltage Detect Register 2 */ + +#pragma ADDRESS vd1ls_addr 005BH /* Voltage Detection 1 Level Select Register */ + +#pragma ADDRESS vw0c_addr 005CH /* Voltage Monitor 0 Circuit Control Register */ + +#pragma ADDRESS vw1c_addr 005DH /* Voltage Monitor 1 Circuit Control Register */ + +#pragma ADDRESS rstfr_addr 005FH /* Reset Source Determination Register */ + +#pragma ADDRESS fr18s0_addr 0064H /* High-Speed On-Chip Oscillator 18.432 MHz Control Register 0 */ + +#pragma ADDRESS fr18s1_addr 0065H /* High-Speed On-Chip Oscillator 18.432 MHz Control Register 1 */ + +#pragma ADDRESS frv1_addr 0067H /* High-Speed On-Chip Oscillator Control Register 1 */ + +#pragma ADDRESS frv2_addr 0068H /* High-Speed On-Chip Oscillator Control Register 2 */ + +#pragma ADDRESS u0mr_addr 0080H /* UART0 Transmit/Receive Mode Register */ + +#pragma ADDRESS u0brg_addr 0081H /* UART0 Bit Rate Register */ + +#pragma ADDRESS u0tbl_addr 0082H /* UART0 Transmit Buffer Register Low */ + +#pragma ADDRESS u0tbh_addr 0083H /* UART0 Transmit Buffer Register Hogh */ + +#pragma ADDRESS u0c0_addr 0084H /* UART0 Transmit/Receive Control Register 0 */ + +#pragma ADDRESS u0c1_addr 0085H /* UART0 Transmit/Receive Control Register 1 */ + +#pragma ADDRESS u0rb_addr 0086H /* UART0 Receive Buffer Register */ + +#pragma ADDRESS u0ir_addr 0088H /* UART0 Interrupt Flag and Enable Register */ + +#pragma ADDRESS ad0_addr 0098H /* A/D Register 0 */ + +#pragma ADDRESS ad1_addr 009AH /* A/D Register 1 */ + +#pragma ADDRESS admod_addr 009CH /* A/D Mode Register */ + +#pragma ADDRESS adinsel_addr 009DH /* A/D Input Select Register */ + +#pragma ADDRESS adcon0_addr 009EH /* A/D Control Register 0 */ + +#pragma ADDRESS adicsr_addr 009FH /* A/D Interrupt Control Status Register */ + +#pragma ADDRESS pd1_addr 00A9H /* Port P1 Direction Register */ + +#pragma ADDRESS pd3_addr 00ABH /* Port P3 Direction Register */ + +#pragma ADDRESS pd4_addr 00ACH /* Port P4 Direction Register */ + +#pragma ADDRESS pda_addr 00ADH /* Port PA Direction Register */ + +#pragma ADDRESS p1_addr 00AFH /* Port P1 Register */ + +#pragma ADDRESS p3_addr 00B1H /* Port P3 Register */ + +#pragma ADDRESS p4_addr 00B2H /* Port P4 Register */ + +#pragma ADDRESS pa_addr 00B3H /* Port PA Register */ + +#pragma ADDRESS pur1_addr 00B5H /* Pull-Up Control Register 1 */ + +#pragma ADDRESS pur3_addr 00B7H /* Pull-Up Control Register 3 */ + +#pragma ADDRESS pur4_addr 00B8H /* Pull-Up Control Register 4 */ + +#pragma ADDRESS pinsr_addr 00B9H /* Port I/O Function Control Register */ + +#pragma ADDRESS drr1_addr 00BBH /* Drive Capacity Control Register 1 */ + +#pragma ADDRESS drr3_addr 00BDH /* Drive Capacity Control Register 3 */ + +#pragma ADDRESS pod1_addr 00C1H /* Open-Drain Control Register 1 */ + +#pragma ADDRESS pod3_addr 00C3H /* Open-Drain Control Register 3 */ + +#pragma ADDRESS pod4_addr 00C4H /* Open-Drain Control Register 4 */ + +#pragma ADDRESS pamcr_addr 00C5H /* Port PA Mode Control Register */ + +#pragma ADDRESS pml1_addr 00C8H /* Port 1 Function Mapping Register 0 */ + +#pragma ADDRESS pmh1_addr 00C9H /* Port 1 Function Mapping Register 1 */ + +#pragma ADDRESS pml3_addr 00CCH /* Port 3 Function Mapping Register 0 */ + +#pragma ADDRESS pmh3_addr 00CDH /* Port 3 Function Mapping Register 1 */ + +#pragma ADDRESS pml4_addr 00CEH /* Port 4 Function Mapping Register 0 */ + +#pragma ADDRESS pmh4_addr 00CFH /* Port 4 Function Mapping Register 1 */ + +#pragma ADDRESS pmh1e_addr 00D1H /* Port 1 Function Mapping Expansion Register */ + +#pragma ADDRESS pmh4e_addr 00D5H /* Port 4 Function Mapping Expansion Register */ + +#pragma ADDRESS trj_addr 00D8H /* Timer RJ Counter Register, Timer RJ Reload Register */ + +#pragma ADDRESS trjcr_addr 00DAH /* Timer RJ Control Register */ + +#pragma ADDRESS trjioc_addr 00DBH /* Timer RJ I/O Control Register */ + +#pragma ADDRESS trjmr_addr 00DCH /* Timer RJ Mode Register */ + +#pragma ADDRESS trjisr_addr 00DDH /* Timer RJ Event Select Register */ + +#pragma ADDRESS trjir_addr 00DEH /* Timer RJ Interrupt Control Register */ + +#pragma ADDRESS trbcr_addr 00E0H /* Timer RB Control Register */ + +#pragma ADDRESS trbocr_addr 00E1H /* Timer RB One-Shot Control Register */ + +#pragma ADDRESS trbioc_addr 00E2H /* Timer RB I/O Control Register */ + +#pragma ADDRESS trbmr_addr 00E3H /* Timer RB Mode Register */ + +#pragma ADDRESS trbpre_addr 00E4H /* Timer RB Prescaler Register */ + +#pragma ADDRESS trbpr_addr 00E5H /* Timer RB Primary Register */ + +#pragma ADDRESS trbsc_addr 00E6H /* Timer RB Secondary Register */ + +#pragma ADDRESS trbir_addr 00E7H /* Timer RB Interrupt Control Register */ + +#pragma ADDRESS trccnt_addr 00E8H /* Timer RC Counter */ + +#pragma ADDRESS trcgra_addr 00EAH /* Timer RC General Register A */ + +#pragma ADDRESS trcgrb_addr 00ECH /* Timer RC General Register B */ + +#pragma ADDRESS trcgrc_addr 00EEH /* Timer RC General Register C */ + +#pragma ADDRESS trcgrd_addr 00F0H /* Timer RC General Register D */ + +#pragma ADDRESS trcmr_addr 00F2H /* Timer RC Mode Register */ + +#pragma ADDRESS trccr1_addr 00F3H /* Timer RC Control Register 1 */ + +#pragma ADDRESS trcier_addr 00F4H /* Timer RC Interrupt Enable Register */ + +#pragma ADDRESS trcsr_addr 00F5H /* Timer RC Status Register */ + +#pragma ADDRESS trcior0_addr 00F6H /* Timer RC I/O Control Register 0 */ + +#pragma ADDRESS trcior1_addr 00F7H /* Timer RC I/O Control Register 1 */ + +#pragma ADDRESS trccr2_addr 00F8H /* Timer RC Control Register 2 */ + +#pragma ADDRESS trcdf_addr 00F9H /* Timer RC Digital Filter Function Select Register */ + +#pragma ADDRESS trcoer_addr 00FAH /* Timer RC Output Enable Register */ + +#pragma ADDRESS trcadcr_addr 00FBH /* Timer RC A/D Conversion Trigger Control Register */ + +#pragma ADDRESS trcopr_addr 00FCH /* Timer RC Waveform Output Manipulation Register */ + +#pragma ADDRESS wcmpr_addr 0180H /* Comparator B Control Register */ + +#pragma ADDRESS wcb1intr_addr 0181H /* Comparator B1 Interrupt Control Register */ + +#pragma ADDRESS wcb3intr_addr 0182H /* Comparator B3 Interrupt Control Register */ + +#pragma ADDRESS fst_addr 01A9H /* Flash Memory Status Register */ + +#pragma ADDRESS fmr0_addr 01AAH /* Flash Memory Control Register 0 */ + +#pragma ADDRESS fmr1_addr 01ABH /* Flash Memory Control Register 1 */ + +#pragma ADDRESS fmr2_addr 01ACH /* Flash Memory Control Register 2 */ + +#pragma ADDRESS frefr_addr 01ADH /* Flash Memory Refresh Control Register */ + +#pragma ADDRESS aiadr0_addr 01C0H /* Address Match Interrupt Register 0 */ + +#pragma ADDRESS aien0_addr 01C3H /* Address Match Interrupt Enable Register 0 */ + +#pragma ADDRESS aiadr1_addr 01C4H /* Address Match Interrupt Register 1 */ + +#pragma ADDRESS aien1_addr 01C7H /* Address Match Interrupt Enable Register 1 */ + +/******************************************************** +* declare SFR union * +********************************************************/ +struct bit_def_b { + unsigned char b0:1; + unsigned char b1:1; + unsigned char b2:1; + unsigned char b3:1; + unsigned char b4:1; + unsigned char b5:1; + unsigned char b6:1; + unsigned char b7:1; +}; + +struct bit_def_w { + unsigned char b0:1; + unsigned char b1:1; + unsigned char b2:1; + unsigned char b3:1; + unsigned char b4:1; + unsigned char b5:1; + unsigned char b6:1; + unsigned char b7:1; + + unsigned char b8:1; + unsigned char b9:1; + unsigned char b10:1; + unsigned char b11:1; + unsigned char b12:1; + unsigned char b13:1; + unsigned char b14:1; + unsigned char b15:1; +}; + +struct bit_def_dw { + unsigned char b0:1; + unsigned char b1:1; + unsigned char b2:1; + unsigned char b3:1; + unsigned char b4:1; + unsigned char b5:1; + unsigned char b6:1; + unsigned char b7:1; + + unsigned char b8:1; + unsigned char b9:1; + unsigned char b10:1; + unsigned char b11:1; + unsigned char b12:1; + unsigned char b13:1; + unsigned char b14:1; + unsigned char b15:1; + + unsigned char b16:1; + unsigned char b17:1; + unsigned char b18:1; + unsigned char b19:1; + unsigned char b20:1; + unsigned char b21:1; + unsigned char b22:1; + unsigned char b23:1; + + unsigned char b24:1; + unsigned char b25:1; + unsigned char b26:1; + unsigned char b27:1; + unsigned char b28:1; + unsigned char b29:1; + unsigned char b30:1; + unsigned char b31:1; +}; + +union byte_def{ + struct bit_def_b bit; + unsigned char byte; +}; + +union word_def{ + struct bit_def_w bit; + struct{ + unsigned char low; /* low 8 bit */ + unsigned char high; /* high 8 bit */ + } byte; + unsigned short word; +}; + +union dword_def{ + struct bit_def_dw bit; + struct{ + unsigned char low; /* low 8 bit */ + unsigned char mid; /* mid 8 bit */ + unsigned char high; /* high 8 bit */ + unsigned char nc; /* non use */ + } byte; + unsigned long dword; +}; +/******************************************************** +* declare SFR bit * +********************************************************/ + +/*------------------------------------------------------ + Processor Mode Register 0 +------------------------------------------------------*/ +union byte_def pm0_addr; +#define pm0 pm0_addr.byte + +#define srst pm0_addr.bit.b3 /* Software reset bit */ + +/*------------------------------------------------------ + Module Standby Control Register +------------------------------------------------------*/ +union byte_def mstcr_addr; +#define mstcr mstcr_addr.byte + +#define msttrj mstcr_addr.bit.b0 /* Timer RJ2 standby bit */ +#define msttrb mstcr_addr.bit.b1 /* Timer RB2 standby bit */ +#define mstad mstcr_addr.bit.b4 /* A/D converter standby bit */ +#define msttrc mstcr_addr.bit.b5 /* Timer RC standby bit */ +#define mstuart mstcr_addr.bit.b6 /* UART0 standby bit */ + +/*------------------------------------------------------ + Protect Register +------------------------------------------------------*/ +union byte_def prcr_addr; +#define prcr prcr_addr.byte + +#define prc0 prcr_addr.bit.b0 /* Protect bit 0 */ +#define prc1 prcr_addr.bit.b1 /* Protect bit 1 */ +#define prc3 prcr_addr.bit.b3 /* Protect bit 3 */ +#define prc4 prcr_addr.bit.b4 /* Protect bit 4 */ + +/*------------------------------------------------------ + Hardware Reset Protect Register +------------------------------------------------------*/ +union byte_def hrpr_addr; +#define hrpr hrpr_addr.byte + +#define pamcre hrpr_addr.bit.b0 /* PAMCR register write enable bit */ + +/*------------------------------------------------------ + External Clock Control Register +------------------------------------------------------*/ +union byte_def exckcr_addr; +#define exckcr exckcr_addr.byte + +#define ckpt0 exckcr_addr.bit.b0 /* P4_6 and P4_7 pin function select bit */ +#define ckpt1 exckcr_addr.bit.b1 /* P4_6 and P4_7 pin function select bit */ +#define xrcut exckcr_addr.bit.b6 /* XIN-XOUT on-chip feedback resistor select bit */ + +/*------------------------------------------------------ + High-Speed/Low-Speed On-Chip Oscillator Control Register +------------------------------------------------------*/ +union byte_def ococr_addr; +#define ococr ococr_addr.byte + +#define hocoe ococr_addr.bit.b0 /* High-speed on-chip oscillator oscillation enable bit */ +#define locodis ococr_addr.bit.b1 /* Low-speed on-chip oscillator oscillation stop bit */ + +/*------------------------------------------------------ + System Clock f Control Register +------------------------------------------------------*/ +union byte_def sckcr_addr; +#define sckcr sckcr_addr.byte + +#define phissel0 sckcr_addr.bit.b0 /* CPU clock division ratio select bit */ +#define phissel1 sckcr_addr.bit.b1 /* CPU clock division ratio select bit */ +#define phissel2 sckcr_addr.bit.b2 /* CPU clock division ratio select bit */ +#define waitm sckcr_addr.bit.b5 /* Wait control bit */ +#define hscksel sckcr_addr.bit.b6 /* High-speed on-chip oscillator/XIN clock select bit */ + +/*------------------------------------------------------ + System Clock f Select Register +------------------------------------------------------*/ +union byte_def phisel_addr; +#define phisel phisel_addr.byte + +#define phisel0 phisel_addr.bit.b0 /* System clock division select bit */ +#define phisel1 phisel_addr.bit.b1 /* System clock division select bit */ +#define phisel2 phisel_addr.bit.b2 /* System clock division select bit */ +#define phisel3 phisel_addr.bit.b3 /* System clock division select bit */ +#define phisel4 phisel_addr.bit.b4 /* System clock division select bit */ +#define phisel5 phisel_addr.bit.b5 /* System clock division select bit */ +#define phisel6 phisel_addr.bit.b6 /* System clock division select bit */ +#define phisel7 phisel_addr.bit.b7 /* System clock division select bit */ + +/*------------------------------------------------------ + Clock Stop Control Register +------------------------------------------------------*/ +union byte_def ckstpr_addr; +#define ckstpr ckstpr_addr.byte + +#define stpm ckstpr_addr.bit.b0 /* All clock stop control bit */ +#define wckstp ckstpr_addr.bit.b1 /* fBASE stop bit in wait mode */ +#define pscstp ckstpr_addr.bit.b2 /* Prescaler stop bit */ +#define scksel ckstpr_addr.bit.b7 /* System base clock select bit */ + +/*------------------------------------------------------ + Clock Control Register When Returning from Modes +------------------------------------------------------*/ +union byte_def ckrscr_addr; +#define ckrscr ckrscr_addr.byte + +#define ckst0 ckrscr_addr.bit.b0 /* Clock oscillator circuit oscillation stabilization state select bit */ +#define ckst1 ckrscr_addr.bit.b1 /* Clock oscillator circuit oscillation stabilization state select bit */ +#define ckst2 ckrscr_addr.bit.b2 /* Clock oscillator circuit oscillation stabilization state select bit */ +#define ckst3 ckrscr_addr.bit.b3 /* Clock oscillator circuit oscillation stabilization state select bit */ +#define phisrs ckrscr_addr.bit.b5 /* CPU clock division select bit when returning from wait mode or stop mode */ +#define waitrs ckrscr_addr.bit.b6 /* System base clock select bit when returning from wait mode */ +#define stoprs ckrscr_addr.bit.b7 /* System base clock select bit when returning from stop mode */ + +/*------------------------------------------------------ + Oscillation Stop Detection Register +------------------------------------------------------*/ +union byte_def bakcr_addr; +#define bakcr bakcr_addr.byte + +#define xinbake bakcr_addr.bit.b0 /* Oscillation stop detection enable bit */ +#define ckswie bakcr_addr.bit.b1 /* Oscillation stop detection interrupt enable bit */ +#define xinhalt bakcr_addr.bit.b2 /* Clock monitor bit */ +#define ckswif bakcr_addr.bit.b3 /* Oscillation stop detection interrupt request flag */ + +/*------------------------------------------------------ + Watchdog Timer Function Register +------------------------------------------------------*/ +union byte_def risr_addr; +#define risr risr_addr.byte + +#define ufif risr_addr.bit.b6 /* WDT underflow detection flag */ +#define ris risr_addr.bit.b7 /* WDT interrupt/reset switch bit */ + +/*------------------------------------------------------ + Watchdog Timer Reset Register +------------------------------------------------------*/ +union byte_def wdtr_addr; +#define wdtr wdtr_addr.byte + +/*------------------------------------------------------ + Watchdog Timer Start Register +------------------------------------------------------*/ +union byte_def wdts_addr; +#define wdts wdts_addr.byte + +/*------------------------------------------------------ + Watchdog Timer Control Register +------------------------------------------------------*/ +union byte_def wdtc_addr; +#define wdtc wdtc_addr.byte + +#define wdtc6 wdtc_addr.bit.b6 /* Watchdog timer count source select bit */ +#define wdtc7 wdtc_addr.bit.b7 /* Watchdog timer count source select bit */ + +/*------------------------------------------------------ + Count Source Protection Mode Register +------------------------------------------------------*/ +union byte_def cspr_addr; +#define cspr cspr_addr.byte + +#define cspro cspr_addr.bit.b7 /* Count source protection mode select bit */ + +/*------------------------------------------------------ + Periodic Timer Interrupt Control Register +------------------------------------------------------*/ +union byte_def wdtir_addr; +#define wdtir wdtir_addr.byte + +#define wdtif wdtir_addr.bit.b6 /* Periodic timer interrupt request flag */ +#define wdtie wdtir_addr.bit.b7 /* Periodic timer interrupt enable bit */ + +/*------------------------------------------------------ + External Input Enable Register +------------------------------------------------------*/ +union byte_def inten_addr; +#define inten inten_addr.byte + +#define int0en inten_addr.bit.b0 /* INT0 input enable bit */ +#define int1en inten_addr.bit.b1 /* INT1 input enable bit */ +#define int2en inten_addr.bit.b2 /* INT2 input enable bit */ +#define int3en inten_addr.bit.b3 /* INT3 input enable bit */ + +/*------------------------------------------------------ + INT Input Filter Select Register 0 +------------------------------------------------------*/ +union byte_def intf0_addr; +#define intf0 intf0_addr.byte + +#define int0f0 intf0_addr.bit.b0 /* INT0 input filter select bit */ +#define int0f1 intf0_addr.bit.b1 /* INT0 input filter select bit */ +#define int1f0 intf0_addr.bit.b2 /* INT1 input filter select bit */ +#define int1f1 intf0_addr.bit.b3 /* INT1 input filter select bit */ +#define int2f0 intf0_addr.bit.b4 /* INT2 input filter select bit */ +#define int2f1 intf0_addr.bit.b5 /* INT2 input filter select bit */ +#define int3f0 intf0_addr.bit.b6 /* INT3 input filter select bit */ +#define int3f1 intf0_addr.bit.b7 /* INT3 input filter select bit */ + +/*------------------------------------------------------ + INT Input Edge Select Register 0 +------------------------------------------------------*/ +union byte_def iscr0_addr; +#define iscr0 iscr0_addr.byte + +#define int0sa iscr0_addr.bit.b0 /* INT0 input edge select bit */ +#define int0sb iscr0_addr.bit.b1 /* INT0 input edge select bit */ +#define int1sa iscr0_addr.bit.b2 /* INT1 input edge select bit */ +#define int1sb iscr0_addr.bit.b3 /* INT1 input edge select bit */ +#define int2sa iscr0_addr.bit.b4 /* INT2 input edge select bit */ +#define int2sb iscr0_addr.bit.b5 /* INT2 input edge select bit */ +#define int3sa iscr0_addr.bit.b6 /* INT3 input edge select bit */ +#define int3sb iscr0_addr.bit.b7 /* INT3 input edge select bit */ + +/*------------------------------------------------------ + Key Input Enable Register +------------------------------------------------------*/ +union byte_def kien_addr; +#define kien kien_addr.byte + +#define ki0en kien_addr.bit.b0 /* KI0 input enable bit */ +#define ki0pl kien_addr.bit.b1 /* KI0 input edge select bit */ +#define ki1en kien_addr.bit.b2 /* KI1 input enable bit */ +#define ki1pl kien_addr.bit.b3 /* KI1 input edge select bit */ +#define ki2en kien_addr.bit.b4 /* KI2 input enable bit */ +#define ki2pl kien_addr.bit.b5 /* KI2 input edge select bit */ +#define ki3en kien_addr.bit.b6 /* KI3 input enable bit */ +#define ki3pl kien_addr.bit.b7 /* KI3 input edge select bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 0 +------------------------------------------------------*/ +union byte_def ilvl0_addr; +#define ilvl0 ilvl0_addr.byte + +#define ilvl00 ilvl0_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl01 ilvl0_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl04 ilvl0_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl05 ilvl0_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 2 +------------------------------------------------------*/ +union byte_def ilvl2_addr; +#define ilvl2 ilvl2_addr.byte + +#define ilvl20 ilvl2_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl21 ilvl2_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl24 ilvl2_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl25 ilvl2_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 3 +------------------------------------------------------*/ +union byte_def ilvl3_addr; +#define ilvl3 ilvl3_addr.byte + +#define ilvl30 ilvl3_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl31 ilvl3_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl34 ilvl3_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl35 ilvl3_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 4 +------------------------------------------------------*/ +union byte_def ilvl4_addr; +#define ilvl4 ilvl4_addr.byte + +#define ilvl40 ilvl4_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl41 ilvl4_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl44 ilvl4_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl45 ilvl4_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 5 +------------------------------------------------------*/ +union byte_def ilvl5_addr; +#define ilvl5 ilvl5_addr.byte + +#define ilvl50 ilvl5_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl51 ilvl5_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl54 ilvl5_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl55 ilvl5_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 6 +------------------------------------------------------*/ +union byte_def ilvl6_addr; +#define ilvl6 ilvl6_addr.byte + +#define ilvl60 ilvl6_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl61 ilvl6_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl64 ilvl6_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl65 ilvl6_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 7 +------------------------------------------------------*/ +union byte_def ilvl7_addr; +#define ilvl7 ilvl7_addr.byte + +#define ilvl70 ilvl7_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl71 ilvl7_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl74 ilvl7_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl75 ilvl7_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 8 +------------------------------------------------------*/ +union byte_def ilvl8_addr; +#define ilvl8 ilvl8_addr.byte + +#define ilvl80 ilvl8_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl81 ilvl8_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl84 ilvl8_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl85 ilvl8_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register 9 +------------------------------------------------------*/ +union byte_def ilvl9_addr; +#define ilvl9 ilvl9_addr.byte + +#define ilvl90 ilvl9_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvl91 ilvl9_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvl94 ilvl9_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvl95 ilvl9_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register A +------------------------------------------------------*/ +union byte_def ilvla_addr; +#define ilvla ilvla_addr.byte + +#define ilvla0 ilvla_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvla1 ilvla_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvla4 ilvla_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvla5 ilvla_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register B +------------------------------------------------------*/ +union byte_def ilvlb_addr; +#define ilvlb ilvlb_addr.byte + +#define ilvlb0 ilvlb_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvlb1 ilvlb_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvlb4 ilvlb_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvlb5 ilvlb_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register C +------------------------------------------------------*/ +union byte_def ilvlc_addr; +#define ilvlc ilvlc_addr.byte + +#define ilvlc0 ilvlc_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvlc1 ilvlc_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvlc4 ilvlc_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvlc5 ilvlc_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register D +------------------------------------------------------*/ +union byte_def ilvld_addr; +#define ilvld ilvld_addr.byte + +#define ilvld0 ilvld_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvld1 ilvld_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvld4 ilvld_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvld5 ilvld_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Priority Level Register E +------------------------------------------------------*/ +union byte_def ilvle_addr; +#define ilvle ilvle_addr.byte + +#define ilvle0 ilvle_addr.bit.b0 /* Interrupt priority level setting bit */ +#define ilvle1 ilvle_addr.bit.b1 /* Interrupt priority level setting bit */ +#define ilvle4 ilvle_addr.bit.b4 /* Interrupt priority level setting bit */ +#define ilvle5 ilvle_addr.bit.b5 /* Interrupt priority level setting bit */ + +/*------------------------------------------------------ + Interrupt Monitor Flag Register 0 +------------------------------------------------------*/ +union byte_def irr0_addr; +#define irr0 irr0_addr.byte + +#define irtj irr0_addr.bit.b0 /* Timer RJ2 interrupt request monitor flag */ +#define irtb irr0_addr.bit.b1 /* Timer RB2 interrupt request monitor flag */ +#define irtc irr0_addr.bit.b2 /* Timer RC interrupt request monitor flag */ +#define irs0t irr0_addr.bit.b4 /* UART0 transmit interrupt request monitor flag */ +#define irs0r irr0_addr.bit.b5 /* UART0 receive interrupt request monitor flag */ + +/*------------------------------------------------------ + Interrupt Monitor Flag Register 1 +------------------------------------------------------*/ +union byte_def irr1_addr; +#define irr1 irr1_addr.byte + +#define irad irr1_addr.bit.b2 /* A/D conversion interrupt request monitor flag */ +#define irfm irr1_addr.bit.b4 /* Flash ready interrupt request monitor flag */ +#define irwd irr1_addr.bit.b5 /* Periodic timer interrupt request monitor flag */ + +/*------------------------------------------------------ + Interrupt Monitor Flag Register 2 +------------------------------------------------------*/ +union byte_def irr2_addr; +#define irr2 irr2_addr.byte + +#define ircmp1 irr2_addr.bit.b2 /* Comparator B1 interrupt request monitor flag */ +#define ircmp3 irr2_addr.bit.b3 /* Comparator B3 interrupt request monitor flag */ + +/*------------------------------------------------------ + External Interrupt Flag Register +------------------------------------------------------*/ +union byte_def irr3_addr; +#define irr3 irr3_addr.byte + +#define iri0 irr3_addr.bit.b0 /* INT0 interrupt request flag */ +#define iri1 irr3_addr.bit.b1 /* INT1 interrupt request flag */ +#define iri2 irr3_addr.bit.b2 /* INT2 interrupt request flag */ +#define iri3 irr3_addr.bit.b3 /* INT3 interrupt request flag */ +#define irki irr3_addr.bit.b5 /* Key input interrupt request flag */ + +/*------------------------------------------------------ + Voltage Monitor Circuit Edge Select Register +------------------------------------------------------*/ +union byte_def vcac_addr; +#define vcac vcac_addr.byte + +#define vcac1 vcac_addr.bit.b1 /* Voltage monitor 1 circuit edge select bit */ + +/*------------------------------------------------------ + Voltage Detect Register 2 +------------------------------------------------------*/ +union byte_def vca2_addr; +#define vca2 vca2_addr.byte + +#define lpe vca2_addr.bit.b0 /* Internal low-power-consumption enable bit */ +#define vc0e vca2_addr.bit.b5 /* Voltage detection 0 enable bit */ +#define vc1e vca2_addr.bit.b6 /* Voltage detection 1 enable bit */ + +/*------------------------------------------------------ + Voltage Detection 1 Level Select Register +------------------------------------------------------*/ +union byte_def vd1ls_addr; +#define vd1ls vd1ls_addr.byte + +#define vd1s1 vd1ls_addr.bit.b1 /* Voltage detection 1 Level select bit */ +#define vd1s2 vd1ls_addr.bit.b2 /* Voltage detection 1 Level select bit */ +#define vd1s3 vd1ls_addr.bit.b3 /* Voltage detection 1 Level select bit */ + +/*------------------------------------------------------ + Voltage Monitor 0 Circuit Control Register +------------------------------------------------------*/ +union byte_def vw0c_addr; +#define vw0c vw0c_addr.byte + +#define vw0c0 vw0c_addr.bit.b0 /* Voltage monitor 0 reset enable bit */ +#define vw0c1 vw0c_addr.bit.b1 /* Voltage monitor 0 digital filter mode select bit */ +#define vw0f0 vw0c_addr.bit.b4 /* Sampling clock select bit */ +#define vw0f1 vw0c_addr.bit.b5 /* Sampling clock select bit */ + +/*------------------------------------------------------ + Voltage Monitor 1 Circuit Control Register +------------------------------------------------------*/ +union byte_def vw1c_addr; +#define vw1c vw1c_addr.byte + +#define vw1c0 vw1c_addr.bit.b0 /* Voltage monitor 1 interrupt enable bit */ +#define vw1c1 vw1c_addr.bit.b1 /* Voltage monitor 1 digital filter mode select bit */ +#define vw1c2 vw1c_addr.bit.b2 /* Voltage change detection flag */ +#define vw1c3 vw1c_addr.bit.b3 /* Voltage detection 1 signal monitor flag */ +#define vw1f0 vw1c_addr.bit.b4 /* Sampling clock select bit */ +#define vw1f1 vw1c_addr.bit.b5 /* Sampling clock select bit */ +#define vw1c7 vw1c_addr.bit.b7 /* Voltage monitor 1 interrupt generation condition select bit */ + +/*------------------------------------------------------ + Reset Source Determination Register +------------------------------------------------------*/ +union byte_def rstfr_addr; +#define rstfr rstfr_addr.byte + +#define cwr rstfr_addr.bit.b0 /* Cold start-up/warm start-up determine flag */ +#define hwr rstfr_addr.bit.b1 /* Hardware reset detect flag */ +#define swr rstfr_addr.bit.b2 /* Software reset detect flag */ +#define wdr rstfr_addr.bit.b3 /* Watchdog timer reset detect flag */ + +/*------------------------------------------------------ + High-Speed On-Chip Oscillator 18.432 MHz Control Register 0 +------------------------------------------------------*/ +union byte_def fr18s0_addr; +#define fr18s0 fr18s0_addr.byte + +/*------------------------------------------------------ + High-Speed On-Chip Oscillator 18.432 MHz Control Register 1 +------------------------------------------------------*/ +union byte_def fr18s1_addr; +#define fr18s1 fr18s1_addr.byte + +/*------------------------------------------------------ + High-Speed On-Chip Oscillator Control Register 1 +------------------------------------------------------*/ +union byte_def frv1_addr; +#define frv1 frv1_addr.byte + +/*------------------------------------------------------ + High-Speed On-Chip Oscillator Control Register 2 +------------------------------------------------------*/ +union byte_def frv2_addr; +#define frv2 frv2_addr.byte + +/*------------------------------------------------------ + UART0 Transmit/Receive Mode Register +------------------------------------------------------*/ +union byte_def u0mr_addr; +#define u0mr u0mr_addr.byte + +#define smd0_u0mr u0mr_addr.bit.b0 /* Serial I/O mode select bit */ +#define smd1_u0mr u0mr_addr.bit.b1 /* Serial I/O mode select bit */ +#define smd2_u0mr u0mr_addr.bit.b2 /* Serial I/O mode select bit */ +#define ckdir_u0mr u0mr_addr.bit.b3 /* Internal/external clock select bit */ +#define stps_u0mr u0mr_addr.bit.b4 /* Stop bit length select bit */ +#define pry_u0mr u0mr_addr.bit.b5 /* Odd/even parity select bit */ +#define prye_u0mr u0mr_addr.bit.b6 /* Parity enable bit */ + +/*------------------------------------------------------ + UART0 Bit Rate Register +------------------------------------------------------*/ +union byte_def u0brg_addr; +#define u0brg u0brg_addr.byte + +/*------------------------------------------------------ + UART0 Transmit Buffer Register Low +------------------------------------------------------*/ +union byte_def u0tbl_addr; +#define u0tbl u0tbl_addr.byte + +/*------------------------------------------------------ + UART0 Transmit Buffer Register High +------------------------------------------------------*/ +union byte_def u0tbh_addr; +#define u0tbh u0tbh_addr.byte + +/*------------------------------------------------------ + UART0 Transmit/Receive Control Register 0 +------------------------------------------------------*/ +union byte_def u0c0_addr; +#define u0c0 u0c0_addr.byte + +#define clk0_u0c0 u0c0_addr.bit.b0 /* U0BRG count source select bit */ +#define clk1_u0c0 u0c0_addr.bit.b1 /* U0BRG count source select bit */ +#define txept_u0c0 u0c0_addr.bit.b3 /* Transmit register empty flag */ +#define dfe_u0c0 u0c0_addr.bit.b4 /* RXD0 digital filter enable bit */ +#define nch_u0c0 u0c0_addr.bit.b5 /* Data output select bit */ +#define ckpol_u0c0 u0c0_addr.bit.b6 /* CLK polarity select bit */ +#define uform_u0c0 u0c0_addr.bit.b7 /* Transfer format select bit */ + +/*------------------------------------------------------ + UART0 Transmit/Receive Control Register 1 +------------------------------------------------------*/ +union byte_def u0c1_addr; +#define u0c1 u0c1_addr.byte + +#define te_u0c1 u0c1_addr.bit.b0 /* Transmit enable bit */ +#define ti_u0c1 u0c1_addr.bit.b1 /* Transmit buffer empty flag */ +#define re_u0c1 u0c1_addr.bit.b2 /* Receive enable bit */ +#define ri_u0c1 u0c1_addr.bit.b3 /* Receive complete flag */ +#define u0irs_u0c1 u0c1_addr.bit.b4 /* UART0 transmit interrupt source select bit */ +#define u0rrm_u0c1 u0c1_addr.bit.b5 /* UART0 continuous receive mode enable bit */ + +/*------------------------------------------------------ + UART0 Receive Buffer Register +------------------------------------------------------*/ +union word_def u0rb_addr; +#define u0rb u0rb_addr.word + +/*------------------------------------------------------ + UART0 Interrupt Flag and Enable Register +------------------------------------------------------*/ +union byte_def u0ir_addr; +#define u0ir u0ir_addr.byte + +#define u0rie u0ir_addr.bit.b2 /* UART0 receive interrupt enable bit */ +#define u0tie u0ir_addr.bit.b3 /* UART0 transmit interrupt enable bit */ +#define u0rif u0ir_addr.bit.b6 /* UART0 receive interrupt flag */ +#define u0tif u0ir_addr.bit.b7 /* UART0 transmit interrupt flag */ + +/*------------------------------------------------------ + A/D Register 0 +------------------------------------------------------*/ +union word_def ad0_addr; +#define ad0 ad0_addr.word /* A/D Register 0 */ + +#define ad0l ad0_addr.byte.low /* A/D Register 0 Low */ +#define ad0h ad0_addr.byte.high /* A/D Register 0 High */ + +/*------------------------------------------------------ + A/D Register 1 +------------------------------------------------------*/ +union word_def ad1_addr; +#define ad1 ad1_addr.word /* A/D Register 1 */ + +#define ad1l ad1_addr.byte.low /* A/D Register 1 Low */ +#define ad1h ad1_addr.byte.high /* A/D Register 1 High */ + +/*------------------------------------------------------ + A/D Mode Register +------------------------------------------------------*/ +union byte_def admod_addr; +#define admod admod_addr.byte + +#define cks0 admod_addr.bit.b0 /* A/D conversion clock select bit */ +#define cks1 admod_addr.bit.b1 /* A/D conversion clock select bit */ +#define cks2 admod_addr.bit.b2 /* A/D conversion clock select bit */ +#define md0 admod_addr.bit.b3 /* A/D operating mode select bit */ +#define md1 admod_addr.bit.b4 /* A/D operating mode select bit */ +#define adcap0 admod_addr.bit.b6 /* A/D conversion trigger select bit */ +#define adcap1 admod_addr.bit.b7 /* A/D conversion trigger select bit */ + +/*------------------------------------------------------ + A/D Input Select Register +------------------------------------------------------*/ +union byte_def adinsel_addr; +#define adinsel adinsel_addr.byte + +#define ch0 adinsel_addr.bit.b0 /* Channel select bit */ +#define adgsel0 adinsel_addr.bit.b6 /* A/D input group select bit */ +#define adgsel1 adinsel_addr.bit.b7 /* A/D input group select bit */ + +/*------------------------------------------------------ + A/D Control Register 0 +------------------------------------------------------*/ +union byte_def adcon0_addr; +#define adcon0 adcon0_addr.byte + +#define adst adcon0_addr.bit.b0 /* A/D conversion start bit */ + +/*------------------------------------------------------ + A/D Interrupt Control Status Register +------------------------------------------------------*/ +union byte_def adicsr_addr; +#define adicsr adicsr_addr.byte + +#define adie adicsr_addr.bit.b6 /* A/D conversion interrupt enable bit */ +#define adf adicsr_addr.bit.b7 /* A/D conversion Interrupt request bit */ + +/*------------------------------------------------------ + Port P1 Direction Register +------------------------------------------------------*/ +union byte_def pd1_addr; +#define pd1 pd1_addr.byte + +#define pd1_0 pd1_addr.bit.b0 /* Port P1_0 direction bit */ +#define pd1_1 pd1_addr.bit.b1 /* Port P1_1 direction bit */ +#define pd1_2 pd1_addr.bit.b2 /* Port P1_2 direction bit */ +#define pd1_3 pd1_addr.bit.b3 /* Port P1_3 direction bit */ +#define pd1_4 pd1_addr.bit.b4 /* Port P1_4 direction bit */ +#define pd1_5 pd1_addr.bit.b5 /* Port P1_5 direction bit */ +#define pd1_6 pd1_addr.bit.b6 /* Port P1_6 direction bit */ +#define pd1_7 pd1_addr.bit.b7 /* Port P1_7 direction bit */ + +/*------------------------------------------------------ + Port P3 Direction Register +------------------------------------------------------*/ +union byte_def pd3_addr; +#define pd3 pd3_addr.byte + +#define pd3_3 pd3_addr.bit.b3 /* Port P3_3 direction bit */ +#define pd3_4 pd3_addr.bit.b4 /* Port P3_4 direction bit */ +#define pd3_5 pd3_addr.bit.b5 /* Port P3_5 direction bit */ +#define pd3_7 pd3_addr.bit.b7 /* Port P3_7 direction bit */ + +/*------------------------------------------------------ + Port P4 Direction Register +------------------------------------------------------*/ +union byte_def pd4_addr; +#define pd4 pd4_addr.byte + +#define pd4_2 pd4_addr.bit.b2 /* Port P4_2 direction bit */ +#define pd4_5 pd4_addr.bit.b5 /* Port P4_5 direction bit */ +#define pd4_6 pd4_addr.bit.b6 /* Port P4_6 direction bit */ +#define pd4_7 pd4_addr.bit.b7 /* Port P4_7 direction bit */ + +/*------------------------------------------------------ + Port PA Direction Register +------------------------------------------------------*/ +union byte_def pda_addr; +#define pda pda_addr.byte + +#define pda_0 pda_addr.bit.b0 /* Port PA_0 direction bit */ + +/*------------------------------------------------------ + Port P1 Register +------------------------------------------------------*/ +union byte_def p1_addr; +#define p1 p1_addr.byte + +#define p1_0 p1_addr.bit.b0 /* Port P1_0 bit */ +#define p1_1 p1_addr.bit.b1 /* Port P1_1 bit */ +#define p1_2 p1_addr.bit.b2 /* Port P1_2 bit */ +#define p1_3 p1_addr.bit.b3 /* Port P1_3 bit */ +#define p1_4 p1_addr.bit.b4 /* Port P1_4 bit */ +#define p1_5 p1_addr.bit.b5 /* Port P1_5 bit */ +#define p1_6 p1_addr.bit.b6 /* Port P1_6 bit */ +#define p1_7 p1_addr.bit.b7 /* Port P1_7 bit */ + +/*------------------------------------------------------ + Port P3 Register +------------------------------------------------------*/ +union byte_def p3_addr; +#define p3 p3_addr.byte + +#define p3_3 p3_addr.bit.b3 /* Port P3_3 bit */ +#define p3_4 p3_addr.bit.b4 /* Port P3_4 bit */ +#define p3_5 p3_addr.bit.b5 /* Port P3_5 bit */ +#define p3_7 p3_addr.bit.b7 /* Port P3_7 bit */ + +/*------------------------------------------------------ + Port P4 Register +------------------------------------------------------*/ +union byte_def p4_addr; +#define p4 p4_addr.byte + +#define p4_2 p4_addr.bit.b2 /* Port P4_2 bit */ +#define p4_5 p4_addr.bit.b5 /* Port P4_5 bit */ +#define p4_6 p4_addr.bit.b6 /* Port P4_6 bit */ +#define p4_7 p4_addr.bit.b7 /* Port P4_7 bit */ + +/*------------------------------------------------------ + Port PA Register +------------------------------------------------------*/ +union byte_def pa_addr; +#define pa pa_addr.byte + +#define pa_0 pa_addr.bit.b0 /* Port PA_0 bit */ + +/*------------------------------------------------------ + Pull-Up Control Register 1 +------------------------------------------------------*/ +union byte_def pur1_addr; +#define pur1 pur1_addr.byte + +#define pu1_0 pur1_addr.bit.b0 /* Port P1_0 pull-up control bit */ +#define pu1_1 pur1_addr.bit.b1 /* Port P1_1 pull-up control bit */ +#define pu1_2 pur1_addr.bit.b2 /* Port P1_2 pull-up control bit */ +#define pu1_3 pur1_addr.bit.b3 /* Port P1_3 pull-up control bit */ +#define pu1_4 pur1_addr.bit.b4 /* Port P1_4 pull-up control bit */ +#define pu1_5 pur1_addr.bit.b5 /* Port P1_5 pull-up control bit */ +#define pu1_6 pur1_addr.bit.b6 /* Port P1_6 pull-up control bit */ +#define pu1_7 pur1_addr.bit.b7 /* Port P1_7 pull-up control bit */ + +/*------------------------------------------------------ + Pull-Up Control Register 3 +------------------------------------------------------*/ +union byte_def pur3_addr; +#define pur3 pur3_addr.byte + +#define pu3_3 pur3_addr.bit.b3 /* Port P3_3 pull-up control bit */ +#define pu3_4 pur3_addr.bit.b4 /* Port P3_4 pull-up control bit */ +#define pu3_5 pur3_addr.bit.b5 /* Port P3_5 pull-up control bit */ +#define pu3_7 pur3_addr.bit.b7 /* Port P3_7 pull-up control bit */ + +/*------------------------------------------------------ + Pull-Up Control Register 4 +------------------------------------------------------*/ +union byte_def pur4_addr; +#define pur4 pur4_addr.byte + +#define pu4_2 pur4_addr.bit.b2 /* Port P4_2 pull-up control bit */ +#define pu4_5 pur4_addr.bit.b5 /* Port P4_5 pull-up control bit */ +#define pu4_6 pur4_addr.bit.b6 /* Port P4_6 pull-up control bit */ +#define pu4_7 pur4_addr.bit.b7 /* Port P4_7 pull-up control bit */ + +/*------------------------------------------------------ + Port I/O Function Control Register +------------------------------------------------------*/ +union byte_def pinsr_addr; +#define pinsr pinsr_addr.byte + +#define trjiosel pinsr_addr.bit.b6 /* TRJIO input signal select bit */ +#define ioinsel pinsr_addr.bit.b7 /* Pin level forced read-out bit */ + +/*------------------------------------------------------ + Drive Capacity Control Register 1 +------------------------------------------------------*/ +union byte_def drr1_addr; +#define drr1 drr1_addr.byte + +#define drr1_2 drr1_addr.bit.b2 /* Port P1_2 drive capacity control bit */ +#define drr1_3 drr1_addr.bit.b3 /* Port P1_3 drive capacity control bit */ +#define drr1_4 drr1_addr.bit.b4 /* Port P1_4 drive capacity control bit */ +#define drr1_5 drr1_addr.bit.b5 /* Port P1_5 drive capacity control bit */ + +/*------------------------------------------------------ + Drive Capacity Control Register 3 +------------------------------------------------------*/ +union byte_def drr3_addr; +#define drr3 drr3_addr.byte + +#define drr3_3 drr3_addr.bit.b3 /* Port P3_3 drive capacity control bit */ +#define drr3_4 drr3_addr.bit.b4 /* Port P3_4 drive capacity control bit */ +#define drr3_5 drr3_addr.bit.b5 /* Port P3_5 drive capacity control bit */ +#define drr3_7 drr3_addr.bit.b7 /* Port P3_7 drive capacity control bit */ + +/*------------------------------------------------------ + Open-Drain Control Register 1 +------------------------------------------------------*/ +union byte_def pod1_addr; +#define pod1 pod1_addr.byte + +#define pod1_0 pod1_addr.bit.b0 /* Port P1_0 open-drain control bit */ +#define pod1_1 pod1_addr.bit.b1 /* Port P1_1 open-drain control bit */ +#define pod1_2 pod1_addr.bit.b2 /* Port P1_2 open-drain control bit */ +#define pod1_3 pod1_addr.bit.b3 /* Port P1_3 open-drain control bit */ +#define pod1_4 pod1_addr.bit.b4 /* Port P1_4 open-drain control bit */ +#define pod1_5 pod1_addr.bit.b5 /* Port P1_5 open-drain control bit */ +#define pod1_6 pod1_addr.bit.b6 /* Port P1_6 open-drain control bit */ +#define pod1_7 pod1_addr.bit.b7 /* Port P1_7 open-drain control bit */ + +/*------------------------------------------------------ + Open-Drain Control Register 3 +------------------------------------------------------*/ +union byte_def pod3_addr; +#define pod3 pod3_addr.byte + +#define pod3_3 pod3_addr.bit.b3 /* Port P3_3 open-drain control bit */ +#define pod3_4 pod3_addr.bit.b4 /* Port P3_4 open-drain control bit */ +#define pod3_5 pod3_addr.bit.b5 /* Port P3_5 open-drain control bit */ +#define pod3_7 pod3_addr.bit.b7 /* Port P3_7 open-drain control bit */ + +/*------------------------------------------------------ + Open-Drain Control Register 4 +------------------------------------------------------*/ +union byte_def pod4_addr; +#define pod4 pod4_addr.byte + +#define pod4_2 pod4_addr.bit.b2 /* Port P4_2 open-drain control bit */ +#define pod4_5 pod4_addr.bit.b5 /* Port P4_5 open-drain control bit */ +#define pod4_6 pod4_addr.bit.b6 /* Port P4_6 open-drain control bit */ +#define pod4_7 pod4_addr.bit.b7 /* Port P4_7 open-drain control bit */ + +/*------------------------------------------------------ + Port PA Mode Control Register +------------------------------------------------------*/ +union byte_def pamcr_addr; +#define pamcr pamcr_addr.byte + +#define poda_0 pamcr_addr.bit.b0 /* Port PA_0 open-drain control bit */ +#define hwrste pamcr_addr.bit.b4 /* Hardware reset enabled bit */ + +/*------------------------------------------------------ + Port 1 Function Mapping Register 0 +------------------------------------------------------*/ +union byte_def pml1_addr; +#define pml1 pml1_addr.byte + +#define p10sel0 pml1_addr.bit.b0 /* Port P1_0 function select bit */ +#define p10sel1 pml1_addr.bit.b1 /* Port P1_0 function select bit */ +#define p11sel0 pml1_addr.bit.b2 /* Port P1_1 function select bit */ +#define p11sel1 pml1_addr.bit.b3 /* Port P1_1 function select bit */ +#define p12sel0 pml1_addr.bit.b4 /* Port P1_2 function select bit */ +#define p12sel1 pml1_addr.bit.b5 /* Port P1_2 function select bit */ +#define p13sel0 pml1_addr.bit.b6 /* Port P1_3 function select bit */ +#define p13sel1 pml1_addr.bit.b7 /* Port P1_3 function select bit */ + +/*------------------------------------------------------ + Port 1 Function Mapping Register 1 +------------------------------------------------------*/ +union byte_def pmh1_addr; +#define pmh1 pmh1_addr.byte + +#define p14sel0 pmh1_addr.bit.b0 /* Port P1_4 function select bit */ +#define p14sel1 pmh1_addr.bit.b1 /* Port P1_4 function select bit */ +#define p15sel0 pmh1_addr.bit.b2 /* Port P1_5 function select bit */ +#define p15sel1 pmh1_addr.bit.b3 /* Port P1_5 function select bit */ +#define p16sel0 pmh1_addr.bit.b4 /* Port P1_6 function select bit */ +#define p16sel1 pmh1_addr.bit.b5 /* Port P1_6 function select bit */ +#define p17sel0 pmh1_addr.bit.b6 /* Port P1_7 function select bit */ +#define p17sel1 pmh1_addr.bit.b7 /* Port P1_7 function select bit */ + +/*------------------------------------------------------ + Port 3 Function Mapping Register 0 +------------------------------------------------------*/ +union byte_def pml3_addr; +#define pml3 pml3_addr.byte + +#define p33sel0 pml3_addr.bit.b6 /* Port P3_3 function select bit */ +#define p33sel1 pml3_addr.bit.b7 /* Port P3_3 function select bit */ + +/*------------------------------------------------------ + Port 3 Function Mapping Register 1 +------------------------------------------------------*/ +union byte_def pmh3_addr; +#define pmh3 pmh3_addr.byte + +#define p34sel0 pmh3_addr.bit.b0 /* Port P3_4 function select bit */ +#define p34sel1 pmh3_addr.bit.b1 /* Port P3_4 function select bit */ +#define p35sel0 pmh3_addr.bit.b2 /* Port P3_5 function select bit */ +#define p35sel1 pmh3_addr.bit.b3 /* Port P3_5 function select bit */ +#define p37sel0 pmh3_addr.bit.b6 /* Port P3_7 function select bit */ +#define p37sel1 pmh3_addr.bit.b7 /* Port P3_7 function select bit */ + +/*------------------------------------------------------ + Port 4 Function Mapping Register 0 +------------------------------------------------------*/ +union byte_def pml4_addr; +#define pml4 pml4_addr.byte + +#define p42sel0 pml4_addr.bit.b4 /* Port P4_2 function select bit */ +#define p42sel1 pml4_addr.bit.b5 /* Port P4_2 function select bit */ + +/*------------------------------------------------------ + Port 4 Function Mapping Register 1 +------------------------------------------------------*/ +union byte_def pmh4_addr; +#define pmh4 pmh4_addr.byte + +#define p45sel0 pmh4_addr.bit.b2 /* Port P4_5 function select bit */ +#define p45sel1 pmh4_addr.bit.b3 /* Port P4_5 function select bit */ +#define p46sel0 pmh4_addr.bit.b4 /* Port P4_6 function select bit */ +#define p46sel1 pmh4_addr.bit.b5 /* Port P4_6 function select bit */ +#define p47sel0 pmh4_addr.bit.b6 /* Port P4_7 function select bit */ +#define p47sel1 pmh4_addr.bit.b7 /* Port P4_7 function select bit */ + +/*------------------------------------------------------ + Port 1 Function Mapping Expansion Register +------------------------------------------------------*/ +union byte_def pmh1e_addr; +#define pmh1e pmh1e_addr.byte + +#define p14sel2 pmh1e_addr.bit.b0 /* The P1_4 pin function is selected in conjunction with bits P14SEL0 to P14SEL1 in the PMH1 register */ +#define p15sel2 pmh1e_addr.bit.b2 /* The P1_5 pin function is selected in conjunction with bits P15SEL0 to P15SEL1 in the PMH1 register */ + +/*------------------------------------------------------ + Port 4 Function Mapping Expansion Register +------------------------------------------------------*/ +union byte_def pmh4e_addr; +#define pmh4e pmh4e_addr.byte + +#define p46sel2 pmh4e_addr.bit.b4 /* The P4_6 pin function is selected in conjunction with bits P46SEL0 to P46SEL1 in the PMH4 register */ + +/*------------------------------------------------------ + Timer RJ Counter Register / Timer RJ Reload Register +------------------------------------------------------*/ +union word_def trj_addr; +#define trj trj_addr.word /* Timer RJ Counter Register, Timer RJ Reload Register */ + +/*------------------------------------------------------ + Timer RJ Control Register +------------------------------------------------------*/ +union byte_def trjcr_addr; +#define trjcr trjcr_addr.byte + +#define tstart_trjcr trjcr_addr.bit.b0 /* Timer RJ count start bit */ +#define tcstf_trjcr trjcr_addr.bit.b1 /* Timer RJ count status flag */ +#define tstop_trjcr trjcr_addr.bit.b2 /* Timer RJ count forced stop bit */ +#define tedgf_trjcr trjcr_addr.bit.b4 /* Active edge judgment flag */ +#define tundf_trjcr trjcr_addr.bit.b5 /* Timer RJ underflow flag */ + +/*------------------------------------------------------ + Timer RJ I/O Control Register +------------------------------------------------------*/ +union byte_def trjioc_addr; +#define trjioc trjioc_addr.byte + +#define tedgsel_trjioc trjioc_addr.bit.b0 /* I/O polarity switch bit */ +#define topcr_trjioc trjioc_addr.bit.b1 /* TRJIO output control bit */ +#define tipf0_trjioc trjioc_addr.bit.b4 /* TRJIO input filter select bit */ +#define tipf1_trjioc trjioc_addr.bit.b5 /* TRJIO input filter select bit */ +#define tiogt0_trjioc trjioc_addr.bit.b6 /* TRJIO count control bit */ +#define tiogt1_trjioc trjioc_addr.bit.b7 /* TRJIO count control bit */ + +/*------------------------------------------------------ + Timer RJ Mode Register +------------------------------------------------------*/ +union byte_def trjmr_addr; +#define trjmr trjmr_addr.byte + +#define tmod0_trjmr trjmr_addr.bit.b0 /* Timer RJ operating mode select bit */ +#define tmod1_trjmr trjmr_addr.bit.b1 /* Timer RJ operating mode select bit */ +#define tmod2_trjmr trjmr_addr.bit.b2 /* Timer RJ operating mode select bit */ +#define tedgpl_trjmr trjmr_addr.bit.b3 /* TRJIO edge polarity select bit */ +#define tck0_trjmr trjmr_addr.bit.b4 /* Timer RJ count source select bit */ +#define tck1_trjmr trjmr_addr.bit.b5 /* Timer RJ count source select bit */ +#define tck2_trjmr trjmr_addr.bit.b6 /* Timer RJ count source select bit */ +#define tckcut_trjmr trjmr_addr.bit.b7 /* Timer RJ count source cutoff bit */ + +/*------------------------------------------------------ + Timer RJ Event Select Register +------------------------------------------------------*/ +union byte_def trjisr_addr; +#define trjisr trjisr_addr.byte + +#define rccpsel0_trjisr trjisr_addr.bit.b0 /* Timer RC output signal select bit */ +#define rccpsel1_trjisr trjisr_addr.bit.b1 /* Timer RC output signal select bit */ +#define rccpsel2_trjisr trjisr_addr.bit.b2 /* Timer RC output signal inversion bit */ + +/*------------------------------------------------------ + Timer RJ Interrupt Control Register +------------------------------------------------------*/ +union byte_def trjir_addr; +#define trjir trjir_addr.byte + +#define trjif_trjir trjir_addr.bit.b6 /* Timer RJ interrupt request flag */ +#define trjie_trjir trjir_addr.bit.b7 /* Timer RJ interrupt enable bit */ + +/*------------------------------------------------------ + Timer RB Control Register +------------------------------------------------------*/ +union byte_def trbcr_addr; +#define trbcr trbcr_addr.byte + +#define tstart_trbcr trbcr_addr.bit.b0 /* Timer RB count start bit */ +#define tcstf_trbcr trbcr_addr.bit.b1 /* Timer RB count status flag */ +#define tstop_trbcr trbcr_addr.bit.b2 /* Timer RB count forced stop bit */ + +/*------------------------------------------------------ + Timer RB One-Shot Control Register +------------------------------------------------------*/ +union byte_def trbocr_addr; +#define trbocr trbocr_addr.byte + +#define tosst_trbocr trbocr_addr.bit.b0 /* Timer RB one-shot start bit */ +#define tossp_trbocr trbocr_addr.bit.b1 /* Timer RB one-shot stop bit */ +#define tosstf_trbocr trbocr_addr.bit.b2 /* Timer RB one-shot status flag */ + +/*------------------------------------------------------ + Timer RB I/O Control Register +------------------------------------------------------*/ +union byte_def trbioc_addr; +#define trbioc trbioc_addr.byte + +#define topl_trbioc trbioc_addr.bit.b0 /* Timer RB output level select bit */ +#define tocnt_trbioc trbioc_addr.bit.b1 /* Timer RB output switch bit */ +#define inostg_trbioc trbioc_addr.bit.b2 /* One-shot trigger control bit */ +#define inoseg_trbioc trbioc_addr.bit.b3 /* One-shot trigger polarity select bit */ + +/*------------------------------------------------------ + Timer RB Mode Register +------------------------------------------------------*/ +union byte_def trbmr_addr; +#define trbmr trbmr_addr.byte + +#define tmod0_trbmr trbmr_addr.bit.b0 /* Timer RB operating mode select bit */ +#define tmod1_trbmr trbmr_addr.bit.b1 /* Timer RB operating mode select bit */ +#define tcnt16_trbmr trbmr_addr.bit.b2 /* Timer RB counter select bit */ +#define twrc_trbmr trbmr_addr.bit.b3 /* Timer RB write control bit */ +#define tck0_trbmr trbmr_addr.bit.b4 /* Timer RB count source select bit */ +#define tck1_trbmr trbmr_addr.bit.b5 /* Timer RB count source select bit */ +#define tck2_trbmr trbmr_addr.bit.b6 /* Timer RB count source select bit */ +#define tckcut_trbmr trbmr_addr.bit.b7 /* Timer RB count source cutoff bit */ + +/*------------------------------------------------------ + Timer RB Prescaler Register +------------------------------------------------------*/ +union byte_def trbpre_addr; +#define trbpre trbpre_addr.byte + +/*------------------------------------------------------ + Timer RB Primary Register +------------------------------------------------------*/ +union byte_def trbpr_addr; +#define trbpr trbpr_addr.byte + +/*------------------------------------------------------ + Timer RB Secondary Register +------------------------------------------------------*/ +union byte_def trbsc_addr; +#define trbsc trbsc_addr.byte + +/*------------------------------------------------------ + Timer RB Interrupt Control Register +------------------------------------------------------*/ +union byte_def trbir_addr; +#define trbir trbir_addr.byte + +#define trbif_trbir trbir_addr.bit.b6 /* Timer RB interrupt request flag */ +#define trbie_trbir trbir_addr.bit.b7 /* Timer RB interrupt enable bit */ + +/*------------------------------------------------------ + Timer RC Counter, General Register A,B,C,D +------------------------------------------------------*/ +union word_def trccnt_addr; +#define trccnt trccnt_addr.word /* Timer RC Counter */ + +union word_def trcgra_addr; +#define trcgra trcgra_addr.word /* Timer RC General Register A */ + +union word_def trcgrb_addr; +#define trcgrb trcgrb_addr.word /* Timer RC General Register B */ + +union word_def trcgrc_addr; +#define trcgrc trcgrc_addr.word /* Timer RC General Register C */ + +union word_def trcgrd_addr; +#define trcgrd trcgrd_addr.word /* Timer RC General Register D */ + +/*------------------------------------------------------ + Timer RC Mode Register +------------------------------------------------------*/ +union byte_def trcmr_addr; +#define trcmr trcmr_addr.byte + +#define pwmb_trcmr trcmr_addr.bit.b0 /* TRCIOB PWM mode select bit */ +#define pwmc_trcmr trcmr_addr.bit.b1 /* TRCIOC PWM mode select bit */ +#define pwmd_trcmr trcmr_addr.bit.b2 /* TRCIOD PWM mode select bit */ +#define pwm2_trcmr trcmr_addr.bit.b3 /* PWM2 mode select bit */ +#define bufea_trcmr trcmr_addr.bit.b4 /* TRCGRC register function select bit */ +#define bufeb_trcmr trcmr_addr.bit.b5 /* TRCGRD register function select bit */ +#define cts_trcmr trcmr_addr.bit.b7 /* TRCCNT count start bit */ + +/*------------------------------------------------------ + Timer RC Control Register 1 +------------------------------------------------------*/ +union byte_def trccr1_addr; +#define trccr1 trccr1_addr.byte + +#define toa_trccr1 trccr1_addr.bit.b0 /* Timer output level select A bit */ +#define tob_trccr1 trccr1_addr.bit.b1 /* Timer output level select B bit */ +#define toc_trccr1 trccr1_addr.bit.b2 /* Timer output level select C bit */ +#define tod_trccr1 trccr1_addr.bit.b3 /* Timer output level select D bit */ +#define cks0_trccr1 trccr1_addr.bit.b4 /* Count source select bit */ +#define cks1_trccr1 trccr1_addr.bit.b5 /* Count source select bit */ +#define cks2_trccr1 trccr1_addr.bit.b6 /* Count source select bit */ +#define cclr_trccr1 trccr1_addr.bit.b7 /* TRCCNT counter clear select bit */ + +/*------------------------------------------------------ + Timer RC Interrupt Enable Register +------------------------------------------------------*/ +union byte_def trcier_addr; +#define trcier trcier_addr.byte + +#define imiea_trcier trcier_addr.bit.b0 /* Input capture/compare match A interrupt enable bit */ +#define imieb_trcier trcier_addr.bit.b1 /* Input capture/compare match B interrupt enable bit */ +#define imiec_trcier trcier_addr.bit.b2 /* Input capture/compare match C interrupt enable bit */ +#define imied_trcier trcier_addr.bit.b3 /* Input capture/compare match D interrupt enable bit */ +#define ovie_trcier trcier_addr.bit.b7 /* Timer overflow interrupt enable bit */ + +/*------------------------------------------------------ + Timer RC Status Register +------------------------------------------------------*/ +union byte_def trcsr_addr; +#define trcsr trcsr_addr.byte + +#define imfa_trcsr trcsr_addr.bit.b0 /* Input capture/compare match A flag */ +#define imfb_trcsr trcsr_addr.bit.b1 /* Input capture/compare match B flag */ +#define imfc_trcsr trcsr_addr.bit.b2 /* Input capture/compare match C flag */ +#define imfd_trcsr trcsr_addr.bit.b3 /* Input capture/compare match D flag */ +#define ovf_trcsr trcsr_addr.bit.b7 /* Timer overflow flag */ + +/*------------------------------------------------------ + Timer RC I/O Control Register 0 +------------------------------------------------------*/ +union byte_def trcior0_addr; +#define trcior0 trcior0_addr.byte + +#define ioa0_trcior0 trcior0_addr.bit.b0 /* TRCGRA control A0 bit */ +#define ioa1_trcior0 trcior0_addr.bit.b1 /* TRCGRA control A1 bit */ +#define ioa2_trcior0 trcior0_addr.bit.b2 /* TRCGRA control A2 bit */ +#define iob0_trcior0 trcior0_addr.bit.b4 /* TRCGRB control B0 bit */ +#define iob1_trcior0 trcior0_addr.bit.b5 /* TRCGRB control B1 bit */ +#define iob2_trcior0 trcior0_addr.bit.b6 /* TRCGRB control B2 bit */ + +/*------------------------------------------------------ + Timer RC I/O Control Register 1 +------------------------------------------------------*/ +union byte_def trcior1_addr; +#define trcior1 trcior1_addr.byte + +#define ioc0_trcior1 trcior1_addr.bit.b0 /* TRCGRC control C0 bit */ +#define ioc1_trcior1 trcior1_addr.bit.b1 /* TRCGRC control C1 bit */ +#define ioc2_trcior1 trcior1_addr.bit.b2 /* TRCGRC control C2 bit */ +#define ioc3_trcior1 trcior1_addr.bit.b3 /* TRCGRC control C3 bit */ +#define iod0_trcior1 trcior1_addr.bit.b4 /* TRCGRD control D0 bit */ +#define iod1_trcior1 trcior1_addr.bit.b5 /* TRCGRD control D1 bit */ +#define iod2_trcior1 trcior1_addr.bit.b6 /* TRCGRD control D2 bit */ +#define iod3_trcior1 trcior1_addr.bit.b7 /* TRCGRD control D3 bit */ + +/*------------------------------------------------------ + Timer RC Control Register 2 +------------------------------------------------------*/ +union byte_def trccr2_addr; +#define trccr2 trccr2_addr.byte + +#define polb_trccr2 trccr2_addr.bit.b0 /* TRCIOB PWM mode output level control bit */ +#define polc_trccr2 trccr2_addr.bit.b1 /* TRCIOC PWM mode output level control bit */ +#define pold_trccr2 trccr2_addr.bit.b2 /* TRCIOD PWM mode output level control bit */ +#define cstp_trccr2 trccr2_addr.bit.b5 /* Count stop bit */ +#define tceg0_trccr2 trccr2_addr.bit.b6 /* TRCTRG input edge select bit */ +#define tceg1_trccr2 trccr2_addr.bit.b7 /* TRCTRG input edge select bit */ + +/*------------------------------------------------------ + Timer RC Digital Filter Function Select Register +------------------------------------------------------*/ +union byte_def trcdf_addr; +#define trcdf trcdf_addr.byte + +#define dfa_trcdf trcdf_addr.bit.b0 /* TRCIOA digital filter function bit */ +#define dfb_trcdf trcdf_addr.bit.b1 /* TRCIOB digital filter function bit */ +#define dfc_trcdf trcdf_addr.bit.b2 /* TRCIOC digital filter function bit */ +#define dfd_trcdf trcdf_addr.bit.b3 /* TRCIOD digital filter function bit */ +#define dftrg_trcdf trcdf_addr.bit.b4 /* TRCTRG digital filter function bit */ +#define dfck0_trcdf trcdf_addr.bit.b6 /* Digital filter clock select bit */ +#define dfck1_trcdf trcdf_addr.bit.b7 /* Digital filter clock select bit */ + +/*------------------------------------------------------ + Timer RC Output Enable Register +------------------------------------------------------*/ +union byte_def trcoer_addr; +#define trcoer trcoer_addr.byte + +#define ea_trcoer trcoer_addr.bit.b0 /* TRCIOA output disable bit */ +#define eb_trcoer trcoer_addr.bit.b1 /* TRCIOB output disable bit */ +#define ec_trcoer trcoer_addr.bit.b2 /* TRCIOC output disable bit */ +#define ed_trcoer trcoer_addr.bit.b3 /* TRCIOD output disable bit */ +#define pto_trcoer trcoer_addr.bit.b7 /* Timer output disable bit */ + +/*------------------------------------------------------ + Timer RC A/D Conversion Trigger Control Register +------------------------------------------------------*/ +union byte_def trcadcr_addr; +#define trcadcr trcadcr_addr.byte + +#define adtrgae_trcadcr trcadcr_addr.bit.b0 /* TRCGRA A/D conversion start trigger enable bit */ +#define adtrgbe_trcadcr trcadcr_addr.bit.b1 /* TRCGRB A/D conversion start trigger enable bit */ +#define adtrgce_trcadcr trcadcr_addr.bit.b2 /* TRCGRC A/D conversion start trigger enable bit */ +#define adtrgde_trcadcr trcadcr_addr.bit.b3 /* TRCGRD A/D conversion start trigger enable bit */ + +/*------------------------------------------------------ + Timer RC Waveform Output Manipulation Register +------------------------------------------------------*/ +union byte_def trcopr_addr; +#define trcopr trcopr_addr.byte + +#define opsel0_trcopr trcopr_addr.bit.b0 /* Waveform output manipulation event select bit */ +#define opsel1_trcopr trcopr_addr.bit.b1 /* Waveform output manipulation event select bit */ +#define opol0_trcopr trcopr_addr.bit.b2 /* Waveform output manipulation period output level select bit */ +#define opol1_trcopr trcopr_addr.bit.b3 /* Waveform output manipulation period output level select bit */ +#define restats_trcopr trcopr_addr.bit.b4 /* Restart method select bit */ +#define ope_trcopr trcopr_addr.bit.b5 /* Waveform output manipulation enable bit */ + +/*------------------------------------------------------ + Comparator B Control Register 0 +------------------------------------------------------*/ +union byte_def wcmpr_addr; +#define wcmpr wcmpr_addr.byte + +#define wcb1m0 wcmpr_addr.bit.b0 /* Comparator B1 operation enable bit */ +#define wcb1out wcmpr_addr.bit.b3 /* Comparator B1 monitor flag */ +#define wcb3m0 wcmpr_addr.bit.b4 /* Comparator B3 operation enable bit */ +#define wcb3out wcmpr_addr.bit.b7 /* Comparator B3 monitor flag */ + +/*------------------------------------------------------ + Comparator B1 Interrupt Control Register +------------------------------------------------------*/ +union byte_def wcb1intr_addr; +#define wcb1intr wcb1intr_addr.byte + +#define wcb1f0 wcb1intr_addr.bit.b0 /* Comparator B1 filter select bit */ +#define wcb1f1 wcb1intr_addr.bit.b1 /* Comparator B1 filter select bit */ +#define wcb1s0 wcb1intr_addr.bit.b4 /* Comparator B1 interrupt edge select bit */ +#define wcb1s1 wcb1intr_addr.bit.b5 /* Comparator B1 interrupt edge select bit */ +#define wcb1inten wcb1intr_addr.bit.b6 /* Comparator B1 interrupt enable signal bit */ +#define wcb1f wcb1intr_addr.bit.b7 /* Comparator B1 interrupt request flag */ + +/*------------------------------------------------------ + Comparator B3 Interrupt Control Register +------------------------------------------------------*/ +union byte_def wcb3intr_addr; +#define wcb3intr wcb3intr_addr.byte + +#define wcb3f0 wcb3intr_addr.bit.b0 /* Comparator B3 filter select bit */ +#define wcb3f1 wcb3intr_addr.bit.b1 /* Comparator B3 filter select bit */ +#define wcb3s0 wcb3intr_addr.bit.b4 /* Comparator B3 interrupt edge select bit */ +#define wcb3s1 wcb3intr_addr.bit.b5 /* Comparator B3 interrupt edge select bit */ +#define wcb3inten wcb3intr_addr.bit.b6 /* Comparator B3 interrupt enable signal bit */ +#define wcb3f wcb3intr_addr.bit.b7 /* Comparator B3 interrupt request flag */ + +/*------------------------------------------------------ + Flash Memory Status Register +------------------------------------------------------*/ +union byte_def fst_addr; +#define fst fst_addr.byte + +#define rdysti fst_addr.bit.b0 /* Flash ready status interrupt request flag */ +#define bsyaei fst_addr.bit.b1 /* Flash access error interrupt request flag */ +#define fst2 fst_addr.bit.b2 /* LBDATA monitor flag */ +#define fst3 fst_addr.bit.b3 /* Program-suspend status flag */ +#define fst4 fst_addr.bit.b4 /* Program error status flag */ +#define fst5 fst_addr.bit.b5 /* Erase error/blank check error status flag */ +#define fst6 fst_addr.bit.b6 /* Erase-suspend status flag */ +#define fst7 fst_addr.bit.b7 /* Ready/busy status flag */ + +/*------------------------------------------------------ + Flash Memory Control Register 0 +------------------------------------------------------*/ +union byte_def fmr0_addr; +#define fmr0 fmr0_addr.byte + +#define fmr01 fmr0_addr.bit.b1 /* CPU rewrite mode select bit */ +#define fmr02 fmr0_addr.bit.b2 /* EW1 mode select bit */ +#define fmstp fmr0_addr.bit.b3 /* Flash memory stop bit */ +#define cmdrst fmr0_addr.bit.b4 /* Erase/write sequence reset bit */ +#define cmderie fmr0_addr.bit.b5 /* Erase/write error, blank check error, command error interrupt enable bit */ +#define bsyaeie fmr0_addr.bit.b6 /* Flash access error interrupt enable bit */ +#define rdystie fmr0_addr.bit.b7 /* Flash ready status interrupt enable bit */ + +/*------------------------------------------------------ + Flash Memory Control Register 1 +------------------------------------------------------*/ +union byte_def fmr1_addr; +#define fmr1 fmr1_addr.byte + +#define wtfmstp fmr1_addr.bit.b2 /* Flash memory stop bit in wait mode */ +#define fmr13 fmr1_addr.bit.b3 /* Lock bit disable select bit */ +#define fmr16 fmr1_addr.bit.b6 /* Data flash block A rewrite disable bit */ +#define fmr17 fmr1_addr.bit.b7 /* Data flash block B rewrite disable bit */ + +/*------------------------------------------------------ + Flash Memory Control Register 2 +------------------------------------------------------*/ +union byte_def fmr2_addr; +#define fmr2 fmr2_addr.byte + +#define fmr20 fmr2_addr.bit.b0 /* Suspend enable bit */ +#define fmr21 fmr2_addr.bit.b1 /* Suspend request bit */ +#define fmr22 fmr2_addr.bit.b2 /* Interrupt request suspend request enable bit */ +#define fmr27 fmr2_addr.bit.b7 /* Low-current-consumption read mode enable bit */ + +/*------------------------------------------------------ + Flash Memory Refresh Control Register +------------------------------------------------------*/ +union byte_def frefr_addr; +#define frefr frefr_addr.byte + +#define ref0 frefr_addr.bit.b0 /* Periodic refresh interval control bit */ +#define ref1 frefr_addr.bit.b1 /* Periodic refresh interval control bit */ +#define ref2 frefr_addr.bit.b2 /* Periodic refresh interval control bit */ +#define ref3 frefr_addr.bit.b3 /* Periodic refresh interval control bit */ +#define ref4 frefr_addr.bit.b4 /* Periodic refresh interval control bit */ +#define ref5 frefr_addr.bit.b5 /* Periodic refresh interval control bit */ + +/*------------------------------------------------------ + Address Match Interrupt Register 0 +------------------------------------------------------*/ +union dword_def aiadr0_addr; +#define aiadr0 aiadr0_addr.dword /* Address Match Interrupt Register 0 */ + +#define aiadr0l aiadr0_addr.byte.low /* Address Match Interrupt Register 0 Low */ +#define aiadr0m aiadr0_addr.byte.mid /* Address Match Interrupt Register 0 Middle */ +#define aiadr0h aiadr0_addr.byte.high /* Address Match Interrupt Register 0 High */ + +/*------------------------------------------------------ + Address Match Interrupt Enable Register 0 +------------------------------------------------------*/ +union byte_def aien0_addr; +#define aien0 aien0_addr.byte + +#define aien00 aien0_addr.bit.b0 /* Address match interrupt enable 0 bit */ + +/*------------------------------------------------------ + Address Match Interrupt Register 1 +------------------------------------------------------*/ +union dword_def aiadr1_addr; +#define aiadr1 aiadr1_addr.dword /* Address Match Interrupt Register 1 */ + +#define aiadr1l aiadr1_addr.byte.low /* Address Match Interrupt Register 1 Low */ +#define aiadr1m aiadr1_addr.byte.mid /* Address Match Interrupt Register 1 Middle */ +#define aiadr1h aiadr1_addr.byte.high /* Address Match Interrupt Register 1 High */ + +/*------------------------------------------------------ + Address Match Interrupt Enable Register 1 +------------------------------------------------------*/ +union byte_def aien1_addr; +#define aien1 aien1_addr.byte + +#define aien10 aien1_addr.bit.b0 /* Address match interrupt enable 1 bit */ + + diff --git a/src.original/sfr_r8m12a.inc b/src.original/sfr_r8m12a.inc new file mode 100644 index 0000000..8f71ecc --- /dev/null +++ b/src.original/sfr_r8m12a.inc @@ -0,0 +1,1286 @@ +;------------------------------------------------------------------------ +; | +; | +; | +; DESCRIPTION :define the sfr register. (for Assembler language) | +; | +; | +; This file is generated by Renesas Project Generator. | +; | +;------------------------------------------------------------------------ +;/*********************************************************************** +;* +;* Device : R8C/M12A +;* +;* File Name : sfr_r8m12a.inc +;* +;* Abstract : definition of R8C/M12A Group SFR +;* +;* History : 2.00 ( 2010-12-03 ) [User's Manual: Hardware Rev.1.00] +;* : 1.10 ( 2010-06-24 ) [User's Manual: Hardware Rev.0.10] +;* : 1.00 ( 2010-02-26 ) [User's Manual: Hardware Rev.0.01] +;* +;* NOTE : THIS IS A TYPICAL EXAMPLE. +;* +;* Copyright (C) 2010 Renesas Electronics Corporation. +;* and Renesas Solutions Corp. +;* +;************************************************************************/ +; +;------------------------------------------------------- +; Processor Mode Register 0 +;------------------------------------------------------- +pm0 .equ 0010h +; +srst .btequ 3,pm0 ; Software reset bit +; +;------------------------------------------------------- +; Module Standby Control Register +;------------------------------------------------------- +mstcr .equ 0012h +; +msttrj .btequ 0,mstcr ; Timer RJ2 standby bit +msttrb .btequ 1,mstcr ; Timer RB2 standby bit +mstad .btequ 4,mstcr ; A/D converter standby bit +msttrc .btequ 5,mstcr ; Timer RC standby bit +mstuart .btequ 6,mstcr ; UART0 standby bit +; +;------------------------------------------------------- +; Protect Register +;------------------------------------------------------- +prcr .equ 0013h +; +prc0 .btequ 0,prcr ; Protect bit 0 +prc1 .btequ 1,prcr ; Protect bit 1 +prc3 .btequ 3,prcr ; Protect bit 3 +prc4 .btequ 4,prcr ; Protect bit 4 +; +;------------------------------------------------------- +; Hardware Reset Protect Register +;------------------------------------------------------- +hrpr .equ 0016h +; +pamcre .btequ 0,hrpr ; PAMCR register write enable bit +; +;------------------------------------------------------- +; External Clock Control Register +;------------------------------------------------------- +exckcr .equ 0020h +; +ckpt0 .btequ 0,exckcr ; P4_6 and P4_7 pin function select bit +ckpt1 .btequ 1,exckcr ; P4_6 and P4_7 pin function select bit +xrcut .btequ 6,exckcr ; XIN-XOUT on-chip feedback resistor select bit +; +;------------------------------------------------------- +; High-Speed/Low-Speed On-Chip Oscillator Control Register +;------------------------------------------------------- +ococr .equ 0021h +; +hocoe .btequ 0,ococr ; High-speed on-chip oscillator oscillation enable bit +locodis .btequ 1,ococr ; Low-speed on-chip oscillator oscillation stop bit +; +;------------------------------------------------------- +; System Clock f Control Register +;------------------------------------------------------- +sckcr .equ 0022h +; +phissel0 .btequ 0,sckcr ; CPU clock division ratio select bit +phissel1 .btequ 1,sckcr ; CPU clock division ratio select bit +phissel2 .btequ 2,sckcr ; CPU clock division ratio select bit +waitm .btequ 5,sckcr ; Wait control bit +hscksel .btequ 6,sckcr ; High-speed on-chip oscillator/XIN clock select bit +; +;------------------------------------------------------- +; System Clock f Select Register +;------------------------------------------------------- +phisel .equ 0023h +; +phisel0 .btequ 0,phisel ; System clock division select bit select bit +phisel1 .btequ 1,phisel ; System clock division select bit select bit +phisel2 .btequ 2,phisel ; System clock division select bit select bit +phisel3 .btequ 3,phisel ; System clock division select bit select bit +phisel4 .btequ 4,phisel ; System clock division select bit select bit +phisel5 .btequ 5,phisel ; System clock division select bit select bit +phisel6 .btequ 6,phisel ; System clock division select bit select bit +phisel7 .btequ 7,phisel ; System clock division select bit select bit +; +;------------------------------------------------------- +; Clock Stop Control Register +;------------------------------------------------------- +ckstpr .equ 0024h +; +stpm .btequ 0,ckstpr ; All clock stop control bit +wckstp .btequ 1,ckstpr ; fBASE stop bit in wait mode +pscstp .btequ 2,ckstpr ; Prescaler stop bit +scksel .btequ 7,ckstpr ; System base clock select bit +; +;------------------------------------------------------- +; Clock Control Register When Returning from Modes +;------------------------------------------------------- +ckrscr .equ 0025h +; +ckst0 .btequ 0,ckrscr ; Clock oscillator circuit oscillation stabilization state select bit +ckst1 .btequ 1,ckrscr ; Clock oscillator circuit oscillation stabilization state select bit +ckst2 .btequ 2,ckrscr ; Clock oscillator circuit oscillation stabilization state select bit +ckst3 .btequ 3,ckrscr ; Clock oscillator circuit oscillation stabilization state select bit +phisrs .btequ 5,ckrscr ; CPU clock division select bit when returning from wait mode or stop mode +waitrs .btequ 6,ckrscr ; System base clock select bit when returning from wait mode +stoprs .btequ 7,ckrscr ; System base clock select bit when returning from stop mode +; +;------------------------------------------------------- +; Oscillation Stop Detection Register +;------------------------------------------------------- +bakcr .equ 0026h +; +xinbake .btequ 0,bakcr ; Oscillation stop detection enable bit +ckswie .btequ 1,bakcr ; Oscillation stop detection interrupt enable bit +xinhalt .btequ 2,bakcr ; Clock monitor bit +ckswif .btequ 3,bakcr ; Oscillation stop detection interrupt request flag +; +;------------------------------------------------------- +; Watchdog Timer Function Register +;------------------------------------------------------- +risr .equ 0030h +; +ufif .btequ 6,risr ; WDT underflow detection flag +ris .btequ 7,risr ; WDT interrupt/reset switch bit +; +;------------------------------------------------------- +; Watchdog Timer Reset Register +;------------------------------------------------------- +wdtr .equ 0031h +; +;------------------------------------------------------- +; Watchdog Timer Start Register +;------------------------------------------------------- +wdts .equ 0032h +; +;------------------------------------------------------- +; Watchdog Timer Control Register +;------------------------------------------------------- +wdtc .equ 0033h +; +wdtc6 .btequ 6,wdtc ; Watchdog timer count source select bit +wdtc7 .btequ 7,wdtc ; Watchdog timer count source select bit +; +;------------------------------------------------------- +; Count Source Protection Mode Register +;------------------------------------------------------- +cspr .equ 0034h +; +cspro .btequ 7,cspr ; Count source protection mode select bit +; +;------------------------------------------------------- +; Periodic Timer Interrupt Control Register +;------------------------------------------------------- +wdtir .equ 0035h +; +wdtif .btequ 6,wdtir ; Periodic timer interrupt request flag +wdtie .btequ 7,wdtir ; Periodic timer interrupt enable bit +; +;------------------------------------------------------- +; External Input Enable Register +;------------------------------------------------------- +inten .equ 0038h +; +int0en .btequ 0,inten ; INT0 input enable bit +int1en .btequ 1,inten ; INT1 input enable bit +int2en .btequ 2,inten ; INT2 input enable bit +int3en .btequ 3,inten ; INT3 input enable bit +; +;------------------------------------------------------- +; INT Input Filter Select Register 0 +;------------------------------------------------------- +intf0 .equ 003Ah +; +int0f0 .btequ 0,intf0 ; INT0 input filter select bit +int0f1 .btequ 1,intf0 ; INT0 input filter select bit +int1f0 .btequ 2,intf0 ; INT1 input filter select bit +int1f1 .btequ 3,intf0 ; INT1 input filter select bit +int2f0 .btequ 4,intf0 ; INT2 input filter select bit +int2f1 .btequ 5,intf0 ; INT2 input filter select bit +int3f0 .btequ 6,intf0 ; INT3 input filter select bit +int3f1 .btequ 7,intf0 ; INT3 input filter select bit +; +;------------------------------------------------------- +; INT Input Edge Select Register 0 +;------------------------------------------------------- +iscr0 .equ 003Ch +; +int0sa .btequ 0,iscr0 ; INT0 input edge select bit +int0sb .btequ 1,iscr0 ; INT0 input edge select bit +int1sa .btequ 2,iscr0 ; INT1 input edge select bit +int1sb .btequ 3,iscr0 ; INT1 input edge select bit +int2sa .btequ 4,iscr0 ; INT2 input edge select bit +int2sb .btequ 5,iscr0 ; INT2 input edge select bit +int3sa .btequ 6,iscr0 ; INT3 input edge select bit +int3sb .btequ 7,iscr0 ; INT3 input edge select bit +; +;------------------------------------------------------- +; Key Input Enable Register +;------------------------------------------------------- +kien .equ 003Eh +; +ki0en .btequ 0,kien ; KI0 input enable bit +ki0pl .btequ 1,kien ; KI0 input edge select bit +ki1en .btequ 2,kien ; KI1 input enable bit +ki1pl .btequ 3,kien ; KI1 input edge select bit +ki2en .btequ 4,kien ; KI2 input enable bit +ki2pl .btequ 5,kien ; KI2 input edge select bit +ki3en .btequ 6,kien ; KI3 input enable bit +ki3pl .btequ 7,kien ; KI3 input edge select bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 0 +;------------------------------------------------------- +ilvl0 .equ 0040h +; +ilvl00 .btequ 0,ilvl0 ; Interrupt priority level setting bit +ilvl01 .btequ 1,ilvl0 ; Interrupt priority level setting bit +ilvl04 .btequ 4,ilvl0 ; Interrupt priority level setting bit +ilvl05 .btequ 5,ilvl0 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 2 +;------------------------------------------------------- +ilvl2 .equ 0042h +; +ilvl20 .btequ 0,ilvl2 ; Interrupt priority level setting bit +ilvl21 .btequ 1,ilvl2 ; Interrupt priority level setting bit +ilvl24 .btequ 4,ilvl2 ; Interrupt priority level setting bit +ilvl25 .btequ 5,ilvl2 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 3 +;------------------------------------------------------- +ilvl3 .equ 0043h +; +ilvl30 .btequ 0,ilvl3 ; Interrupt priority level setting bit +ilvl31 .btequ 1,ilvl3 ; Interrupt priority level setting bit +ilvl34 .btequ 4,ilvl3 ; Interrupt priority level setting bit +ilvl35 .btequ 5,ilvl3 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 4 +;------------------------------------------------------- +ilvl4 .equ 0044h +; +ilvl40 .btequ 0,ilvl4 ; Interrupt priority level setting bit +ilvl41 .btequ 1,ilvl4 ; Interrupt priority level setting bit +ilvl44 .btequ 4,ilvl4 ; Interrupt priority level setting bit +ilvl45 .btequ 5,ilvl4 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 5 +;------------------------------------------------------- +ilvl5 .equ 0045h +; +ilvl50 .btequ 0,ilvl5 ; Interrupt priority level setting bit +ilvl51 .btequ 1,ilvl5 ; Interrupt priority level setting bit +ilvl54 .btequ 4,ilvl5 ; Interrupt priority level setting bit +ilvl55 .btequ 5,ilvl5 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 6 +;------------------------------------------------------- +ilvl6 .equ 0046h +; +ilvl60 .btequ 0,ilvl6 ; Interrupt priority level setting bit +ilvl61 .btequ 1,ilvl6 ; Interrupt priority level setting bit +ilvl64 .btequ 4,ilvl6 ; Interrupt priority level setting bit +ilvl65 .btequ 5,ilvl6 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 7 +;------------------------------------------------------- +ilvl7 .equ 0047h +; +ilvl70 .btequ 0,ilvl7 ; Interrupt priority level setting bit +ilvl71 .btequ 1,ilvl7 ; Interrupt priority level setting bit +ilvl74 .btequ 4,ilvl7 ; Interrupt priority level setting bit +ilvl75 .btequ 5,ilvl7 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 8 +;------------------------------------------------------- +ilvl8 .equ 0048h +; +ilvl80 .btequ 0,ilvl8 ; Interrupt priority level setting bit +ilvl81 .btequ 1,ilvl8 ; Interrupt priority level setting bit +ilvl84 .btequ 4,ilvl8 ; Interrupt priority level setting bit +ilvl85 .btequ 5,ilvl8 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register 9 +;------------------------------------------------------- +ilvl9 .equ 0049h +; +ilvl90 .btequ 0,ilvl9 ; Interrupt priority level setting bit +ilvl91 .btequ 1,ilvl9 ; Interrupt priority level setting bit +ilvl94 .btequ 4,ilvl9 ; Interrupt priority level setting bit +ilvl95 .btequ 5,ilvl9 ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register A +;------------------------------------------------------- +ilvla .equ 004Ah +; +ilvla0 .btequ 0,ilvla ; Interrupt priority level setting bit +ilvla1 .btequ 1,ilvla ; Interrupt priority level setting bit +ilvla4 .btequ 4,ilvla ; Interrupt priority level setting bit +ilvla5 .btequ 5,ilvla ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register B +;------------------------------------------------------- +ilvlb .equ 004Bh +; +ilvlb0 .btequ 0,ilvlb ; Interrupt priority level setting bit +ilvlb1 .btequ 1,ilvlb ; Interrupt priority level setting bit +ilvlb4 .btequ 4,ilvlb ; Interrupt priority level setting bit +ilvlb5 .btequ 5,ilvlb ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register C +;------------------------------------------------------- +ilvlc .equ 004Ch +; +ilvlc0 .btequ 0,ilvlc ; Interrupt priority level setting bit +ilvlc1 .btequ 1,ilvlc ; Interrupt priority level setting bit +ilvlc4 .btequ 4,ilvlc ; Interrupt priority level setting bit +ilvlc5 .btequ 5,ilvlc ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register D +;------------------------------------------------------- +ilvld .equ 004Dh +; +ilvld0 .btequ 0,ilvld ; Interrupt priority level setting bit +ilvld1 .btequ 1,ilvld ; Interrupt priority level setting bit +ilvld4 .btequ 4,ilvld ; Interrupt priority level setting bit +ilvld5 .btequ 5,ilvld ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Priority Level Register E +;------------------------------------------------------- +ilvle .equ 004Eh +; +ilvle0 .btequ 0,ilvle ; Interrupt priority level setting bit +ilvle1 .btequ 1,ilvle ; Interrupt priority level setting bit +ilvle4 .btequ 4,ilvle ; Interrupt priority level setting bit +ilvle5 .btequ 5,ilvle ; Interrupt priority level setting bit +; +;------------------------------------------------------- +; Interrupt Monitor Flag Register 0 +;------------------------------------------------------- +irr0 .equ 0050h +; +irtj .btequ 0,irr0 ; Timer RJ2 interrupt request monitor flag +irtb .btequ 1,irr0 ; Timer RB2 interrupt request monitor flag +irtc .btequ 2,irr0 ; Timer RC interrupt request monitor flag +irs0t .btequ 4,irr0 ; UART0 transmit interrupt request monitor flag +irs0r .btequ 5,irr0 ; UART0 receive interrupt request monitor flag +; +;------------------------------------------------------- +; Interrupt Monitor Flag Register 1 +;------------------------------------------------------- +irr1 .equ 0051h +; +irad .btequ 2,irr1 ; A/D conversion interrupt request monitor flag +irfm .btequ 4,irr1 ; Flash ready interrupt request monitor flag +irwd .btequ 5,irr1 ; Periodic timer interrupt request monitor flag +; +;------------------------------------------------------- +; Interrupt Monitor Flag Register 2 +;------------------------------------------------------- +irr2 .equ 0052h +; +ircmp1 .btequ 2,irr2 ; Comparator B1 interrupt request monitor flag +ircmp3 .btequ 3,irr2 ; Comparator B3 interrupt request monitor flag +; +;------------------------------------------------------- +; External Interrupt Flag Register +;------------------------------------------------------- +irr3 .equ 0053h +; +iri0 .btequ 0,irr3 ; INT0 interrupt request flag +iri1 .btequ 1,irr3 ; INT1 interrupt request flag +iri2 .btequ 2,irr3 ; INT2 interrupt request flag +iri3 .btequ 3,irr3 ; INT3 interrupt request flag +irki .btequ 5,irr3 ; Key input interrupt request flag +; +;------------------------------------------------------- +; Voltage Monitor Circuit Edge Select Register +;------------------------------------------------------- +vcac .equ 0058h +; +vcac1 .btequ 1,vcac ; Voltage monitor 1 circuit edge select bit +; +;------------------------------------------------------- +; Voltage Detect Register 2 +;------------------------------------------------------- +vca2 .equ 005Ah +; +lpe .btequ 0,vca2 ; Internal low-power-consumption enable bit +vc0e .btequ 5,vca2 ; Voltage detection 0 enable bit +vc1e .btequ 6,vca2 ; Voltage detection 1 enable bit +; +;------------------------------------------------------- +; Voltage Detection 1 Level Select Register +;------------------------------------------------------- +vd1ls .equ 005Bh +; +vd1s1 .btequ 1,vd1ls ; Voltage detection 1 Level select bit +vd1s2 .btequ 2,vd1ls ; Voltage detection 1 Level select bit +vd1s3 .btequ 3,vd1ls ; Voltage detection 1 Level select bit +; +;------------------------------------------------------- +; Voltage Monitor 0 Circuit Control Register +;------------------------------------------------------- +vw0c .equ 005Ch +; +vw0c0 .btequ 0,vw0c ; Voltage monitor 0 reset enable bit +vw0c1 .btequ 1,vw0c ; Voltage monitor 0 digital filter mode select bit +vw0f0 .btequ 4,vw0c ; Sampling clock select bit +vw0f1 .btequ 5,vw0c ; Sampling clock select bit +; +;------------------------------------------------------- +; Voltage Monitor 1 Circuit Control Register +;------------------------------------------------------- +vw1c .equ 005Dh +; +vw1c0 .btequ 0,vw1c ; Voltage monitor 1 interrupt enable bit +vw1c1 .btequ 1,vw1c ; Voltage monitor 1 digital filter mode select bit +vw1c2 .btequ 2,vw1c ; Voltage change detection flag +vw1c3 .btequ 3,vw1c ; Voltage detection 1 signal monitor flag +vw1f0 .btequ 4,vw1c ; Sampling clock select bit +vw1f1 .btequ 5,vw1c ; Sampling clock select bit +vw1c7 .btequ 7,vw1c ; Voltage monitor 1 interrupt generation condition select bit +; +;------------------------------------------------------- +; Reset Source Determination Register +;------------------------------------------------------- +rstfr .equ 005Fh +; +cwr .btequ 0,rstfr ; Cold start-up/warm start-up determine flag +hwr .btequ 1,rstfr ; Hardware reset detect flag +swr .btequ 2,rstfr ; Software reset detect flag +wdr .btequ 3,rstfr ; Watchdog timer reset detect flag +; +;------------------------------------------------------- +; High-Speed On-Chip Oscillator 18.432 MHz Control Register 0 +;------------------------------------------------------- +fr18s0 .equ 0064h +; +;------------------------------------------------------- +; High-Speed On-Chip Oscillator 18.432 MHz Control Register 1 +;------------------------------------------------------- +fr18s1 .equ 0065h +; +;------------------------------------------------------- +; High-Speed On-Chip Oscillator Control Register 1 +;------------------------------------------------------- +frv1 .equ 0067h +; +;------------------------------------------------------- +; High-Speed On-Chip Oscillator Control Register 2 +;------------------------------------------------------- +frv2 .equ 0068h +; +;------------------------------------------------------- +; UART0 Transmit/Receive Mode Register +;------------------------------------------------------- +u0mr .equ 0080h +; +smd0_u0mr .btequ 0,u0mr ; Serial I/O mode select bit +smd1_u0mr .btequ 1,u0mr ; Serial I/O mode select bit +smd2_u0mr .btequ 2,u0mr ; Serial I/O mode select bit +ckdir_u0mr .btequ 3,u0mr ; Internal/external clock select bit +stps_u0mr .btequ 4,u0mr ; Stop bit length select bit +pry_u0mr .btequ 5,u0mr ; Odd/even parity select bit +prye_u0mr .btequ 6,u0mr ; Parity enable bit +; +;------------------------------------------------------- +; UART0 Bit Rate Register +;------------------------------------------------------- +u0brg .equ 0081h +; +;------------------------------------------------------- +; UART0 Transmit Buffer Register Low +;------------------------------------------------------- +u0tbl .equ 0082h +; +;------------------------------------------------------- +; UART0 Transmit Buffer Register High +;------------------------------------------------------- +u0tbh .equ 0083h +; +;------------------------------------------------------- +; UART0 Transmit/Receive Control Register 0 +;------------------------------------------------------- +u0c0 .equ 0084h +; +clk0_u0c0 .btequ 0,u0c0 ; U0BRG count source select bit +clk1_u0c0 .btequ 1,u0c0 ; U0BRG count source select bit +txept_u0c0 .btequ 3,u0c0 ; Transmit register empty flag +dfe_u0c0 .btequ 4,u0c0 ; RXD0 digital filter enable bit +nch_u0c0 .btequ 5,u0c0 ; Data output select bit +ckpol_u0c0 .btequ 6,u0c0 ; CLK polarity select bit +uform_u0c0 .btequ 7,u0c0 ; Transfer format select bit +; +;------------------------------------------------------- +; UART0 Transmit/Receive Control Register 1 +;------------------------------------------------------- +u0c1 .equ 0085h +; +te_u0c1 .btequ 0,u0c1 ; Transmit enable bit +ti_u0c1 .btequ 1,u0c1 ; Transmit buffer empty flag +re_u0c1 .btequ 2,u0c1 ; Receive enable bit +ri_u0c1 .btequ 3,u0c1 ; Receive complete flag +u0irs_u0c1 .btequ 4,u0c1 ; UART0 transmit interrupt source select bit +u0rrm_u0c1 .btequ 5,u0c1 ; UART0 continuous receive mode enable bit +; +;------------------------------------------------------- +; UART0 Receive Buffer Register +;------------------------------------------------------- +u0rb .equ 0086h +; +;------------------------------------------------------- +; UART0 Interrupt Flag and Enable Register +;------------------------------------------------------- +u0ir .equ 0088h +; +u0rie .btequ 2,u0ir ; UART0 receive interrupt enable bit +u0tie .btequ 3,u0ir ; UART0 transmit interrupt enable bit +u0rif .btequ 6,u0ir ; UART0 receive interrupt flag +u0tif .btequ 7,u0ir ; UART0 transmit interrupt flag +; +;------------------------------------------------------- +; A/D Register 0 +;------------------------------------------------------- +ad0 .equ 0098h +; +ad0l .equ ad0 ; Low +ad0h .equ ad0+1 ; High +; +;------------------------------------------------------- +; A/D Register 1 +;------------------------------------------------------- +ad1 .equ 009Ah +; +ad1l .equ ad1 ; Low +ad1h .equ ad1+1 ; High +; +;------------------------------------------------------- +; A/D Mode Register +;------------------------------------------------------- +admod .equ 009Ch +; +cks0 .btequ 0,admod ; A/D conversion clock select bit +cks1 .btequ 1,admod ; A/D conversion clock select bit +cks2 .btequ 2,admod ; A/D conversion clock select bit +md0 .btequ 3,admod ; A/D operating mode select bit +md1 .btequ 4,admod ; A/D operating mode select bit +adcap0 .btequ 6,admod ; A/D conversion trigger select bit +adcap1 .btequ 7,admod ; A/D conversion trigger select bit +; +;------------------------------------------------------- +; A/D Input Select Register +;------------------------------------------------------- +adinsel .equ 009Dh +; +ch0 .btequ 0,adinsel ; Channel select bit +adgsel0 .btequ 6,adinsel ; A/D input group select bit +adgsel1 .btequ 7,adinsel ; A/D input group select bit +; +;------------------------------------------------------- +; A/D Control Register 0 +;------------------------------------------------------- +adcon0 .equ 009Eh +; +adst .btequ 0,adcon0 ; A/D conversion start bit +; +;------------------------------------------------------- +; A/D Interrupt Control Status Register +;------------------------------------------------------- +adicsr .equ 009Fh +; +adie .btequ 6,adicsr ; A/D conversion interrupt enable bit +adf .btequ 7,adicsr ; A/D conversion Interrupt request bit +; +;------------------------------------------------------- +; Port P1 Direction Register +;------------------------------------------------------- +pd1 .equ 00A9h +; +pd1_0 .btequ 0,pd1 ; Port P1_0 direction bit +pd1_1 .btequ 1,pd1 ; Port P1_1 direction bit +pd1_2 .btequ 2,pd1 ; Port P1_2 direction bit +pd1_3 .btequ 3,pd1 ; Port P1_3 direction bit +pd1_4 .btequ 4,pd1 ; Port P1_4 direction bit +pd1_5 .btequ 5,pd1 ; Port P1_5 direction bit +pd1_6 .btequ 6,pd1 ; Port P1_6 direction bit +pd1_7 .btequ 7,pd1 ; Port P1_7 direction bit +; +;------------------------------------------------------- +; Port P3 Direction Register +;------------------------------------------------------- +pd3 .equ 00ABh +; +pd3_3 .btequ 3,pd3 ; Port P3_3 direction bit +pd3_4 .btequ 4,pd3 ; Port P3_4 direction bit +pd3_5 .btequ 5,pd3 ; Port P3_5 direction bit +pd3_7 .btequ 7,pd3 ; Port P3_7 direction bit +; +;------------------------------------------------------- +; Port P4 Direction Register +;------------------------------------------------------- +pd4 .equ 00ACh +; +pd4_2 .btequ 2,pd4 ; Port P4_2 direction bit +pd4_5 .btequ 5,pd4 ; Port P4_5 direction bit +pd4_6 .btequ 6,pd4 ; Port P4_6 direction bit +pd4_7 .btequ 7,pd4 ; Port P4_7 direction bit +; +;------------------------------------------------------- +; Port PA Direction Register +;------------------------------------------------------- +pda .equ 00ADh +; +pda_0 .btequ 0,pda ; Port PA_0 direction bit +; +;------------------------------------------------------- +; Port P1 Register +;------------------------------------------------------- +p1 .equ 00AFh +; +p1_0 .btequ 0,p1 ; Port P1_0 bit +p1_1 .btequ 1,p1 ; Port P1_1 bit +p1_2 .btequ 2,p1 ; Port P1_2 bit +p1_3 .btequ 3,p1 ; Port P1_3 bit +p1_4 .btequ 4,p1 ; Port P1_4 bit +p1_5 .btequ 5,p1 ; Port P1_5 bit +p1_6 .btequ 6,p1 ; Port P1_6 bit +p1_7 .btequ 7,p1 ; Port P1_7 bit +; +;------------------------------------------------------- +; Port P3 Register +;------------------------------------------------------- +p3 .equ 00B1h +; +p3_3 .btequ 3,p3 ; Port P3_3 bit +p3_4 .btequ 4,p3 ; Port P3_4 bit +p3_5 .btequ 5,p3 ; Port P3_5 bit +p3_7 .btequ 7,p3 ; Port P3_7 bit +; +;------------------------------------------------------- +; Port P4 Register +;------------------------------------------------------- +p4 .equ 00B2h +; +p4_2 .btequ 2,p4 ; Port P4_2 bit +p4_5 .btequ 5,p4 ; Port P4_5 bit +p4_6 .btequ 6,p4 ; Port P4_6 bit +p4_7 .btequ 7,p4 ; Port P4_7 bit +; +;------------------------------------------------------- +; Port PA Register +;------------------------------------------------------- +pa .equ 00B3h +; +pa_0 .btequ 0,pa ; Port PA_0 bit +; +;------------------------------------------------------- +; Pull-Up Control Register 1 +;------------------------------------------------------- +pur1 .equ 00B5h +; +pu1_0 .btequ 0,pur1 ; Port P1_0 pull-up control bit +pu1_1 .btequ 1,pur1 ; Port P1_1 pull-up control bit +pu1_2 .btequ 2,pur1 ; Port P1_2 pull-up control bit +pu1_3 .btequ 3,pur1 ; Port P1_3 pull-up control bit +pu1_4 .btequ 4,pur1 ; Port P1_4 pull-up control bit +pu1_5 .btequ 5,pur1 ; Port P1_5 pull-up control bit +pu1_6 .btequ 6,pur1 ; Port P1_6 pull-up control bit +pu1_7 .btequ 7,pur1 ; Port P1_7 pull-up control bit +; +;------------------------------------------------------- +; Pull-Up Control Register 3 +;------------------------------------------------------- +pur3 .equ 00B7h +; +pu3_3 .btequ 3,pur3 ; Port P3_3 pull-up control bit +pu3_4 .btequ 4,pur3 ; Port P3_4 pull-up control bit +pu3_5 .btequ 5,pur3 ; Port P3_5 pull-up control bit +pu3_7 .btequ 7,pur3 ; Port P3_7 pull-up control bit +; +;------------------------------------------------------- +; Pull-Up Control Register 4 +;------------------------------------------------------- +pur4 .equ 00B8h +; +pu4_2 .btequ 2,pur4 ; Port P4_2 pull-up control bit +pu4_5 .btequ 5,pur4 ; Port P4_5 pull-up control bit +pu4_6 .btequ 6,pur4 ; Port P4_6 pull-up control bit +pu4_7 .btequ 7,pur4 ; Port P4_7 pull-up control bit +; +;------------------------------------------------------- +; Port I/O Function Control Register +;------------------------------------------------------- +pinsr .equ 00B9h +; +trjiosel .btequ 6,pinsr ; TRJIO input signal select bit +ioinsel .btequ 7,pinsr ; Pin level force read-out bit +; +;------------------------------------------------------- +; Drive Capacity Control Register 1 +;------------------------------------------------------- +drr1 .equ 00BBh +; +drr1_2 .btequ 2,drr1 ; Port P1_2 drive capacity control bit +drr1_3 .btequ 3,drr1 ; Port P1_3 drive capacity control bit +drr1_4 .btequ 4,drr1 ; Port P1_4 drive capacity control bit +drr1_5 .btequ 5,drr1 ; Port P1_5 drive capacity control bit +; +;------------------------------------------------------- +; Drive Capacity Control Register 3 +;------------------------------------------------------- +drr3 .equ 00BDh +; +drr3_3 .btequ 3,drr3 ; Port P3_3 drive capacity control bit +drr3_4 .btequ 4,drr3 ; Port P3_4 drive capacity control bit +drr3_5 .btequ 5,drr3 ; Port P3_5 drive capacity control bit +drr3_7 .btequ 7,drr3 ; Port P3_7 drive capacity control bit +; +;------------------------------------------------------- +; Open-Drain Control Register 1 +;------------------------------------------------------- +pod1 .equ 00C1h +; +pod1_0 .btequ 0,pod1 ; Port P1_0 open-drain control bit +pod1_1 .btequ 1,pod1 ; Port P1_1 open-drain control bit +pod1_2 .btequ 2,pod1 ; Port P1_2 open-drain control bit +pod1_3 .btequ 3,pod1 ; Port P1_3 open-drain control bit +pod1_4 .btequ 4,pod1 ; Port P1_4 open-drain control bit +pod1_5 .btequ 5,pod1 ; Port P1_5 open-drain control bit +pod1_6 .btequ 6,pod1 ; Port P1_6 open-drain control bit +pod1_7 .btequ 7,pod1 ; Port P1_7 open-drain control bit +; +;------------------------------------------------------- +; Open-Drain Control Register 3 +;------------------------------------------------------- +pod3 .equ 00C3h +; +pod3_3 .btequ 3,pod3 ; Port P3_3 open-drain control bit +pod3_4 .btequ 4,pod3 ; Port P3_4 open-drain control bit +pod3_5 .btequ 5,pod3 ; Port P3_5 open-drain control bit +pod3_7 .btequ 7,pod3 ; Port P3_7 open-drain control bit +; +;------------------------------------------------------- +; Open-Drain Control Register 4 +;------------------------------------------------------- +pod4 .equ 00C4h +; +pod4_2 .btequ 2,pod4 ; Port P4_2 open-drain control bi +pod4_5 .btequ 5,pod4 ; Port P4_5 open-drain control bi +pod4_6 .btequ 6,pod4 ; Port P4_6 open-drain control bi +pod4_7 .btequ 7,pod4 ; Port P4_7 open-drain control bi +; +;------------------------------------------------------- +; Port PA Mode Control Register +;------------------------------------------------------- +pamcr .equ 00C5h +; +poda_0 .btequ 0,pamcr ; Port PA_0 open-drain control bit +hwrste .btequ 4,pamcr ; Hardware reset enabled bit +; +;------------------------------------------------------- +; Port 1 Function Mapping Register 0 +;------------------------------------------------------- +pml1 .equ 00C8h +; +p10sel0 .btequ 0,pml1 ; Port P1_0 function select bit +p10sel1 .btequ 1,pml1 ; Port P1_0 function select bit +p11sel0 .btequ 2,pml1 ; Port P1_1 function select bit +p11sel1 .btequ 3,pml1 ; Port P1_1 function select bit +p12sel0 .btequ 4,pml1 ; Port P1_2 function select bit +p12sel1 .btequ 5,pml1 ; Port P1_2 function select bit +p13sel0 .btequ 6,pml1 ; Port P1_3 function select bit +p13sel1 .btequ 7,pml1 ; Port P1_3 function select bit +; +;------------------------------------------------------- +; Port 1 Function Mapping Register 1 +;------------------------------------------------------- +pmh1 .equ 00C9h +; +p14sel0 .btequ 0,pmh1 ; Port P1_4 function select bit +p14sel1 .btequ 1,pmh1 ; Port P1_4 function select bit +p15sel0 .btequ 2,pmh1 ; Port P1_5 function select bit +p15sel1 .btequ 3,pmh1 ; Port P1_5 function select bit +p16sel0 .btequ 4,pmh1 ; Port P1_6 function select bit +p16sel1 .btequ 5,pmh1 ; Port P1_6 function select bit +p17sel0 .btequ 6,pmh1 ; Port P1_7 function select bit +p17sel1 .btequ 7,pmh1 ; Port P1_7 function select bit +; +;------------------------------------------------------- +; Port 3 Function Mapping Register 0 +;------------------------------------------------------- +pml3 .equ 00CCh +; +p33sel0 .btequ 6,pml3 ; Port P3_3 function select bit +p33sel1 .btequ 7,pml3 ; Port P3_3 function select bit +; +;------------------------------------------------------- +; Port 3 Function Mapping Register 1 +;------------------------------------------------------- +pmh3 .equ 00CDh +; +p34sel0 .btequ 0,pmh3 ; Port P3_4 function select bit +p34sel1 .btequ 1,pmh3 ; Port P3_4 function select bit +p35sel0 .btequ 2,pmh3 ; Port P3_5 function select bit +p35sel1 .btequ 3,pmh3 ; Port P3_5 function select bit +p37sel0 .btequ 6,pmh3 ; Port P3_7 function select bit +p37sel1 .btequ 7,pmh3 ; Port P3_7 function select bit +; +;------------------------------------------------------- +; Port 4 Function Mapping Register 0 +;------------------------------------------------------- +pml4 .equ 00CEh +; +p42sel0 .btequ 4,pml4 ; Port P4_2 function select bit +p42sel1 .btequ 5,pml4 ; Port P4_2 function select bit +; +;------------------------------------------------------- +; Port 4 Function Mapping Register 1 +;------------------------------------------------------- +pmh4 .equ 00CFh +; +p45sel0 .btequ 2,pmh4 ; Port P4_5 function select bit +p45sel1 .btequ 3,pmh4 ; Port P4_5 function select bit +p46sel0 .btequ 4,pmh4 ; Port P4_6 function select bit +p46sel1 .btequ 5,pmh4 ; Port P4_6 function select bit +p47sel0 .btequ 6,pmh4 ; Port P4_7 function select bit +p47sel1 .btequ 7,pmh4 ; Port P4_7 function select bit +; +;------------------------------------------------------- +; Port 1 Function Mapping Expansion Register +;------------------------------------------------------- +pmh1e .equ 00D1h +; +p14sel2 .btequ 0,pmh1e ; The P1_4 pin function is selected in conjunction with bits P14SEL0 to P14SEL1 in the PMH1 register +p15sel2 .btequ 2,pmh1e ; The P1_5 pin function is selected in conjunction with bits P15SEL0 to P15SEL1 in the PMH1 register +; +;------------------------------------------------------- +; Port 4 Function Mapping Expansion Register +;------------------------------------------------------- +pmh4e .equ 00D5h +; +p46sel2 .btequ 4,pmh4e ; The P4_6 pin function is selected in conjunction with bits P46SEL0 to P46SEL1 in the PMH4 register +; +;------------------------------------------------------- +; Timer RJ Counter Register, Timer RJ Reload Register +;------------------------------------------------------- +trj .equ 00D8h +; +;------------------------------------------------------- +; Timer RJ Control Register +;------------------------------------------------------- +trjcr .equ 00DAh +; +tstart_trjcr .btequ 0,trjcr ; Timer RJ count start bit +tcstf_trjcr .btequ 1,trjcr ; Timer RJ count status flag +tstop_trjcr .btequ 2,trjcr ; Timer RJ count forced stop bit +tedgf_trjcr .btequ 4,trjcr ; Active edge judgment flag +tundf_trjcr .btequ 5,trjcr ; Timer RJ underflow flag +; +;------------------------------------------------------- +; Timer RJ I/O Control Register +;------------------------------------------------------- +trjioc .equ 00DBh +; +tedgsel_trjioc .btequ 0,trjioc ; I/O polarity switch bit +topcr_trjioc .btequ 1,trjioc ; TRJIO output control bit +tipf0_trjioc .btequ 4,trjioc ; TRJIO input filter select bit +tipf1_trjioc .btequ 5,trjioc ; TRJIO input filter select bit +tiogt0_trjioc .btequ 6,trjioc ; TRJIO count control bit +tiogt1_trjioc .btequ 7,trjioc ; TRJIO count control bit +; +;------------------------------------------------------- +; Timer RJ Mode Register +;------------------------------------------------------- +trjmr .equ 00DCh +; +tmod0_trjmr .btequ 0,trjmr ; Timer RJ operating mode select bit +tmod1_trjmr .btequ 1,trjmr ; Timer RJ operating mode select bit +tmod2_trjmr .btequ 2,trjmr ; Timer RJ operating mode select bit +tedgpl_trjmr .btequ 3,trjmr ; TRJIO edge polarity select bit +tck0_trjmr .btequ 4,trjmr ; Timer RJ count source select bit +tck1_trjmr .btequ 5,trjmr ; Timer RJ count source select bit +tck2_trjmr .btequ 6,trjmr ; Timer RJ count source select bit +tckcut_trjmr .btequ 7,trjmr ; Timer RJ count source cutoff bit +; +;------------------------------------------------------- +; Timer RJ Event Select Register +;------------------------------------------------------- +trjisr .equ 00DDh +; +rccpsel0_trjisr .btequ 0,trjisr ; Timer RC output signal select bit +rccpsel1_trjisr .btequ 1,trjisr ; Timer RC output signal select bit +rccpsel2_trjisr .btequ 2,trjisr ; Timer RC output signal inversion bit +; +;------------------------------------------------------- +; Timer RJ Interrupt Control Register +;------------------------------------------------------- +trjir .equ 00DEh +; +trjif_trjir .btequ 6,trjir ; Timer RJ interrupt request flag +trjie_trjir .btequ 7,trjir ; Timer RJ interrupt enable bit +; +;------------------------------------------------------- +; Timer RB Control Register +;------------------------------------------------------- +trbcr .equ 00E0h +; +tstart_trbcr .btequ 0,trbcr ; Timer RB count start bit +tcstf_trbcr .btequ 1,trbcr ; Timer RB count status flag +tstop_trbcr .btequ 2,trbcr ; Timer RB count forced stop bit +; +;------------------------------------------------------- +; Timer RB One-Shot Control Register +;------------------------------------------------------- +trbocr .equ 00E1h +; +tosst_trbocr .btequ 0,trbocr ; Timer RB one-shot start bit +tossp_trbocr .btequ 1,trbocr ; Timer RB one-shot stop bit +tosstf_trbocr .btequ 2,trbocr ; Timer RB one-shot status flag +; +;------------------------------------------------------- +; Timer RB I/O Control Register +;------------------------------------------------------- +trbioc .equ 00E2h +; +topl_trbioc .btequ 0,trbioc ; Timer RB output level select bit +tocnt_trbioc .btequ 1,trbioc ; Timer RB output switch bit +inostg_trbioc .btequ 2,trbioc ; One-shot trigger control bit +inoseg_trbioc .btequ 3,trbioc ; One-shot trigger polarity select bit +; +;------------------------------------------------------- +; Timer RB Mode Register +;------------------------------------------------------- +trbmr .equ 00E3h +; +tmod0_trbmr .btequ 0,trbmr ; Timer RB operating mode select bit +tmod1_trbmr .btequ 1,trbmr ; Timer RB operating mode select bit +tcnt16_trbmr .btequ 2,trbmr ; Timer RB counter select bit +twrc_trbmr .btequ 3,trbmr ; Timer RB write control bit +tck0_trbmr .btequ 4,trbmr ; Timer RB count source select bit +tck1_trbmr .btequ 5,trbmr ; Timer RB count source select bit +tck2_trbmr .btequ 6,trbmr ; Timer RB count source select bit +tckcut_trbmr .btequ 7,trbmr ; Timer RB count source cutoff bit +; +;------------------------------------------------------- +; Timer RB Prescaler Register +;------------------------------------------------------- +trbpre .equ 00E4h +; +;------------------------------------------------------- +; Timer RB Primary Register +;------------------------------------------------------- +trbpr .equ 00E5h +; +;------------------------------------------------------- +; Timer RB Secondary Register +;------------------------------------------------------- +trbsc .equ 00E6h +; +;------------------------------------------------------- +; Timer RB Interrupt Control Register +;------------------------------------------------------- +trbir .equ 00E7h +; +trbif_trbir .btequ 6,trbir ; Timer RB interrupt request flag +trbie_trbir .btequ 7,trbir ; Timer RB interrupt enable bit +; +;------------------------------------------------------- +; Timer RC Counter +;------------------------------------------------------- +trccnt .equ 00E8h +; +;------------------------------------------------------- +; Timer RC General Register A +;------------------------------------------------------- +trcgra .equ 00EAh +; +;------------------------------------------------------- +; Timer RC General Register B +;------------------------------------------------------- +trcgrb .equ 00ECh +; +;------------------------------------------------------- +; Timer RC General Register C +;------------------------------------------------------- +trcgrc .equ 00EEh +; +;------------------------------------------------------- +; Timer RC General Register D +;------------------------------------------------------- +trcgrd .equ 00F0h +; +;------------------------------------------------------- +; Timer RC Mode Register +;------------------------------------------------------- +trcmr .equ 00F2h +; +pwmb_trcmr .btequ 0,trcmr ; TRCIOB PWM mode select bit +pwmc_trcmr .btequ 1,trcmr ; TRCIOC PWM mode select bit +pwmd_trcmr .btequ 2,trcmr ; TRCIOD PWM mode select bit +pwm2_trcmr .btequ 3,trcmr ; PWM2 mode select bit +bufea_trcmr .btequ 4,trcmr ; TRCGRC register function select bit +bufeb_trcmr .btequ 5,trcmr ; TRCGRD register function select bit +cts_trcmr .btequ 7,trcmr ; TRCCNT count start bit +; +;------------------------------------------------------- +; Timer RC Control Register 1 +;------------------------------------------------------- +trccr1 .equ 00F3h +; +toa_trccr1 .btequ 0,trccr1 ; Timer output level select A bit +tob_trccr1 .btequ 1,trccr1 ; Timer output level select B bit +toc_trccr1 .btequ 2,trccr1 ; Timer output level select C bit +tod_trccr1 .btequ 3,trccr1 ; Timer output level select D bit +cks0_trccr1 .btequ 4,trccr1 ; Count source select bit +cks1_trccr1 .btequ 5,trccr1 ; Count source select bit +cks2_trccr1 .btequ 6,trccr1 ; Count source select bit +cclr_trccr1 .btequ 7,trccr1 ; TRCCNT counter clear select bit +; +;------------------------------------------------------- +; Timer RC Interrupt Enable Register +;------------------------------------------------------- +trcier .equ 00F4h +; +imiea_trcier .btequ 0,trcier ; Input capture/compare match A interrupt enable bit +imieb_trcier .btequ 1,trcier ; Input capture/compare match B interrupt enable bit +imiec_trcier .btequ 2,trcier ; Input capture/compare match C interrupt enable bit +imied_trcier .btequ 3,trcier ; Input capture/compare match D interrupt enable bit +ovie_trcier .btequ 7,trcier ; Timer overflow interrupt enable bit +; +;------------------------------------------------------- +; Timer RC Status Register +;------------------------------------------------------- +trcsr .equ 00F5h +; +imfa_trcsr .btequ 0,trcsr ; Input capture/compare match A flag +imfb_trcsr .btequ 1,trcsr ; Input capture/compare match B flag +imfc_trcsr .btequ 2,trcsr ; Input capture/compare match C flag +imfd_trcsr .btequ 3,trcsr ; Input capture/compare match D flag +ovf_trcsr .btequ 7,trcsr ; Timer overflow flag +; +;------------------------------------------------------- +; Timer RC I/O Control Register 0 +;------------------------------------------------------- +trcior0 .equ 00F6h +; +ioa0_trcior0 .btequ 0,trcior0 ; TRCGRA control A0 bit +ioa1_trcior0 .btequ 1,trcior0 ; TRCGRA control A1 bit +ioa2_trcior0 .btequ 2,trcior0 ; TRCGRA control A2 bit +iob0_trcior0 .btequ 4,trcior0 ; TRCGRB control B0 bit +iob1_trcior0 .btequ 5,trcior0 ; TRCGRB control B1 bit +iob2_trcior0 .btequ 6,trcior0 ; TRCGRB control B2 bit +; +;------------------------------------------------------- +; Timer RC I/O Control Register 1 +;------------------------------------------------------- +trcior1 .equ 00F7h +; +ioc0_trcior1 .btequ 0,trcior1 ; TRCGRC control C0 bit +ioc1_trcior1 .btequ 1,trcior1 ; TRCGRC control C1 bit +ioc2_trcior1 .btequ 2,trcior1 ; TRCGRC control C2 bit +ioc3_trcior1 .btequ 3,trcior1 ; TRCGRC control C3 bit +iod0_trcior1 .btequ 4,trcior1 ; TRCGRD control D0 bit +iod1_trcior1 .btequ 5,trcior1 ; TRCGRD control D1 bit +iod2_trcior1 .btequ 6,trcior1 ; TRCGRD control D2 bit +iod3_trcior1 .btequ 7,trcior1 ; TRCGRD control D3 bit +; +;------------------------------------------------------- +; Timer RC Control Register 2 +;------------------------------------------------------- +trccr2 .equ 00F8h +; +polb_trccr2 .btequ 0,trccr2 ; TRCIOB PWM mode output level control bit +polc_trccr2 .btequ 1,trccr2 ; TRCIOC PWM mode output level control bit +pold_trccr2 .btequ 2,trccr2 ; TRCIOD PWM mode output level control bit +cstp_trccr2 .btequ 5,trccr2 ; Count stop bit +tceg0_trccr2 .btequ 6,trccr2 ; TRCTRG input edge select bit +tceg1_trccr2 .btequ 7,trccr2 ; TRCTRG input edge select bit +; +;------------------------------------------------------- +; Timer RC Digital Filter Function Select Register +;------------------------------------------------------- +trcdf .equ 00F9h +; +dfa_trcdf .btequ 0,trcdf ; TRCIOA digital filter function bit +dfb_trcdf .btequ 1,trcdf ; TRCIOB digital filter function bit +dfc_trcdf .btequ 2,trcdf ; TRCIOC digital filter function bit +dfd_trcdf .btequ 3,trcdf ; TRCIOD digital filter function bit +dftrg_trcdf .btequ 4,trcdf ; TRCTRG digital filter function bit +dfck0_trcdf .btequ 6,trcdf ; Digital filter clock select bit +dfck1_trcdf .btequ 7,trcdf ; Digital filter clock select bit +; +;------------------------------------------------------- +; Timer RC Output Enable Register +;------------------------------------------------------- +trcoer .equ 00FAh +; +ea_trcoer .btequ 0,trcoer ; TRCIOA output disable bit +eb_trcoer .btequ 1,trcoer ; TRCIOB output disable bit +ec_trcoer .btequ 2,trcoer ; TRCIOC output disable bit +ed_trcoer .btequ 3,trcoer ; TRCIOD output disable bit +pto_trcoer .btequ 7,trcoer ; Timer output disable bit +; +;------------------------------------------------------- +; Timer RC A/D Conversion Trigger Control Register +;------------------------------------------------------- +trcadcr .equ 00FBh +; +adtrgae_trcadcr .btequ 0,trcadcr ; TRCGRA A/D conversion start trigger enable bit +adtrgbe_trcadcr .btequ 1,trcadcr ; TRCGRB A/D conversion start trigger enable bit +adtrgce_trcadcr .btequ 2,trcadcr ; TRCGRC A/D conversion start trigger enable bit +adtrgde_trcadcr .btequ 3,trcadcr ; TRCGRD A/D conversion start trigger enable bit +; +;------------------------------------------------------- +; Timer RC Waveform Output Manipulation Register +;------------------------------------------------------- +trcopr .equ 00FCh +; +opsel0_trcopr .btequ 0,trcopr ; Waveform output manipulation event select bit +opsel1_trcopr .btequ 1,trcopr ; Waveform output manipulation event select bit +opol0_trcopr .btequ 2,trcopr ; Waveform output manipulation period output level select bit +opol1_trcopr .btequ 3,trcopr ; Waveform output manipulation period output level select bit +restats_trcopr .btequ 4,trcopr ; Restart method select bit +ope_trcopr .btequ 5,trcopr ; Waveform output manipulation enable bit +; +;------------------------------------------------------- +; Comparator B Control Register +;------------------------------------------------------- +wcmpr .equ 0180h +; +wcb1m0 .btequ 0,wcmpr ; Comparator B1 operation enable bit +wcb1out .btequ 3,wcmpr ; Comparator B1 monitor flag +wcb3m0 .btequ 4,wcmpr ; Comparator B3 operation enable bit +wcb3out .btequ 7,wcmpr ; Comparator B3 monitor flag +; +;------------------------------------------------------- +; Comparator B1 Interrupt Control Register +;------------------------------------------------------- +wcb1intr .equ 0181h +; +wcb1f0 .btequ 0,wcb1intr ; Comparator B1 filter select bit +wcb1f1 .btequ 1,wcb1intr ; Comparator B1 filter select bit +wcb1s0 .btequ 4,wcb1intr ; Comparator B1 interrupt edge select bit +wcb1s1 .btequ 5,wcb1intr ; Comparator B1 interrupt edge select bit +wcb1inten .btequ 6,wcb1intr ; Comparator B1 interrupt enable signal bit +wcb1f .btequ 7,wcb1intr ; Comparator B1 interrupt request flag +; +;------------------------------------------------------- +; Comparator B3 Interrupt Control Register +;------------------------------------------------------- +wcb3intr .equ 0182h +; +wcb3f0 .btequ 0,wcb3intr ; Comparator B3 filter select bit +wcb3f1 .btequ 1,wcb3intr ; Comparator B3 filter select bit +wcb3s0 .btequ 4,wcb3intr ; Comparator B3 interrupt edge select bit +wcb3s1 .btequ 5,wcb3intr ; Comparator B3 interrupt edge select bit +wcb3inten .btequ 6,wcb3intr ; Comparator B3 interrupt enable signal bit +wcb3f .btequ 7,wcb3intr ; Comparator B3 interrupt request flag +; +;------------------------------------------------------- +; Flash Memory Status Register +;------------------------------------------------------- +fst .equ 01A9h +; +rdysti .btequ 0,fst ; Flash ready status interrupt request flag +bsyaei .btequ 1,fst ; Flash access error interrupt request flag +fst2 .btequ 2,fst ; LBDATA monitor flag +fst3 .btequ 3,fst ; Program-suspend status flag +fst4 .btequ 4,fst ; Program error status flag +fst5 .btequ 5,fst ; Erase error/blank check error status flag +fst6 .btequ 6,fst ; Erase-suspend status flag +fst7 .btequ 7,fst ; Ready/busy status flag +; +;------------------------------------------------------- +; Flash Memory Control Register 0 +;------------------------------------------------------- +fmr0 .equ 01AAh +; +fmr01 .btequ 1,fmr0 ; CPU rewrite mode select bit +fmr02 .btequ 2,fmr0 ; EW1 mode select bit +fmstp .btequ 3,fmr0 ; Flash memory stop bit +cmdrst .btequ 4,fmr0 ; Erase/write sequence reset bit +cmderie .btequ 5,fmr0 ; Erase/write error, blank check error, command error interrupt enable bit +bsyaeie .btequ 6,fmr0 ; Flash access error interrupt enable bit +rdystie .btequ 7,fmr0 ; Flash ready status interrupt enable bit +; +;------------------------------------------------------- +; Flash Memory Control Register 1 +;------------------------------------------------------- +fmr1 .equ 01ABh +; +wtfmstp .btequ 2,fmr1 ; Flash memory stop bit in wait mode +fmr13 .btequ 3,fmr1 ; Lock bit disable select bit +fmr16 .btequ 6,fmr1 ; Data flash block A rewrite disable bit +fmr17 .btequ 7,fmr1 ; Data flash block B rewrite disable bit +; +;------------------------------------------------------- +; Flash Memory Control Register 2 +;------------------------------------------------------- +fmr2 .equ 01ACh +; +fmr20 .btequ 0,fmr2 ; Suspend enable bit +fmr21 .btequ 1,fmr2 ; Suspend request bit +fmr22 .btequ 2,fmr2 ; Interrupt request suspend request enable bit +fmr27 .btequ 7,fmr2 ; Low-current-consumption read mode enable bit +; +;------------------------------------------------------- +; Flash Memory Refresh Control Register +;------------------------------------------------------- +frefr .equ 01ADh +; +ref0 .btequ 0,frefr ; Periodic refresh interval control bit +ref1 .btequ 1,frefr ; Periodic refresh interval control bit +ref2 .btequ 2,frefr ; Periodic refresh interval control bit +ref3 .btequ 3,frefr ; Periodic refresh interval control bit +ref4 .btequ 4,frefr ; Periodic refresh interval control bit +ref5 .btequ 5,frefr ; Periodic refresh interval control bit +; +;------------------------------------------------------- +; Address Match Interrupt Register 0 +;------------------------------------------------------- +aiadr0 .equ 01C0h +; +aiadr0l .equ aiadr0 ; Low +aiadr0m .equ aiadr0+1 ; Middle +aiadr0h .equ aiadr0+2 ; High +; +;------------------------------------------------------- +; Address Match Interrupt Enable Register 0 +;------------------------------------------------------- +aien0 .equ 01C3h +; +aien00 .btequ 0,aien0 ; Address match interrupt enable 0 bit +; +;------------------------------------------------------- +; Address Match Interrupt Register 1 +;------------------------------------------------------- +aiadr1 .equ 01C4h +; +aiadr1l .equ aiadr1 ; Low +aiadr1m .equ aiadr1+1 ; Middle +aiadr1h .equ aiadr1+2 ; High +; +;------------------------------------------------------- +; Address Match Interrupt Enable Register 1 +;------------------------------------------------------- +aien1 .equ 01C7h +; +aien10 .btequ 0,aien1 ; Address match interrupt enable 1 bit +; diff --git a/src.original/timer.c b/src.original/timer.c new file mode 100644 index 0000000..f32b3c5 --- /dev/null +++ b/src.original/timer.c @@ -0,0 +1,60 @@ +/* + PS/2 L[{[h SHARP X1 ɂ‚Ȃ + 100[ms] ̃C^[o^C}[ + + PS/2 ̎M^CAEgŎgĂ܂B + + + 2014N722 쐬 + + http://kyoutan.jpn.org/ + + ۏ؂łB + ꂪ쐬͗prɐ݂܂BpE񏤗pɂ炸RɎgpĒč\܂B + ɕAAzzA肵ĂǂƂƂłB + AsvłB +*/ + +#include "sfr_r8m12a.h" +#include "timer.h" +#include "ps2.h" +#include "iodefine.h" + +volatile unsigned short TIMER=0; // 100[ms]^C}[ + +void timer_init(void) +{ + // TIMER RB2 100ms C^[o^C}[ + msttrb=0; // X^oC + trbcr=0b00000100; // JEg~ + trbmr=0b01100100; // f64 16rbg ^C}[h +/* + 100[ms] = 100000[us] = 1843200 + f2 921600 + f4 460800 + f8 230400 + f16 115200 + f32 57600 + f64 28800 = 0x7080 +*/ + // 100[ms] = f64 0x7080 + trbpre=0x80; // 8rbg + trbpr=0x70; // 8rbg + trbie_trbir=1; // 荞݋ +} + +/* +void timer_start(void) +{ + tstart_trbcr=1; // TIMER RB2 JEgJn +} +*/ + +#pragma INTERRUPT INT_trb(vect=24) +void INT_trb(void) +{ + TIMER++; + if(0xFF != PS2TIMER) PS2TIMER++; // ^CAEgpI[o[t[Ȃ + + while(trbif_trbir==1) trbif_trbir=0; // 荞݃tONA +} diff --git a/src.original/timer.h b/src.original/timer.h new file mode 100644 index 0000000..fff0543 --- /dev/null +++ b/src.original/timer.h @@ -0,0 +1,19 @@ +/* + PS/2 L[{[h SHARP X1 ɂ‚Ȃ + 100[ms] ̃C^[o^C}[ + + 2014N722 쐬 + + http://kyoutan.jpn.org/ + + ۏ؂łB + ꂪ쐬͗prɐ݂܂BpE񏤗pɂ炸RɎgpĒč\܂B + ɕAAzzA肵ĂǂƂƂłB + AsvłB +*/ + +extern volatile unsigned short TIMER; // 100[ms]^C}[ + +void timer_init(void); +//void timer_start(void); +#define timer_start() tstart_trbcr=1 // TIMER RB2 JEgJn diff --git a/src.original/uart.c b/src.original/uart.c new file mode 100644 index 0000000..a48c147 --- /dev/null +++ b/src.original/uart.c @@ -0,0 +1,188 @@ + +#include "sfr_r8m12a.h" +#include "uart.h" + +// obt@TCY2̔{Ȃ_ +// obt@TCYύXꍇX^bNTCY𒲐RAMȂ悤 +/*#define buffsize 32 + +volatile unsigned char buff[buffsize]; +volatile unsigned char readpos,writepos; +*/ +void osc_init(void) +{ + // IV[^[ɐ؂ւ + prc0=1; // NbNWX^ANZX + ococr=0b00000001; // I`bvIV[^[U ᑬU + { + unsigned char a; + for(a=0; a<255; a++); // ŃIV[^[̔U肷̂҂ĂƂ̂œKɎԑ҂ + } + sckcr=0b01000000; // XIN/IV[^[IōI CPUNbN + ckstpr=0b10000000; // VXeNbNᑬ/IōI + phisel=0x00; // VXeNbN + frv1=fr18s0; // I`bvIV[^[18.432MHzɒ + frv2=fr18s1; + prc0=0; // NbNWX^ANZX֎~ +} + +void uart_init(void) +{ + // UART0̐ݒ + p14sel0=1; + p14sel1=0; + p14sel2=0; // P1_4TXD + + p15sel0=1; + p15sel1=0; + p15sel2=0; // P1_5RXD + +//#define RTS p1_0 +// pd1_0=1; +// RTS=1; // 1:MȂł 0:MĂ + + mstuart=0; // W[X^oC + u0mr=0b00000101; // 8rbg Xgbvrbg1 peB + u0c0=0b00010000; // LSBt@[Xg vbVvo tB^ON JEg\[X + u0brg=119; // 9600bps + //u0brg=29; // 38400bps + //u0brg=19; // 57600bps + //u0brg=9; // 115200bps + u0rrm_u0c1=0; // AM[h֎~ + u0tie=0; // M荞݋֎~ + u0rie=0; // M荞݋֎~ + te_u0c1=1; // M + re_u0c1=1; // M + + /*ilvl8=(ilvl8 & 0x0F) | (1 << 4); // M荞݃x1 + u0rie=1; // M荞݋ + + readpos=0; + writepos=0; + + asm("LDIPL #0"); // vZbT荞ݗD惌x0i̒lx̊荞݂󂯕tj + asm("FSET I"); // 荞݋ + RTS=0; // Mv + */ +} + +void putch(unsigned char a) +{ + while(ti_u0c1==0); // obt@ɂȂ܂ő҂ + + u0tbh=0; + u0tbl=a; +} + +void puts(unsigned char str[]) +{ + unsigned int a=0; + while(1) + { + if(str[a]==0) break; + putch(str[a]); + a++; + } +} + +void puthex(unsigned char a) +{ + putch(tochar((a&0xF0)>>4)); + putch(tochar(a&0x0F)); +} + +unsigned char tochar(unsigned char a) +{ + if(a<10) a=a+0x30; + else a=a+0x41-10; + return a; +} + +void puthexshort(unsigned short a) +{ + puthex((a>>8)&0xFF); + puthex((a&0xFF)); +} + +// ȂɂM1Ԃ +unsigned char keyhit(void) +{ + return (unsigned char)ri_u0c1; +} + +// 荞݂gȂ1oCg[h +unsigned char getch(void) +{ +// RTS=0; // Mv + while(ri_u0c1==0); // M܂ő҂ +// RTS=1; // M֎~ + return (unsigned char)(u0rb&0xFF); // u0rbǂނri0ɂȂ +} + +// 荞݂g1oCg[h Mobt@t +/*unsigned char getch(void) +{ + unsigned char a; + while(writepos==readpos); // M܂ő҂ + a=buff[readpos]; + readpos++; + readpos&=(buffsize-1); + // Mobt@ɂȂ瑗Mv + if(writepos==readpos) RTS=0; // Mv + + return a; +}*/ + + +unsigned short getshort(void) +{ + unsigned short data; + data =((unsigned short)getch()<<8); + data+=((unsigned short)getch() ); + return data; +} + +void putshort(unsigned short data) +{ + putch((data>>8)&0xFF); + putch((data )&0xFF); +} + +void putdecimal(unsigned short data) +{ + putch(tochar(data/10000)); + data=data%10000; + putch(tochar(data/1000)); + data=data%1000; + putch(tochar(data/100)); + data=data%100; + putch(tochar(data/10)); + data=data%10; + putch(tochar(data)); +} + +/* +#pragma INTERRUPT int_uart_receive // int_uart_receive ֐͊荞݃[`łƃRpCɂm点 +void int_uart_receive(void) +{ + signed char a; + // 荞݃tONA + while(u0rif==1) u0rif==0; + + buff[writepos]=(unsigned char)u0rb; + writepos++; + writepos&=(buffsize-1); + + // obt@ɗ܂Ă瑗M֎~ɂ + // RTS1ɂĂAɂ͎~܂Ȃ̂臒l͗]T + a=writepos-readpos; + if(a>0) + { + if(a<4) RTS=1; // M֎~ + } + else + { + if(a>-4) RTS=1; // M֎~ + } +} +*/ \ No newline at end of file diff --git a/src.original/uart.h b/src.original/uart.h new file mode 100644 index 0000000..61918d9 --- /dev/null +++ b/src.original/uart.h @@ -0,0 +1,14 @@ + +void osc_init(void); +void uart_init(void); +void putch(unsigned char a); +void puts(unsigned char str[]); +void puthex(unsigned char a); +void puthexshort(unsigned short a); +unsigned short getshort(void); +void putshort(unsigned short data); + +unsigned char getch(void); +unsigned char keyhit(void); +void putdecimal(unsigned short data); +unsigned char tochar(unsigned char a); diff --git a/src.original/x1key.c b/src.original/x1key.c new file mode 100644 index 0000000..1a37dde --- /dev/null +++ b/src.original/x1key.c @@ -0,0 +1,139 @@ +/* + PS/2 L[{[h SHARP X1 ɂ‚Ȃ + X1 L[{[h̑M + + X1Z^[ (http://www.x1center.org/) ́AL[{[h̓`tH[}bgdlQlɂ܂B + X1L[{[h̎ĂȂ̂ŁAϏ܂B + X1Z^[̎́ug镨ΎRɎgĉvƂ̂ƂłB + + + 2014N722 쐬 + + http://kyoutan.jpn.org/ + + ۏ؂łB + ꂪ쐬͗prɐ݂܂BpE񏤗pɂ炸RɎgpĒč\܂B + ɕAAzzA肵ĂǂƂƂłB + AsvłB +*/ + + +#include "sfr_r8m12a.h" +#include "x1key.h" +#include "iodefine.h" + +unsigned short SEND_DATA; // X1Mf[^ + +void X1_send(unsigned short data) +{ + while(0 != tcstf_trjcr); // MȂI܂ő҂ + + SEND_DATA=data; + + /* TIMER RJ */ + trjioc= 0b00000011; /* TRJO Ho͊JnATRJIO gOo͖ */ + trjmr= 0b00000001; /* pXo̓[hA */ + trjcr= 0b00000100; /* JEg~ o̓s */ + pmh3 = 0b10000000; // P3_7 TRJO X1KEYOUT TRJO + trjie_trjir=1; /* TIMER RJ 荞݋ */ + trj=TRJ250us; // 250us Zbg i250us L wb_[j250usɈӖ͖BƒZĂǂ + tstart_trjcr=1; // ^C}[X^[g +} + +void x1key_init(void) +{ + X1KEYOUT=1; + + /* TIMER RJ */ + msttrj=0; // X^oC + trjcr= 0b00000100; /* JEg~ */ + trjioc= 0b00000011; /* TRJO Ho͊JnATRJIO gOo͖ */ + trjmr= 0b00000001; /* pXo̓[hA */ + trjcr= 0b00000100; /* JEg~ o̓s */ +} + +// TIMER RJ A_[t[荞 +// ^C}[̋@\ŁA_EJE^A_[t[邽тɁA +// o̓s (TRJO) ̏o͂]܂ +#pragma INTERRUPT INT_trj (vect=22) +void INT_trj(void) +{ + static unsigned char count=0; + + if(0==(count&1)) // L + { // 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 + switch(count) + { + case 0: // header L + trj=TRJ1000us; // 1000us + break; + + case 36: // stop I + while(1==tcstf_trjcr) tstart_trjcr=0; // ^C}[~irbg삾Əo͏Ȃ悤j + trjcr= 0b00000100; // JEg~ o̓s + pmh3 =0b10000000; // P3_7 TRJO X1KEYOUT TRJO + break; + + default: + trj=TRJ250us; // 250us + break; + } + } + else //  H + { // 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 + switch(count) + { + case 1: // header H + trj=TRJ700us; + break; + + //case 3: // start H X^[grbgȂ + //trj=TRJ750us; + // break; + + case 35: // stop H + X1KEYOUT=1; // H o + pmh3 =0b00000000; // P3_7 TRJO X1KEYOUT I/O|[g ]o͓I + trj=TRJ1750us; + break; + + default: // ʃrbg16rbgM + if(0==(SEND_DATA & 0x8000)) + { + trj=TRJ750us; // 0 + } + else + { + trj=TRJ1750us; // 1 + } + SEND_DATA=(SEND_DATA<<1); + break; + } + } + + count++; + if(36>4));// + X1_send(((unsigned short)0b11111111 << 8) + 0x00);// + + X1_send(((unsigned short)0b10111111 << 8) + tochar(a&0x0F));// + X1_send(((unsigned short)0b11111111 << 8) + 0x00);// + + X1_send(((unsigned short)0b10111111 << 8) + 0x20);// + X1_send(((unsigned short)0b11111111 << 8) + 0x00);// +} + +// fobOp 0`15̐𕶎ɕϊ +unsigned char tochar(unsigned char a) +{ + if(a<10) a=a+0x30; + else a=a+0x41-10; + return a; +} diff --git a/src.original/x1key.h b/src.original/x1key.h new file mode 100644 index 0000000..ac4d9a6 --- /dev/null +++ b/src.original/x1key.h @@ -0,0 +1,58 @@ +/* + PS/2 L[{[h SHARP X1 ɂ‚Ȃ + X1 L[{[h̑M + + 2014N722 쐬 + + http://kyoutan.jpn.org/ + + ۏ؂łB + ꂪ쐬͗prɐ݂܂BpE񏤗pɂ炸RɎgpĒč\܂B + ɕAAzzA肵ĂǂƂƂłB + AsvłB +*/ + +/* +18.432MHz +1 = 1/18.432 = 0.0543[us] +256 = 256/18.432 = 13.89[us] +65536 = 65536/18.432 = 3555[us] + +1750[us] 1750/(1/18.432) = 1750*(18.432/1) = 1750*18.432 + = 32256 = 0x7E00 +1000[us] = 1000 *18.432 = 18432 = 0x4800 + 750[us] = 13824 = 0x3600 + 700[us] = 12902 = 0x3266 + 250[us] = 250*18.432 = 4608 = 0x1200 + +^C}[RB2̃vOg`[hƎvǁAvC}Ԃ +A_[t[Ŋ荞ݗvłȂ悤̂ŁA +^C}[RJ2̃pXo̓[hgƂɂB +*/ + +#define TRJ1750us (0x7E00 - 2) +#define TRJ1000us (0x4800 - 0) // ^C}[~ԂŎĝŁA͈Ȃ +#define TRJ750us (0x3600 - 2) +#define TRJ700us (0x3266 - 1) +#define TRJ250us (0x1200 - 2) +#define TRJSTOP (0xFFFF) // Xgbvrbĝ₷݊ +// TRJWX^ɏĂA[hWX^ɓ]܂ 2`3TCN̂ +// ̂ԂĂ + +void X1_send(unsigned short data); +void x1key_init(void); + +unsigned char tochar(unsigned char a); +void puth2(unsigned char a); + + +//extern volatile unsigned short SEND_DATA; // X1Mf[^ +// b15 : 0=eL[̓ +// b14 : 0=L[͗L +// b13 : 0=s[gL +// b12 : 0=GRAPH ON +// b11 : 0=CAPS ON +// b10 : 0=Ji ON +// b09 : 0=SHIFT ON +// b08 : 0=CTRL ON +// b07-00 : ASCII CODE (0x00=KEY OFF) diff --git a/timer.c b/timer.c new file mode 100644 index 0000000..c30373a --- /dev/null +++ b/timer.c @@ -0,0 +1,68 @@ +/* + Connect a PS / 2 keyboard to SHARP X1 + 100 [ms] interval timer + + I am using it for the PS/2 reception timeout. + + + Created July 22, 2014 + + Kyoichi Sato http://kyoutan.jpn.org/ + + There is no guarantee. + The part created by Kyoichi Sato has no restrictions on its use. You can use it freely regardless of whether it is commercial or non-commercial. + It means that you can copy, modify, distribute, or sell it without permission. + No need to contact. +*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "sfr_r8m12a.h" +#include "timer.h" +#include "ps2.h" +#include "iodefine.h" + +volatile unsigned short TIMER = 0; // 100 [ms] timer + +void timer_init(void) +{ + // TIMER RB2 initialization 100ms interval timer + msttrb = 0; // Release standby + trbcr = 0b00000100; // Stop counting + trbmr = 0b01100100; // f64 division 16-bit timer mode +/* + 100 [ms] = 100000 [us] = f1 1843200 + f2 921600 + f4 460800 + f8 230400 + f16 115200 + f32 57600 + f64 28800 = 0x7080 +*/ + // 100 [ms] = f64 0x7080 + trbpre = 0x80; // Lower 8 bits + trbpr = 0x70; // Upper 8 bits + trbie_trbir = 1; // Interrupt enabled +} + +/* +void timer_start(void) +{ + tstart_trbcr = 1; // TIMER RB2 count start +} +*/ + +#pragma INTERRUPT INT_trb(vect=24) +void INT_trb(void) +{ + TIMER++; + if (0xFF != PS2TIMER) PS2TIMER++; // Do not overflow for timeout processing + + while (trbif_trbir == 1) trbif_trbir = 0; // Clear interrupt flag +} + +#ifdef __cplusplus +} +#endif diff --git a/timer.h b/timer.h new file mode 100644 index 0000000..cedc2c4 --- /dev/null +++ b/timer.h @@ -0,0 +1,31 @@ +/* + Connect a PS / 2 keyboard to SHARP X1 + 100 [ms] interval timer + + Created July 22, 2014 + + Kyoichi Sato http://kyoutan.jpn.org/ + + There is no guarantee. + The part created by Kyoichi Sato has no restrictions on its use. You can use it freely regardless of whether it is commercial or non-commercial. + It means that you can copy, modify, distribute, or sell it without permission. + No need to contact. +*/ + +#ifndef TIMER_H +#define TIMER_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern volatile unsigned short TIMER; // 100 [ms] timer + +void timer_init (void); +// void timer_start(void); +#define timer_start() tstart_trbcr = 1 // TIMER RB2 Count start + +#ifdef __cplusplus +} +#endif +#endif // TIMER_H diff --git a/uart.c b/uart.c new file mode 100644 index 0000000..6c2b592 --- /dev/null +++ b/uart.c @@ -0,0 +1,194 @@ +#ifdef __cplusplus + extern "C" { +#endif + +#include "sfr_r8m12a.h" +#include "uart.h" + +// Buffer size must be a multiple of 2 +// When changing the buffer size Adjust the stack size so that RAM does not overflow +/* #define buffsize 32 + +volatile unsigned char buff [buffsize]; +volatile unsigned char readpos, writepos; +*/ +void osc_init (void) +{ + // Switch to built-in high speed oscillator + prc0 = 1; // Clock register permission + ococr = 0b00000001; // High-speed on-chip oscillator oscillation Low-speed oscillation + { + unsigned char a; + for (a = 0; a <255; a ++); // Wait for the oscillator oscillation to stabilize, so wait for an appropriate amount of time. + } + sckcr = 0b01000000; // Select high speed by selecting XIN / high speed oscillator No CPU clock division + ckstpr = 0b10000000; // Select high speed by system clock low speed / high speed selection + phisel = 0x00; // No system clock division + frv1 = fr18s0; // Adjust high speed on-chip oscillator to 18.432MHz + frv2 = fr18s1; + prc0 = 0; // Clock register access prohibited +} + +void uart_init(void) +{ + // UART0 settings + p14sel0 = 1; + p14sel1 = 0; + p14sel2 = 0; // TXD P1_4 + + p15sel0 = 1; + p15sel1 = 0; + p15sel2 = 0; // RXD P1_5 + + // # define RTS p1_0 + // pd1_0 = 1; + // RTS = 1; // 1: Please do not send 0: Please send + + mstuart = 0; // Release module standby + u0mr = 0b00000101; // 8-bit stop bit 1 no parity + u0c0 = 0b00010000; // LSB first push-pull output filter ON count source no frequency division + u0brg = 119; // 9600bps + // u0brg = 29; // 38400bps + // u0brg = 19; // 57600bps + // u0brg = 9; // 115200bps + u0rrm_u0c1 = 0; // Continuous reception mode prohibited + u0tie = 0; // Send interrupt disabled + u0rie = 0; // Receive interrupt disabled + te_u0c1 = 1; // Send permission + re_u0c1 = 1; // Acceptance + + /* ilvl8 = (ilvl8 & 0x0F) | (1 << 4); // Receive interrupt level 1 + u0rie = 1; // Receive interrupt enabled + + readpos = 0; + writepos = 0; + + asm ("LDIPL # 0"); // Processor interrupt priority level 0 (interrupts higher than this value are accepted) + asm ("FSET I"); // Interrupt enabled + RTS = 0; // Send request + */ +} + +void putch(unsigned char a) +{ + while (ti_u0c1 == 0); // Wait until the buffer is empty + + u0tbh = 0; + u0tbl = a; +} + +void puts(unsigned char str []) +{ + unsigned int a = 0; + while (1) + { + if (str [a] == 0) break; + putch (str [a]); + a ++; + } +} + +void puthex(unsigned char a) +{ + putch (tochar ((a & 0xF0) >> 4)); + putch (tochar (a & 0x0F)); +} + +unsigned char tochar(unsigned char a) +{ + if (a <10) a = a + 0x30; + else a = a + 0x41-10; + return a; +} + +void puthexshort(unsigned short a) +{ + puthex ((a >> 8) & 0xFF); + puthex ((a & 0xFF)); +} + +// Returns 1 when something is received +unsigned char keyhit(void) +{ + return (unsigned char) ri_u0c1; +} + +// 1-byte read without interrupts +unsigned char getch(void) +{ + // RTS = 0; // Send request + while (ri_u0c1 == 0); // Wait until received + // RTS = 1; // Send prohibited + return (unsigned char) (u0rb & 0xFF); // ri becomes 0 when reading u0rb +} + +// With 1-byte read receive buffer using interrupts +/* unsigned char getch (void) +{ + unsigned char a; + while (writepos == readpos); // Wait until received + a = buff [readpos]; + readpos ++; + readpos & = (buffsize-1); + // Send request when the receive buffer becomes empty + if (writepos == readpos) RTS = 0; // Send request + + return a; +} */ + + +unsigned short getshort(void) +{ + unsigned short data; + data = ((unsigned short) getch () << 8); + data + = ((unsigned short) getch ()); + return data; +} + +void putshort(unsigned short data) +{ + putch ((data >> 8) & 0xFF); + putch ((data) & 0xFF); +} + +void putdecimal(unsigned short data) +{ + putch (tochar (data / 10000)); + data = data% 10000; + putch (tochar (data / 1000)); + data = data% 1000; + putch (tochar (data / 100)); + data = data% 100; + putch (tochar (data / 10)); + data = data% 10; + putch (tochar (data)); +} + +/* +#pragma INTERRUPT int_uart_receive // ​​Notify the compiler that the int_uart_receive function is an interrupt routine +void int_uart_receive(void) +{ + signed char a; + // Clear interrupt flag + while (u0rif == 1) u0rif == 0; + + buff [writepos] = (unsigned char) u0rb; + writepos ++; + writepos & = (buffsize-1); + + // Prohibit transmission when it accumulates in the buffer + // Even if RTS is set to 1, the threshold does not stop immediately, so the threshold has a margin. + a = writepos-readpos; + if (a> 0) + { + if (a <4) RTS = 1; // Send prohibited + } + else + { + if (a> -4) RTS = 1; // Send prohibited + } +} +*/ +#ifdef __cplusplus +} +#endif diff --git a/uart.h b/uart.h new file mode 100644 index 0000000..123466c --- /dev/null +++ b/uart.h @@ -0,0 +1,25 @@ +#ifndef UART_H +#define UART_H + +#ifdef __cplusplus + extern "C" { +#endif + +void osc_init(void); +void uart_init(void); +void putch(unsigned char a); +void puts(unsigned char str[]); +void puthex(unsigned char a); +void puthexshort(unsigned short a); +unsigned short getshort(void); +void putshort(unsigned short data); + +unsigned char getch(void); +unsigned char keyhit(void); +void putdecimal(unsigned short data); +unsigned char tochar(unsigned char a); + +#ifdef __cplusplus +} +#endif +#endif // UART_H diff --git a/x1key.c b/x1key.c new file mode 100644 index 0000000..9efe2d7 --- /dev/null +++ b/x1key.c @@ -0,0 +1,146 @@ +/* + Connect a PS / 2 keyboard to SHARP X1 + X1 keyboard transmission process + . + I referred to the keyboard transmission format specifications of X1 Center (http://www.x1center.org/). + I don't have the actual X1 keyboard, so it was very helpful. + The material of X1 Center says, "If you have something you can use, feel free to use it." + . + + Created July 22, 2014 + . + Kyoichi Sato http://kyoutan.jpn.org/ + + There is no guarantee. + The part created by Kyoichi Sato has no restrictions on its use. You can use it freely regardless of whether it is commercial or non-commercial. + It means that you can copy, modify, distribute, or sell it without permission. + No need to contact. +*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "sfr_r8m12a.h" +#include "x1key.h" +#include "iodefine.h" + +unsigned short SEND_DATA; // X1 transmission data + +void X1_send(unsigned short data) +{ + while (0 != tcstf_trjcr); // Wait until it finishes if sending + + SEND_DATA = data; + + /* TIMER RJ */ + trjioc = 0b00000011; /* Start output from TRJO H, no TRJIO toggle output */ + trjmr = 0b00000001; /* Pulse output mode, no frequency division */ + trjcr = 0b00000100; /* Stop counting Output pin initialization */ + pmh3 = 0b10000000; // P3_7 TRJO X1KEYOUT to TRJO + trjie_trjir=1; /* TIMER RJ interrupt enabled */ + trj=TRJ250us; // 250us set (250us followed by L header) 250us has no meaning. May be shorter + tstart_trjcr = 1; // Timer start +} + +void x1key_init(void) +{ + X1KEYOUT = 1; + + /* TIMER RJ initialization */ + msttrj = 0; // Release standby + trjcr = 0b00000100; /* Stop counting */ + trjioc = 0b00000011; /* Start output from TRJO H, no TRJIO toggle output */ + trjmr = 0b00000001; /* Pulse output mode, no frequency division */ + trjcr = 0b00000100; /* Stop counting Output pin initialization */ +} + +// TIMER RJ Underflow interrupt +// With the timer function, every time the down counter underflows +// The output of the output pin (TRJO) is inverted +#pragma INTERRUPT INT_trj (vect = 22) +void INT_trj(void) +{ + static unsigned char count = 0; + + if (0 == (count & 1)) // even L period + {// 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 + switch (count) + { + case 0: // header L + trj = TRJ1000us; // 1000us + break; + + case 36: // stop End + while (1 == tcstf_trjcr) tstart_trjcr = 0; // Timer stop (output is not initialized if it is a bit operation) + trjcr = 0b00000100; // Stop counting Output pin initialization + pmh3 = 0b10000000; // P3_7 TRJO X1KEYOUT to TRJO + break; + + default: + trj = TRJ250us; // 250us + break; + } + } + else // odd H period + {// 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 + switch (count) + { + case 1: // header H + trj = TRJ700us; + break; + + // case 3: // start H I don't need a start bit + // trj = TRJ750us; + // break; + + case 35: // stop H period + X1KEYOUT = 1; // H output + pmh3 = 0b00000000; // P3_7 TRJO X1KEYOUT to I / O port Inverted output operation finished + trj = TRJ1750us; + break; + + default: // 16-bit transmission from the most significant bit + if (0 == (SEND_DATA & 0x8000)) + { + trj = TRJ750us; // 0 + } + else + { + trj = TRJ1750us; // 1 + } + SEND_DATA = (SEND_DATA << 1); + break; + } + } + + count++; + if (36 > 4)); // Press + X1_send (((unsigned short) 0b11111111 << 8) + 0x00); // Release + + X1_send (((unsigned short) 0b10111111 << 8) + tochar (a & 0x0F)); // Press + X1_send (((unsigned short) 0b11111111 << 8) + 0x00); // Release + + X1_send (((unsigned short) 0b10111111 << 8) + 0x20); // Press + X1_send (((unsigned short) 0b11111111 << 8) + 0x00); // Release +} + +// Convert numbers from 0 to 15 for debugging to characters +unsigned char tochar(unsigned char a) +{ + if (a <10) a = a + 0x30; + else a = a + 0x41-10; + return a; +} + +#ifdef __cplusplus +} +#endif diff --git a/x1key.h b/x1key.h new file mode 100644 index 0000000..8c7b335 --- /dev/null +++ b/x1key.h @@ -0,0 +1,68 @@ +/* + Connect a PS / 2 keyboard to SHARP X1 + X1 keyboard transmission process + + Created July 22, 2014 + + Kyoichi Sato http://kyoutan.jpn.org/ + + There is no guarantee. + The part created by Kyoichi Sato has no restrictions on its use. You can use it freely regardless of whether it is commercial or non-commercial. + It means that you can copy, modify, distribute, or sell it without permission. + No need to contact. +*/ + +#ifndef X1KEY_H +#define X1KEY_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* 18.432MHz + 1 cycle = 1 / 18.432 = 0.0543 [us] + 256 cycles = 256 / 18.432 = 13.89 [us] + 65536 cycle = 65536 / 18.432 = 3555 [us] + + 1750 [us] 1750 / (1 / 18.432) = 1750 * (18.432/1) = 1750 * 18.432 + = 32256 = 0x7E00 + 1000 [us] = 1000 * 18.432 = 18432 Cycle = 0x4800 + 750 [us] = 13824 = 0x3600 + 700 [us] = 12902 = 0x3266 + 250 [us] = 250 * 18.432 = 4608 = 0x1200 + + I thought that the program waveform generation mode of timer RB2 would be good, but for the primary period + I couldn't request an interrupt due to underflow, so + I decided to use the pulse output mode of timer RJ2. +*/ + +#define TRJ1750us (0x7E00 - 2) +#define TRJ1000us (0x4800 - 0) // Since it is used with the timer stopped, do not pull here +#define TRJ750us (0x3600 - 2) +#define TRJ700us (0x3266 - 1) +#define TRJ250us (0x1200 - 2) +#define TRJSTOP (0xFFFF) // Good night period after stop bit +// It takes 2 to 3 cycles from writing to the TRJ register to transferring to the reload register. +// Pull that much + +void X1_send(unsigned short data); +void x1key_init(void); + +unsigned char tochar(unsigned char a); +void puth2(unsigned char a); + +// extern volatile unsigned short SEND_DATA; // X1 transmission data +// b15: 0 = Input from the numeric keypad +// b14: 0 = With key input +// b13: 0 = With repeat +// b12: 0 = GRAPH ON +// b11: 0 = CAPS ON +// b10: 0 = Kana ON +// b09: 0 = SHIFT ON +// b08: 0 = CTRL ON +// b07-00: ASCII CODE (0x00 = KEY OFF) + +#ifdef __cplusplus +} +#endif +#endif // X1KEY_H diff --git a/x1key.hbp b/x1key.hbp new file mode 100644 index 0000000..2414749 --- /dev/null +++ b/x1key.hbp @@ -0,0 +1,2 @@ +[Setting] +ToolChain=0 diff --git a/x1key.hwp b/x1key.hwp new file mode 100644 index 0000000..9ef7ba7 --- /dev/null +++ b/x1key.hwp @@ -0,0 +1,233 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.8" +[PROJECT_DETAILS] +"X1key" "D:\Renesas\x1key" "D:\Renesas\x1key\X1key.hwp" "M16C" "Renesas M16C Standard" "Application" "R8C/Tiny" "R8C/M12A" +[INFORMATION] +"vWFNg񂪂܂" +[TOOL_CHAIN] +"Renesas M16C Standard Toolchain" "6.00.00" +[CONFIGURATIONS] +"Debug" "D:\Renesas\x1key\Debug" +"Release" "D:\Renesas\x1key\Release" +[BUILD_PHASES] +"Renesas M16C Assembler" 1 +"Renesas M16C C/C++ Compiler" 1 +"Renesas M16C C/C++ Library Generator" 1 +"Renesas M16C Configurator" 1 +"Renesas M16C ConfiguratorR8C" 1 +"Renesas OptLinker" 1 +[TOOL_ENVIRONMENT] +[EXTENSIONS] +"Absolute file" "ABS" +"Absolute list file" "ALS" +"Assembler error tag file" "ATG" +"Assembly include file" "INC" +"Assembly source file" "A30" +"Binary file" "BIN" +"Branch Information file" "JIN" +"C header file" "H" +"C source file" "C" +"C++ header file" "HPP" +"C++ source file" "CC" +"C++ source file" "CP" +"C++ source file" "CPP" +"Calling information file" "CAL" +"Configuration file" "CFG" +"Cross reference file" "XRF" +"Hex file" "HEX" +"ID file" "ID" +"IEEE695 Absolute file" "X30" +"Inspector Information file" "UTL" +"Library file" "LIB" +"Library information file" "LBP" +"Library list file" "LLS" +"Linkage error tag file" "LTG" +"Linkage map file" "MAP" +"List file" "LST" +"MISRA report file" "CSV" +"MISRA rule file" "RDE" +"Object file" "OBJ" +"Preprocessed C source file" "I" +"Profile file" "PRO" +"Relocatable file" "R30" +"Relocatable file" "REL" +"S-Record file" "MOT" +"Stack information file" "SNI" +"Systemcall file" "MRC" +[FILE_GROUPS] +"Absolute file" "BIN" "NONE" "" +"Absolute list file" "TEXT" "EDITOR" "" +"Assembler error tag file" "TEXT" "EDITOR" "" +"Assembly include file" "TEXT" "EDITOR" "" +"Assembly source file" "TEXT" "EDITOR" "" +"Binary file" "BIN" "NONE" "" +"Branch Information file" "TEXT" "EDITOR" "" +"C header file" "TEXT" "EDITOR" "" +"C source file" "TEXT" "EDITOR" "" +"C++ header file" "TEXT" "EDITOR" "" +"C++ source file" "TEXT" "EDITOR" "" +"Calling information file" "BIN" "NONE" "" +"Configuration file" "TEXT" "EDITOR" "" +"Cross reference file" "TEXT" "EDITOR" "" +"Hex file" "TEXT" "EDITOR" "" +"ID file" "TEXT" "EDITOR" "" +"IEEE695 Absolute file" "BIN" "NONE" "" +"Inspector Information file" "BIN" "NONE" "" +"Library file" "BIN" "NONE" "" +"Library information file" "TEXT" "EDITOR" "" +"Library list file" "TEXT" "EDITOR" "" +"Linkage error tag file" "TEXT" "EDITOR" "" +"Linkage map file" "TEXT" "EDITOR" "" +"List file" "TEXT" "EDITOR" "" +"MISRA report file" "TEXT" "EDITOR" "" +"MISRA rule file" "TEXT" "EDITOR" "" +"Object file" "BIN" "NONE" "" +"Preprocessed C source file" "TEXT" "EDITOR" "" +"Profile file" "BIN" "NONE" "" +"Relocatable file" "BIN" "NONE" "" +"S-Record file" "TEXT" "EDITOR" "" +"Stack information file" "BIN" "NONE" "" +"Systemcall file" "TEXT" "EDITOR" "" +[ASSOCIATED_APPLICATIONS] +[TOOLCHAIN_PHASE] +"Renesas M16C Assembler" +"Renesas M16C C/C++ Compiler" +"Renesas M16C C/C++ Library Generator" +"Renesas M16C Configurator" +"Renesas M16C ConfiguratorR8C" +"Renesas OptLinker" +[UTILITY_PHASE] +[CUSTOM_PHASES] +[CUSTOM_PHASE_INPUT_GROUP] +[CUSTOM_PHASE_OUTPUT_SYNTAX] +[BUILD_ORDER] +"Renesas M16C C/C++ Library Generator" 1 +"Renesas M16C C/C++ Compiler" 1 +"Renesas M16C Assembler" 1 +"Renesas OptLinker" 1 +"Renesas M16C ConfiguratorR8C" 0 +"Renesas M16C Configurator" 0 +[BUILD_PHASE_DETAILS] +"Renesas M16C Assembler" "Assembly source file" 1 +"Renesas M16C C/C++ Compiler" "C source file|C++ source file" 1 +"Renesas M16C C/C++ Library Generator" "" 0 +"Renesas M16C Configurator" "Configuration file" 0 +"Renesas M16C ConfiguratorR8C" "Configuration file" 0 +"Renesas OptLinker" "Object file|Library file|Relocatable file" 0 +[BUILD_FILE_ORDER_Assembly source file] +"Renesas M16C Assembler" 1 +[BUILD_FILE_ORDER_C source file] +"Renesas M16C C/C++ Compiler" 1 +[BUILD_FILE_ORDER_C++ source file] +"Renesas M16C C/C++ Compiler" 1 +[SCRAP] +"Project Generator Setup File" "" +[MAPPINGS] +"Assembly source file" "Renesas M16C Assembler" "Renesas M16C C/C++ Compiler" +"Library file" "Renesas OptLinker" "Renesas M16C C/C++ Library Generator" +"Object file" "Renesas OptLinker" "Renesas M16C Assembler" +"Object file" "Renesas OptLinker" "Renesas M16C C/C++ Compiler" +[PROJECT_FILES] +"D:\Renesas\x1key\main.h" "User" "C header file" 2 +"D:\Renesas\x1key\iodefine.h" "User" "C header file" 2 +"D:\Renesas\x1key\keyconv.c" "User" "C source file" 2 +"D:\Renesas\x1key\keyconv.h" "User" "C header file" 2 +"D:\Renesas\x1key\keytable.h" "User" "C header file" 2 +"D:\Renesas\x1key\main.c" "User" "C source file" 2 +"D:\Renesas\x1key\ncrt0.a30" "User" "Assembly source file" 2 +"D:\Renesas\x1key\ps2.c" "User" "C source file" 2 +"D:\Renesas\x1key\ps2.h" "User" "C header file" 2 +"D:\Renesas\x1key\timer.c" "User" "C source file" 2 +"D:\Renesas\x1key\timer.h" "User" "C header file" 2 +"D:\Renesas\x1key\x1key.c" "User" "C source file" 2 +"D:\Renesas\x1key\x1key.h" "User" "C header file" 2 +[FOLDER] +"Assembly source file" "Assembly source file" +"C header file" "C header file" +"C source file" "C source file" +[GENERAL_DATA_PROJECT] +"USE_CUSTOM_LINKAGE_ORDER" "1" +[ON_DEMAND_COMPONENTS_LOADED] +[SYNC_SESSION_NAMES] +[SESSIONS] +"DefaultSession" "D:\Renesas\x1key\DefaultSession.hsf" 0 +[GENERAL_DATA_SESSION_DefaultSession] +[OPTIONS_Debug_Renesas M16C Assembler] +"Assembly source file" "0c08a6ad3a0afc10" 4 +"D:\Renesas\x1key\ncrt0.a30" "0c08a6ad3a0afc10" 4 +[OPTIONS_Debug_Renesas M16C C/C++ Compiler] +"C source file" "0c08a6ad3a0afc10" 2 +"C++ source file" "0d255f408a0afc10" 3 +"D:\Renesas\x1key\keyconv.c" "0005bc57566afc10" 2 +"D:\Renesas\x1key\main.c" "0f26a3f24a0afc10" 2 +"D:\Renesas\x1key\ps2.c" "0697e34f775afc10" 2 +"D:\Renesas\x1key\timer.c" "05a40b30775afc10" 2 +"D:\Renesas\x1key\x1key.c" "02c4a5fd475afc10" 2 +[OPTIONS_Debug_Renesas M16C C/C++ Library Generator] +"Single Shot" "0c08a6ad3a0afc10" 1 +[OPTIONS_Debug_Renesas M16C Configurator] +"Single Shot" "0005bc57566afc10" 6 +[OPTIONS_Debug_Renesas M16C ConfiguratorR8C] +"Single Shot" "0005bc57566afc10" 6 +[OPTIONS_Debug_Renesas OptLinker] +"Single Shot" "0fa00d57566afc10" 5 +[OPTIONS_Debug] +"" 0 +"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] " 6 +"[V|VERSION|1] [S|DEFINE|__UART0__] [S|LANG|CPP] [S|OUTPUT|OBJECTCODE] [B|INSPECTOR|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [S|MISRA|ALL] [B|SILENT|1] [S|CPU|R8C] +" 3 +"[V|VERSION|1] [S|LIST|LM] [B|INSPECTOR|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DISABLES_MESSAGE|1] [S|CPU|R8C] " 4 +"[V|VERSION|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [S|CPU|R8C] [B|NOFLOAT|1] [S|MODE|BUILD/CHANGED]" 1 +"[V|VERSION|1] [S|OUTPUT|OBJECTCODE] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|INSPECTOR|1] [B|SILENT|1] [S|CPU|R8C] [S|DEFINE|__UART0__] " 2 +"[V|VERSION|6] [B|OPTIMIZE|0] [B|DEBUG|1] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|OTHER|^"-change_message=information=1100,1322,1410^"] [S|FORM|STYPE] [B|TOTAL_SIZE|1] [B|STACK|1] [S|START|data_SE,bss_SE,data_SO,bss_SO,data_NE,bss_NE,data_NO,bss_NO,stack,istack,heap_NE(400)|interrupt,rom_NE,rom_NO,data_SEI,data_SOI,data_NEI,data_NOI,switch_table,C$VTBL,program(e000)|vector(fed8)]" 5 +[EXCLUDED_FILES_Debug] +[LINKAGE_ORDER_Debug] +"D:\Renesas\x1key\Debug\ncrt0.r30" +[GENERAL_DATA_CONFIGURATION_Debug] +[OPTIONS_Release_Renesas M16C Assembler] +"Assembly source file" "07cdf9d0e95afc10" 4 +"D:\Renesas\x1key\ncrt0.a30" "07cdf9d0e95afc10" 4 +[OPTIONS_Release_Renesas M16C C/C++ Compiler] +"C source file" "0f9e27549d9afc10" 2 +"C++ source file" "0f9e27549d9afc10" 3 +"D:\Renesas\x1key\keyconv.c" "0f9e27549d9afc10" 2 +"D:\Renesas\x1key\main.c" "0f9e27549d9afc10" 2 +"D:\Renesas\x1key\ps2.c" "0f9e27549d9afc10" 2 +"D:\Renesas\x1key\timer.c" "0f9e27549d9afc10" 2 +"D:\Renesas\x1key\x1key.c" "0f9e27549d9afc10" 2 +[OPTIONS_Release_Renesas M16C C/C++ Library Generator] +"Single Shot" "07cdf9d0e95afc10" 1 +[OPTIONS_Release_Renesas M16C Configurator] +"Single Shot" "0005bc57566afc10" 6 +[OPTIONS_Release_Renesas M16C ConfiguratorR8C] +"Single Shot" "0005bc57566afc10" 6 +[OPTIONS_Release_Renesas OptLinker] +"Single Shot" "00024c3dd5aafc10" 5 +[OPTIONS_Release] +"" 0 +"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] " 6 +"[V|VERSION|1] [B|INSPECTOR|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [S|LIST|L|M] [B|DISABLES_MESSAGE|1] [S|CPU|R8C] +" 4 +"[V|VERSION|1] [S|DEFINE|__UART0__] [S|LANG|CPP] [S|OUTPUT|OBJECTCODE] [B|INSPECTOR|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [S|OPTIMIZE|5] [B|OR|1] [S|MISRA|ALL] [B|SILENT|1] [S|CPU|R8C] +" 3 +"[V|VERSION|1] [S|DEFINE|__UART0__] [S|LANG|C] [S|OUTPUT|OBJECTCODE] [B|INSPECTOR|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [S|OPTIMIZE|5] [B|OR|1] [S|MISRA|ALL] [B|SILENT|1] [S|CPU|R8C] +" 2 +"[V|VERSION|1] [S|MODE|BUILD/CHANGED] [S|EXISTOUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|NOFLOAT|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [S|OPTIMIZE|3] [S|OPTIMIZERS|OR] [S|CPU|R8C] +" 1 +"[V|VERSION|6] [S|FORM|STYPE] [S|BYTE_COUNT_VALUE|FF] [B|DEBUG|0] [S|CRC|NONE|00000000] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|SHOW|METHODCUSTOM|] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [I|SPACE|^"FF^"] [S|OPTIMIZEITEMS|ALL] [S|START|data_SE,bss_SE,data_SO,bss_SO,data_NE,bss_NE,data_NO,bss_NO,stack,istack,heap_NE(0400)|program_dataflash,flash_data_NE,flash_data_NO(03000)|interrupt,rom_NE,rom_NO,data_SEI,data_SOI,data_NEI,data_NOI,switch_table,C$VTBL,program(0F800)|vector(0FED8)] [B|STACK|1] [B|TOTAL_SIZE|1] [S|OTHER|^"-change_message=information=1100,1322,1410^"] +" 5 +[EXCLUDED_FILES_Release] +[LINKAGE_ORDER_Release] +"D:\Renesas\x1key\Release\ncrt0.r30" +[GENERAL_DATA_CONFIGURATION_Release] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +[SESSION_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +"MEMORY_MAPPING_OPTIONS" "" +[GENERAL_DATA_CONFIGURATION_SESSION_Release_DefaultSession] +[SESSION_DATA_CONFIGURATION_SESSION_Release_DefaultSession] +"MEMORY_MAPPING_OPTIONS" "" +[EXT_DEBUGGER_INFO] +0 "" "" "" "" +[END] diff --git a/x1key.hws b/x1key.hws new file mode 100644 index 0000000..84b8ef9 --- /dev/null +++ b/x1key.hws @@ -0,0 +1,40 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"11.0" +[WORKSPACE_DETAILS] +"X1keyboard" "D:\Renesas\x1key" "D:\Renesas\x1key\x1key.hws" "M16C" "Renesas M16C Standard" +[SHARED_WORKSPACE_CONTROL_STATUS] +"" "" "" +"" "" "" +[PROJECTS] +"X1keyboard" "D:\Renesas\x1key" "D:\Renesas\x1key\x1key.hwp" 0 +[INFORMATION] +"[NXy[X񂪂܂" +[SCRAP] +[PROJECT_DEPENDENCY] +[WORKSPACE_PROPERTIES] +[HELP_FILES] +[GENERAL_DATA_PROJECT] +[USERMENUTOOLS] +[CUSTOMPLACEHOLDERS] +[MAKEFILE_BUILD_INFO] +"$(WORKSPDIR)\make\$(PROJECTNAME)_$(CONFIGNAME).mak" "" "$(WORKSPDIR)\make" 0 0 0 +[VD_CONFIGURATION_OPTIONS] +"ACTIVE_DESKTOP" "0" +[VD_CONFIGURATIONS] +"0" "Default1" "1" +"1" "Default2" "1" +"2" "Default3" "1" +"3" "Default4" "1" +[OPTIONS_DEBUG_TAB] +0 0 0 0 0 +[VCS] +"" "" "" 0 +[VCS_PROJECT] +[MAKEFILE_ENV_STRINGS] +[MAKEFILE_ENV_FLAGS] +1 0 0 +[MAKEFILE_CLEAN_INFO] +"" +[END] diff --git a/x1key.nav b/x1key.nav new file mode 100644 index 0000000..310617c Binary files /dev/null and b/x1key.nav differ diff --git a/x1key.tps b/x1key.tps new file mode 100644 index 0000000..a66c798 --- /dev/null +++ b/x1key.tps @@ -0,0 +1,26 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.1" +[SESSIONS_] +"DefaultSession" +[CONFIGURATIONS] +"Debug" +"Release" +[CURRENT_CONFIGURATION] +"Release" +[CURRENT_SESSION] +"DefaultSession" +[GENERAL_DATA_PROJECT] +[GENERAL_DATA_CONFIGURATION_Debug] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Debug] +"DefaultSession" +[GENERAL_DATA_CONFIGURATION_Release] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_Release] +"DefaultSession" +[GENERAL_DATA_SESSION_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession] +[GENERAL_DATA_CONFIGURATION_SESSION_Release_DefaultSession] +[END] diff --git a/x1key.tws b/x1key.tws new file mode 100644 index 0000000..c6e203e --- /dev/null +++ b/x1key.tws @@ -0,0 +1,15 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.2" +[CURRENT_PROJECT] +"X1key" +[GENERAL_DATA] +[BREAKPOINTS] +[OPEN_WORKSPACE_FILES] +"D:\Renesas\x1key\main.c" +[WORKSPACE_FILE_STATES] +"D:\Renesas\x1key\main.c" -8 -30 1724 594 1 0 +[LOADED_PROJECTS] +"X1key" +[END]