Pragnesh Patel 5ce50206ed riscv: sifive: fu540: enable all cache ways from U-Boot proper ...

Add L2 cache node to enable all cache ways from U-Boot proper.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

2020-07-03 15:09:06 +08:00

..

ae350_32.dts

riscv: dts: Add #address-cells and #size-cells in nor node

2019-12-10 08:23:10 +08:00

ae350_64.dts

riscv: dts: Add #address-cells and #size-cells in nor node

2019-12-10 08:23:10 +08:00

fu540-c000-u-boot.dtsi

riscv: sifive: fu540: enable all cache ways from U-Boot proper

2020-07-03 15:09:06 +08:00

fu540-c000.dtsi

riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux

2020-06-04 09:44:09 +08:00

fu540-hifive-unleashed-a00-ddr.dtsi

sifive: dts: fu540: Add DDR controller and phy register settings

2020-06-04 09:44:08 +08:00

hifive-unleashed-a00-u-boot.dtsi

riscv: sifive: fu540: add SPL configuration

2020-06-04 09:44:09 +08:00

hifive-unleashed-a00.dts

riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux

2020-06-04 09:44:09 +08:00

Makefile

riscv: dts: Add hifive-unleashed-a00 dts from Linux

2019-12-10 08:23:10 +08:00