Roy Zang 6d3a10f73e Change PCIE1&2 deciide logic on MPC8544DS board more readable ...

The IO port selection for MPC8544DS board:
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
 PCIE2		0x4, 0x5, 0x6, 0x7
 PCIE3		0x6, 0x7
 This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>

2009-01-13 16:32:53 -06:00

..

config.mk

Add MPC8544DS basic port board files.

2007-04-23 19:58:28 -05:00

ddr.c

Pass dimm parameters to populate populate controller options

2008-10-18 21:54:04 +02:00

law.c

rename CFG_ macros to CONFIG_SYS

2008-10-18 21:54:03 +02:00

Makefile

FSL DDR: Convert MPC8544DS to new DDR code.

2008-08-27 11:43:50 -05:00

mpc8544ds.c

Change PCIE1&2 deciide logic on MPC8544DS board more readable

2009-01-13 16:32:53 -06:00

tlb.c

rename CFG_ macros to CONFIG_SYS

2008-10-18 21:54:03 +02:00

u-boot.lds

mpc85xx: workaround old binutils bug

2008-08-10 22:41:12 +02:00