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Akshay Saraswat 234370cab4 Exynos5: clock: Update the equation to calculate PLL output frequency

According to the latest exynos5 user manual, the equation for
calculating PLL output was changed to
FOUT= MDIV x FIN/(PDIV x 2^SDIV)
earlier it was
FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
So updating the clock code accordingly.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

2013-05-21 20:17:30 +09:00

arm

Exynos5: clock: Update the equation to calculate PLL output frequency

2013-05-21 20:17:30 +09:00

avr32

lib: consolidate hang()

2013-05-01 16:41:08 -04:00

blackfin

lib: consolidate hang()

2013-05-01 16:41:08 -04:00

m68k

lib: consolidate hang()