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u-boot/board/xilinx/common
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Michal Simek fc3c6fd752 xilinx: common: Fix CONFIG_XILINX_OF_BOARD_DTB_ADDR handling for ZynqMP 
Fix bug introduced by commit listed below. It is for cases where Versal or
ZynqMP don't have DDR mapped. Later SPL was also excluded by
commit a672b9871b ("xilinx: common: Do not touch
CONFIG_XILINX_OF_BOARD_DTB_ADDR in SPL").

Fixes: 506009fc10 ("xilinx: common: Change macro handling in board_fdt_blob_setup()")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-10 13:20:27 +01:00
..
board.c
xilinx: common: Fix CONFIG_XILINX_OF_BOARD_DTB_ADDR handling for ZynqMP
2021-02-10 13:20:27 +01:00
board.h
xilinx: board: Read the whole eeprom not just offset
2020-10-27 08:13:32 +01:00
fru_ops.c
fru: ops: avoid out of bounds access
2021-01-05 11:54:53 +01:00
fru.c
xilinx: cmd: Add basic fru format generator
2020-10-27 08:13:32 +01:00
fru.h
fru: common: Record pcie/uuid fields in custom board area
2020-11-20 10:42:54 +01:00
Makefile
xilinx: cmd: Add support for FRU commands
2020-10-27 08:13:32 +01:00