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b1aef0384fcce4ae9cb8485c0df0cdc64bc0cf83
u-boot/drivers/clk
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Dario Binacchi b1aef0384f clk: ti: add custom API for memory access 
As pointed by [1] and [2], commit
d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") is wrong:
- It makes every 'reg' DT property translatable. It changes the address
  translation so that for an I2C 'reg' address you'll get back as reg
  the I2C controller address + reg value.
- The quirk must be fixed with platform code.

The clk_ti_get_reg_addr() is the platform code able to make the correct
address translation for the AM33xx clocks registers. Its implementation
was inspired by the Linux Kernel code.

[1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/
[2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-12 16:27:57 +05:30
..
altera
common: Drop asm/global_data.h from common header
2021-02-02 15:33:42 -05:00
analogbits
clk: sifive: Sync-up WRPLL library with upstream Linux
2019-07-19 14:24:51 +08:00
aspeed
clk: Update drivers to use -EINVAL
2021-04-06 16:33:19 +12:00
at91
Merge branch '2021-02-02-drop-asm_global_data-when-unused'
2021-02-15 10:16:45 -05:00
exynos
dm: treewide: Rename auto_alloc_size members to be shorter
2020-12-13 08:00:25 -07:00
imx
clk: Update drivers to use -EINVAL
2021-04-06 16:33:19 +12:00
intel
clk: x86: Correct the driver name
2021-01-30 14:25:41 -07:00
kendryte
clk: Update drivers to use -EINVAL
2021-04-06 16:33:19 +12:00
mediatek
clk: mediatek: Add MT8183 clock driver
2021-01-18 15:14:13 -05:00
meson
clk: meson-g12a: add PCIe gates
2021-04-19 16:59:33 +02:00
microchip
clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag
2021-04-08 15:37:30 +08:00
mtmips
clk: add clock driver for MediaTek MT7620 SoC
2021-01-24 21:39:26 +01:00
mvebu
clk: Update drivers to use -EINVAL
2021-04-06 16:33:19 +12:00
owl
dm: treewide: Rename auto_alloc_size members to be shorter
2020-12-13 08:00:25 -07:00
renesas
clk: renesas: Synchronize Gen2 MSTP teardown tables
2021-04-25 23:14:18 +02:00
rockchip
common: Drop asm/global_data.h from common header
2021-02-02 15:33:42 -05:00
sifive
dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()
2021-01-05 12:26:35 -07:00
sunxi
clk: sunxi: h6: Add XHCI clocks
2021-04-16 01:12:59 +01:00
tegra
common: Drop log.h from common header
2020-05-18 21:19:18 -04:00
ti
clk: ti: add custom API for memory access
2021-05-12 16:27:57 +05:30
uniphier
dm: treewide: Rename auto_alloc_size members to be shorter
2020-12-13 08:00:25 -07:00
clk_bcm6345.c
dm: treewide: Rename auto_alloc_size members to be shorter
2020-12-13 08:00:25 -07:00
clk_boston.c
dm: treewide: Rename ofdata_to_platdata() to of_to_plat()
2020-12-13 16:51:09 -07:00
clk_fixed_factor.c
dm: treewide: Rename ofdata_to_platdata() to of_to_plat()
2020-12-13 16:51:09 -07:00
clk_fixed_rate.c
clk: fixed-rate: Export driver parts for OF_PLATDATA_INST
2021-03-26 17:03:08 +13:00
clk_octeon.c
common: Drop asm/global_data.h from common header
2021-02-02 15:33:42 -05:00
clk_pic32.c
common: Drop asm/global_data.h from common header
2021-02-02 15:33:42 -05:00
clk_sandbox_ccf.c
clk: set flags in the ccf registration routines
2020-08-24 11:03:26 +02:00
clk_sandbox_test.c
clk: sandbox: Move priv/plat data to a header file
2021-03-26 17:03:08 +13:00
clk_sandbox.c
clk: sandbox: Create a special fixed-rate driver
2021-03-26 17:03:08 +13:00
clk_scmi.c
clk: add clock driver for SCMI agents
2020-09-30 11:55:23 -04:00
clk_stm32f.c
clk: clk_stm32f: migrate trace to dev and log macro
2021-01-13 09:52:58 +01:00
clk_stm32h7.c
clk: clk_stm32h7: migrate trace to dev and log macro
2021-01-13 09:52:58 +01:00
clk_stm32mp1.c
clk: stm32mp1: gets root clocks from fdt
2021-03-11 17:03:19 +01:00
clk_versal.c
clk: versal: Add support to enable clocks
2021-02-23 14:56:59 +01:00
clk_vexpress_osc.c
dm: treewide: Rename auto_alloc_size members to be shorter
2020-12-13 08:00:25 -07:00
clk_zynq.c
Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
2021-02-23 10:45:55 -05:00
clk_zynqmp.c
clk: zynqmp: Fix clk dump values
2021-03-30 12:03:24 +02:00
clk-cdce9xx.c
dm: treewide: Rename auto_alloc_size members to be shorter
2020-12-13 08:00:25 -07:00
clk-composite.c
clk: Return -ENOSYS when system call is not available
2021-04-06 16:33:19 +12:00
clk-divider.c
clk: export generic routines
2021-01-12 10:21:41 +05:30
clk-fixed-factor.c
clk: set flags in the ccf registration routines
2020-08-24 11:03:26 +02:00
clk-gate.c
clk: set flags in the ccf registration routines
2020-08-24 11:03:26 +02:00
clk-hsdk-cgu.c
clk: Update drivers to use -EINVAL
2021-04-06 16:33:19 +12:00
clk-mux.c
clk: ccf: replace the get_rate helper
2020-10-22 11:26:14 -04:00
clk-uclass.c
dm: Rename device_get_by_driver_info_idx()
2021-03-26 17:03:08 +13:00
clk.c
dm: core: Access device flags through functions
2021-01-05 12:24:41 -07:00
ics8n3qv01.c
dm: treewide: Rename auto_alloc_size members to be shorter
2020-12-13 08:00:25 -07:00
Kconfig
clk: Fix typo in Zynq Kconfig symbol description
2021-04-23 08:48:30 +02:00
Makefile
clk: Add Microchip PolarFire SoC clock driver
2021-01-18 11:06:38 +08:00
mpc83xx_clk.c
common: Drop asm/global_data.h from common header
2021-02-02 15:33:42 -05:00
mpc83xx_clk.h
common: Drop linux/bitops.h from common header
2020-05-18 21:19:23 -04:00