Files
u-boot/arch/arm/include/asm
Peng Fan ab87fc6bbd imx: dma: correct MXS_DMA_ALIGNMENT
We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"
NAND:  ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-05-26 14:14:49 +02:00
..
2015-03-05 10:29:27 +01:00
2015-02-25 07:59:50 +01:00
2015-04-29 11:19:04 +02:00
2015-04-22 12:14:55 -04:00
2014-07-04 19:57:22 +02:00
2015-03-27 16:28:58 +01:00
2014-04-08 00:15:12 +02:00
2015-04-16 11:27:15 +02:00