Pankaj Bansal
05c81d98e4
pci: layerscape: Only set EP CFG READY bit
...
In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit
of pci controller is set, so that RC can read the config space of EP.
While setting the config ready bit, LTSSM_EN bit in same register was
also inadvertently getting cleared. This restarts the link training
between RC and EP.
Update code to just set the desired CFG_READY bit (bit 0),
while leaving the other bits unchanged.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com >
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com >
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com >
2019-11-08 11:13:38 +05:30
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