Tom Rini a35747b5e1 Merge git://git.denx.de/u-boot-uniphier

2018-04-18 16:24:26 -04:00

..

aspeed

dm: Rename dev_addr..() functions

2017-06-01 07:03:01 -06:00

at91

clk: at91: clk-system: add set/get_rate operations

2018-03-16 07:30:04 -04:00

exynos

dm: Rename dev_addr..() functions

2017-06-01 07:03:01 -06:00

renesas

clk: renesas: Minor clean up of the R8A7790 clock driver

2018-04-13 23:41:44 +02:00

rockchip

rockchip: clk: rk3188: update dpll settings to make EMAC work

2018-03-28 23:44:59 +02:00

tegra

clock: implement a driver for the Tegra CAR

2016-09-27 09:11:02 -07:00

uniphier

clk: uniphier: add ethernet clock control support

2018-04-18 23:42:25 +09:00

clk_bcm6345.c

dm: Rename dev_addr..() functions

2017-06-01 07:03:01 -06:00

clk_boston.c

treewide: replace with error() with pr_err()

2017-10-04 11:59:44 -04:00

clk_fixed_rate.c

clk: Remove superfluous gd declarations

2018-01-21 10:01:02 -07:00

clk_pic32.c

wait_bit: use wait_for_bit_le32 and remove wait_for_bit

2018-01-24 12:03:43 +05:30

clk_sandbox_test.c

clk: add sandbox test for bulk API

2018-04-10 15:18:56 -04:00

clk_sandbox.c

clk: sandbox: don't check clk ID against 0

2016-06-24 17:24:35 -04:00

clk_stm32f.c

clk: clk_stm32f: Add DSI clock support

2018-03-13 21:45:37 -04:00

clk_stm32h7.c

clk: clk_stm32h7: Fix prescaler for Domain 3

2018-03-13 21:45:37 -04:00

clk_stm32mp1.c

clock: stm32mp1: add stgen clock source change support

2018-04-06 20:45:28 -04:00

clk_zynq.c

clk: zynq: Show watchdog clock rate properly

2018-03-23 09:34:43 +01:00

clk_zynqmp.c

clk: zynqmp: Add new compatible string for clock driver

2018-04-09 12:14:50 +02:00

clk-hsdk-cgu.c

ARC: HSDK: CGU: Add 'Hz' when printing clock frequency

2018-01-19 17:59:35 +03:00

clk-uclass.c

clk: fix clk_get_bulk when phandle error

2018-04-17 17:45:08 -04:00

Kconfig

clk: add driver for stm32mp1

2018-03-19 16:14:22 -04:00

Makefile

clk: add driver for stm32mp1

2018-03-19 16:14:22 -04:00