Marc Zyngier 800c83522c ARM: HYP/non-sec: add a barrier after setting SCR.NS==1 ...

A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

2014-07-28 17:06:19 +02:00

..

cpu

ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

2014-07-28 17:06:19 +02:00

dts

Merge remote-tracking branch 'u-boot-samsung/master'

2014-07-01 20:52:51 +02:00

imx-common

Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

2014-06-30 23:00:34 +02:00

include/asm

Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

2014-07-28 12:26:21 +02:00

lib

ARM: HYP/non-sec: move switch to non-sec to the last boot phase

2014-07-28 17:05:59 +02:00

config.mk

kmake: include DTB section into u-boot.bin if CONFIG_OF_EMBED enabled

2014-07-07 19:47:24 -04:00