Mingkai Hu bbc8e053ba armv8/ls1043a: Implement workaround for erratum A009660 ...

Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

2016-02-24 08:40:56 -08:00

..

arc

arc: cache - utilize IO coherency (AKA IOC) engine

2016-02-20 11:20:05 +03:00

arm

armv8/ls1043a: Implement workaround for erratum A009660

2016-02-24 08:40:56 -08:00

avr32

avr32: Use the generic bitops headers

2015-11-05 10:52:31 -05:00

blackfin

Use correct spelling of "U-Boot"

2016-02-06 12:00:59 +01:00

m68k

m68k: M54418TWR: drop board/freescale/m54418twr/config.mk

2016-01-20 10:19:34 -05:00

microblaze

Use correct spelling of "U-Boot"

2016-02-06 12:00:59 +01:00

mips

Use correct spelling of "U-Boot"

2016-02-06 12:00:59 +01:00

nds32

Use correct spelling of "U-Boot"

2016-02-06 12:00:59 +01:00

nios2

nios2: set up the debug UART early

2016-02-06 15:14:25 +08:00

openrisc

openrisc: Fix build errors

2016-01-25 10:40:01 -05:00

powerpc

powerpc/SECURE_BOOT: Add PAMU driver

2016-02-24 08:40:55 -08:00

sandbox

dm: video: test: Add tests for the video uclass

2016-01-20 19:10:16 -07:00

sh

Add more SPDX-License-Identifier tags

2016-01-19 08:31:21 -05:00

sparc

Use correct spelling of "U-Boot"

2016-02-06 12:00:59 +01:00

x86

x86: Add Intel Cougar Canyon 2 board

2016-02-21 13:42:52 +08:00

.gitignore

.gitignore: drop include/asm/proc from ignore pattern

2014-06-19 11:18:54 -04:00

Kconfig

MIPS: add initial infrastructure for device-tree files

2016-01-16 21:06:45 +01:00