Mike Nuss 54f5f056aa
PPC4xx: Denali core: Fix incorrect DDR row bits ...
The SPD detection code for the Denali memory controller used on some
ppc4xx
processors incorrectly encodes DDR0_42. With certain memory
configurations,
this can cause the bootwrapper to incorrectly calculate the installed
memory
size, because the number of row bits is wrong. This patch fixes that
encoding.
Signed-off-by: Mike Nuss <mike@terascala.com >
Signed-off-by: Stefan Roese <sr@denx.de >
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54f5f056aa