u-boot

eaw/u-boot

Files

Dinh Nguyen 532a54e652 ARM: socfpga: fix data and tag latency values for pl310 cache controller

The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

2019-03-09 17:59:13 +01:00

arc

ARC: cache: define CONFIG_SYS_CACHELINE_SIZE as ARCH_DMA_MINALIGN

2019-01-25 08:41:09 +03:00

arm

ARM: socfpga: fix data and tag latency values for pl310 cache controller

2019-03-09 17:59:13 +01:00

m68k

m68k: ColdFire mcf5441x, add eSDHC support

2018-09-16 00:01:13 +02:00

microblaze

arch: types.h: factor out fixed width typedefs to int-ll64.h