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u-boot/board/freescale
Prabhakar Kushwaha 6b50f62cc4 board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ.  It violates the IEEE specs.

So Slow MDC clock to comply IEEE specs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
..
2014-03-31 18:28:50 +02:00
2014-02-26 21:18:09 +01:00
2013-11-27 09:39:21 +01:00
2013-11-27 09:39:21 +01:00