Roger Quadros 3599774eec dra7xx: Enable USB_PHY3 32KHz clock ...

DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled
for USB1 instance in Super-Speed.

Signed-off-by: Roger Quadros <rogerq@ti.com>

2016-06-02 21:42:15 -04:00

..

arm11

ARM: cache: implement a default weak flush_cache() function

2015-08-12 20:47:48 -04:00

arm720t

ARM: ARM720t: remove empty asm/arch/hardware.h

2015-04-23 08:52:27 -04:00

arm920t

ARM: start.S: fix typo

2016-02-29 14:49:35 -05:00

arm926ejs

mx27: 16-bit wide watchdog registers

2016-03-25 14:03:28 +01:00

arm946es

ARM: start.S: fix typo

2016-02-29 14:49:35 -05:00

arm1136

ARM: start.S: fix typo

2016-02-29 14:49:35 -05:00

arm1176

ARM: start.S: fix typo

2016-02-29 14:49:35 -05:00

armv7

dra7xx: Enable USB_PHY3 32KHz clock

2016-06-02 21:42:15 -04:00

armv7m

stm32: move stm32 specific code to mach-stm32

2016-01-20 10:19:41 -05:00

armv8

arm64: rename __asm_flush_dcache_level to __asm_dcache_level

2016-05-27 15:47:55 -04:00

pxa

pxa: add support for D- and I- caches

2016-03-27 09:13:00 -04:00

sa1100

ARM: start.S: fix typo

2016-02-29 14:49:35 -05:00

Makefile

Various Makefiles: Add SPDX-License-Identifier tags

2015-11-10 09:19:52 -05:00

u-boot-spl.lds

spl: arm: Make sure to include all of the u_boot_list entries

2016-03-16 15:27:55 -04:00

u-boot.lds

arm: x86: Drop command-line code when CONFIG_CMDLINE is disabled

2016-03-22 12:16:09 -04:00