Shaohui Xie abc7d0f75c armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY ...

To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

2016-03-21 12:42:10 -07:00

..

arc

arc: cache - utilize IO coherency (AKA IOC) engine

2016-02-20 11:20:05 +03:00

arm

armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY

2016-03-21 12:42:10 -07:00

avr32

avr32: Use the generic bitops headers

2015-11-05 10:52:31 -05:00

blackfin

Use correct spelling of "U-Boot"

2016-02-06 12:00:59 +01:00

m68k

m68k: M54418TWR: drop board/freescale/m54418twr/config.mk

2016-01-20 10:19:34 -05:00

microblaze

Kconfig: Move CONFIG_FIT and related options to Kconfig

2016-03-14 19:18:07 -04:00

mips

MIPS: fix mips_cache fallback without __builtin_mips_cache

2016-03-09 11:00:40 +01:00

nds32

Use correct spelling of "U-Boot"

2016-02-06 12:00:59 +01:00

nios2

dm: Use uclass_first_device_err() where it is useful

2016-03-14 15:34:50 -06:00

openrisc

openrisc: Fix build errors

2016-01-25 10:40:01 -05:00

powerpc

Kconfig: Move CONFIG_FIT and related options to Kconfig

2016-03-14 19:18:07 -04:00

sandbox

sandbox: Fix building with LLVM

2016-03-08 15:01:46 -05:00

sh

Add more SPDX-License-Identifier tags

2016-01-19 08:31:21 -05:00

sparc

Use correct spelling of "U-Boot"

2016-02-06 12:00:59 +01:00

x86

x86: Add congatec conga-QA3/E3845-4G (Bay Trail) support

2016-03-17 10:27:27 +08:00

.gitignore

…

Kconfig

MIPS: add initial infrastructure for device-tree files

2016-01-16 21:06:45 +01:00