Marek Vasut 23e8ea901a ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 2 ...

If d != 0 after sdr_working_phase() finishes, the else branch
of the condition has no impact on anything at all, since work_end
was already set independently of the value of "d" . Zap this
useless code.

Signed-off-by: Marek Vasut <marex@denx.de>

2015-08-08 14:14:20 +02:00

..

altera

ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 2

2015-08-08 14:14:20 +02:00

fsl

drivers/ddr/fsl: Adjust bstopre value

2015-08-03 12:06:38 -07:00

marvell

arm: mvebu: a38x: Use correct PEX register access macros

2015-07-23 10:39:25 +02:00