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Rajesh Bhagat a1f95ff7d7 armv8: lsch3: Add serdes and DDR voltage setup

Adds SERDES voltage and reset SERDES lanes API and makes
enable/disable DDR controller support 0.9V API common.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

2018-01-23 11:18:12 -08:00

..

ARM: Move SYS_CACHELINE_SIZE over to Kconfig

2016-08-26 17:04:46 -04:00

arm: arm720t: Support CONFIG_SKIP_LOWLEVEL_INIT_ONLY

2017-06-09 13:39:31 -06:00

common: ep93xx: Move arch-specific declarations out of common

2017-06-05 12:31:22 -04:00

build: Drop CONFIG_SPL_BUILD guards in some cases

2018-01-10 08:05:52 -05:00

arm: Allow skipping of low-level init with I-cache on

2016-06-12 23:49:38 +02:00

build: Drop CONFIG_SPL_BUILD guards in some cases

2018-01-10 08:05:52 -05:00

arm: add save_boot_params for ARM1176

2016-11-21 14:07:31 -05:00

arm: Exercise v7_arch_cp15_set_acr even without errata fixups

2018-01-09 15:31:14 -05:00

stm32: fix STMicroelectronics copyright

2017-11-06 09:51:01 -05:00

armv8: lsch3: Add serdes and DDR voltage setup

2018-01-23 11:18:12 -08:00

arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce SPL_SYS_THUMB_BUILD

2017-03-18 20:28:01 -04:00

Remove various unused interrupt related code

2017-04-06 20:42:18 -04:00

Makefile

Various Makefiles: Add SPDX-License-Identifier tags

2015-11-10 09:19:52 -05:00

u-boot-spl.lds

binman: arm: Include the binman symbol table

2017-12-12 19:53:45 -07:00

u-boot.lds

Revert "ARM: fixed relocation using proper alignment"

2017-06-14 09:13:21 -04:00