Files
u-boot/cpu
Dave Liu 0a71c92c7e fsl-ddr: Fix power-down timing settings
1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
   We are setting the mode register MR0[A12]='1'

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:10 -06:00
..
2009-12-07 22:47:17 +01:00
2009-09-04 22:15:53 +02:00
2009-08-10 10:38:34 +02:00
2009-06-12 20:47:16 +02:00
2009-06-12 20:47:16 +02:00
2009-07-08 11:43:15 +09:00
2009-07-08 11:43:15 +09:00
2009-07-08 11:43:15 +09:00