imx6_is_bmode_from_gpr9 always returns false, because
IMX6_SRC_GPR10_BMODE is 1<<28 and gets casted to u8 on return.
This moves the function body into imx6_src_get_boot_mode, since that is the
only one using it and it is on the same abstraction level (accessing
registers directly).
Signed-off-by: Claudius Heine <ch@denx.de>
Introduce disable_ipu_clock(). This is done in preparation for
configuring the NoC registers on i.MX6QP in SPL.
Afer the NoC registers are set the IPU clocks can be disabled.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The code can be made simpler by using setbits_le32(), so switch
to it.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
We already a message indicating that U-Boot is about to jump to SPL, so
make this one a debug() to reduce code size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't need to do this and it is done (in more detail) in U-Boot proper.
Drop this to save code space.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we call spl_init() before identifying the CPU. This is not a
good idea - e.g. if bootstage is enabled then it will try to set up the
timer which works better if the CPU is identified.
Put explicit code at each entry pointer to identify the CPU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
For TPL we only need to set up the features and identify the CPU to a
basic level. Add a function to handle that.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In TPL we try to minimise code size so do not include the PCI subsystem.
We can use fixed BARs and drivers can directly program the devices that
they need.
However we do need to bind the devices on the PCI bus and without PCI this
does not ordinarily happen. As a work-around, define a fake PCI bus which
does this binding, but no other PCI operations. This is a convenient way
to ensure that we can use the same device tree for TPL, SPL and U-Boot
proper:
TPL - CONFIG_TPL_PCI is not set (no auto-config, fake PCI bus)
SPL - CONFIG_SPL_PCI is set (no auto-config but with real PCI bus)
U-Boot - CONFIG_PCI is set (full auto-config after relocation)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The x86 power unit handles power management. Support initing this device
which is modelled as a new type of system controller since there are no
operations needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the value of the timer base is used to determine whether the
timer has been set up or not. It is true that the timer is essentially
never exactly 0 when it is read. However 'time 0' may indicate the time
that the machine was reset so it is useful to be able to denote that.
Update the code to use a separate flag instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ARC fixes for v2020.01-rc2
The main change is move to DM_MMC of yet 2 another ARC boards:
AXS101 & IoTDK.
Among that we improve handling of stock-formatted SD-cards of high volume
on EM SDP as well as introduction of reset driver for HSDK which is required
for prepser reinitialization of some peripherals like USB etc.
- Add I2C clocks for i.MX6Q CCF driver
- Fix check in clk_set_default_parents()
- Managed API to get clock from device tree
- Fixes for core clock code (including sandbox regression tests)
At present some boards generate kwbimage.cfg in the source tree
during the build. This breaks buildman testing on some systems
where the source tree is read-only. Update makefile rules to
generate it in the build tree instead.
Note some other boards have the kwbimage.cfg file written in
advance, hence we need check if the file exists in the build
tree first, otherwise we fall back to one in the source tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This function needs a prototype so that tests can use it. Add one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function writes to its address so the address should not be declared
as const. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
Add the address spaces for the R5F cores in MCU domain to the ranges
property of the cbass_mcu interconnect node so that the addresses
within the R5F nodes can be translated properly by the relevant OF
address API.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
In SPL, DDR should be made available by the end of board_init_f()
so that apis in board_init_r() can use ddr. Adding support for
triggering DDR initialization from board_init_f().
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use the 3733MTs DDR configuration that is auto generated from
DDR_Regconfig tool.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.
Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that same register). Also update the dts files in the same
patch to maintain git bisectability.
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The current configuration of DDR on AM654 base board is for 1600MTs but
the file name is specified as k3-am654-base-board-ddr4-1600MHz.dtsi.
Since 1600MHz is misleading, rename it to
k3-am654-base-board-ddr4-1600MTs.dtsi
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
U-Boot cleans and invalidate L1 and L2 caches before jumping to Linux
by set/way in cleanup_before_linux(). Additionally there is a custom
hook provided to clean and invalidate L3 cache.
Unfortunately on K3 devices(having a coherent architecture), there is no
easy way to quickly clean all the cache lines for L3. The entire address
range needs to be cleaned and invalidated by Virtual Address. This can
be implemented using the L3 custom hook but it take lot of time to clean
the entire address range. In the interest of boot time this might not be
a viable solution.
The best hit is to make sure the loaded Linux image is flushed so that
the entire image is written to DDR from L3. When Linux starts running with
caches disabled the full image is available from DDR.
Reported-by: Andrew F. Davis <afd@ti.com>
Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Once the arch specific boot_prepare_linux completes, boards wants to
have a custom preparation for linux. Add support for a custom
board_prep_linux.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add usb peripheral and usb phy nodes in spl to enable SPL_DFU bootmode.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Second set of u-boot-atmel features and fixes for 2020.01 cycle
This feature set includes Eugen's work on a new tiny flexcom driver and
eeprom mac retrieval for the sam9x60-ek board.
Some drivers (clk, pinctrl, reset, ...) are necessary for reset of the
system, they should be always selected.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds default eth pinctrl for all boards.
There are two pinctrl nodes used for two scenarios:
ephy_iot_mode - for IOT boards which have only one port (PHY0)
ephy_router_mode - For routers which have more than one ports
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds default p0led status and phy0 link polling for all boards.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
All three UARTs of mt7628 are actually MediaTek's high-speed UARTs which
support baudrate up to 921600.
The high-speed UART is compatible with ns16550 when baudrate <= 115200.
Add compatible string to dtsi file so u-boot can use it when serial_mtk
driver is built in.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The UART of MT7628 has fixed 40MHz input clock so there is no need to put
clock-frequency in every dts files. Just put it into the common dtsi file.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
