From c6ab91c77edd3f831ae6ddabd4462bff983fd3fd Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 17 Sep 2022 20:28:29 -0300 Subject: [PATCH 01/12] usb: Kconfig: Fix typo in SPL_DM_USB text Change a typo in "USB host mode". Signed-off-by: Fabio Estevam --- drivers/usb/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index fd13cf31b5..3afb45d5cc 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -48,7 +48,7 @@ config DM_USB automatically probed when found on the bus. config SPL_DM_USB - bool "Enable driver model for USB host most in SPL" + bool "Enable driver model for USB host mode in SPL" depends on SPL_DM && DM_USB default n if ARCH_MVEBU default y From c34edb893aca45b81460fc6ce341b4304f08f0f3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 23 Aug 2022 19:06:50 +0200 Subject: [PATCH 02/12] usb: gadget: designware-udc: Drop the driver This driver is not used by any system and is long unmaintained, drop it. There is a DWC2 OTG driver which is maintained, see CONFIG_USB_GADGET_DWC2_OTG . Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- drivers/serial/usbtty.h | 2 - drivers/usb/gadget/Makefile | 1 - drivers/usb/gadget/designware_udc.c | 1021 --------------------------- include/usb/designware_udc.h | 183 ----- 4 files changed, 1207 deletions(-) delete mode 100644 drivers/usb/gadget/designware_udc.c delete mode 100644 include/usb/designware_udc.h diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index 0d89fc085f..e27aa368c9 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -13,8 +13,6 @@ #include #if defined(CONFIG_PPC) #include -#elif defined(CONFIG_DW_UDC) -#include #elif defined(CONFIG_CI_UDC) #include #endif diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 306dd3127f..dd09ee0195 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -42,6 +42,5 @@ else ifdef CONFIG_USB_DEVICE obj-y += core.o obj-y += ep0.o -obj-$(CONFIG_DW_UDC) += designware_udc.o endif endif diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c deleted file mode 100644 index 41a6e8cb7d..0000000000 --- a/drivers/usb/gadget/designware_udc.c +++ /dev/null @@ -1,1021 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Based on drivers/usb/gadget/omap1510_udc.c - * TI OMAP1510 USB bus interface driver - * - * (C) Copyright 2009 - * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. - */ - -#include -#include -#include -#include - -#include -#include -#include "ep0.h" -#include -#include -#include - -#define UDC_INIT_MDELAY 80 /* Device settle delay */ - -/* Some kind of debugging output... */ -#ifndef DEBUG_DWUSBTTY -#define UDCDBG(str) -#define UDCDBGA(fmt, args...) -#else -#define UDCDBG(str) serial_printf(str "\n") -#define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args) -#endif - -static struct urb *ep0_urb; -static struct usb_device_instance *udc_device; - -static struct plug_regs *const plug_regs_p = - (struct plug_regs * const)CONFIG_SYS_PLUG_BASE; -static struct udc_regs *const udc_regs_p = - (struct udc_regs * const)CONFIG_SYS_USBD_BASE; -static struct udc_endp_regs *const outep_regs_p = - &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->out_regs[0]; -static struct udc_endp_regs *const inep_regs_p = - &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->in_regs[0]; - -/* - * udc_state_transition - Write the next packet to TxFIFO. - * @initial: Initial state. - * @final: Final state. - * - * Helper function to implement device state changes. The device states and - * the events that transition between them are: - * - * STATE_ATTACHED - * || /\ - * \/ || - * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET - * || /\ - * \/ || - * STATE_POWERED - * || /\ - * \/ || - * DEVICE_RESET DEVICE_POWER_INTERRUPTION - * || /\ - * \/ || - * STATE_DEFAULT - * || /\ - * \/ || - * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET - * || /\ - * \/ || - * STATE_ADDRESSED - * || /\ - * \/ || - * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED - * || /\ - * \/ || - * STATE_CONFIGURED - * - * udc_state_transition transitions up (in the direction from STATE_ATTACHED - * to STATE_CONFIGURED) from the specified initial state to the specified final - * state, passing through each intermediate state on the way. If the initial - * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then - * no state transitions will take place. - * - * udc_state_transition also transitions down (in the direction from - * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the - * specified final state, passing through each intermediate state on the way. - * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final - * state, then no state transitions will take place. - * - * This function must only be called with interrupts disabled. - */ -static void udc_state_transition(usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial < final) { - switch (initial) { - case STATE_ATTACHED: - usbd_device_event_irq(udc_device, - DEVICE_HUB_CONFIGURED, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq(udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq(udc_device, - DEVICE_ADDRESS_ASSIGNED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0); - case STATE_CONFIGURED: - break; - default: - break; - } - } else if (initial > final) { - switch (initial) { - case STATE_CONFIGURED: - usbd_device_event_irq(udc_device, - DEVICE_DE_CONFIGURED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq(udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq(udc_device, - DEVICE_POWER_INTERRUPTION, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0); - case STATE_ATTACHED: - break; - default: - break; - } - } -} - -/* Stall endpoint */ -static void udc_stall_ep(u32 ep_num) -{ - writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, - &inep_regs_p[ep_num].endp_cntl); - - writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, - &outep_regs_p[ep_num].endp_cntl); -} - -static void *get_fifo(int ep_num, int in) -{ - u32 *fifo_ptr = (u32 *)CONFIG_SYS_FIFO_BASE; - - switch (ep_num) { - case UDC_EP3: - fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn); - /* break intentionally left out */ - - case UDC_EP1: - fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn); - /* break intentionally left out */ - - case UDC_EP0: - default: - if (in) { - fifo_ptr += - readl(&outep_regs_p[2].endp_maxpacksize) >> 16; - /* break intentionally left out */ - } else { - break; - } - - case UDC_EP2: - fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16; - /* break intentionally left out */ - } - - return (void *)fifo_ptr; -} - -static int usbgetpckfromfifo(int epNum, u8 *bufp, u32 len) -{ - u8 *fifo_ptr = (u8 *)get_fifo(epNum, 0); - u32 i, nw, nb; - u32 *wrdp; - u8 *bytp; - u32 tmp[128]; - - if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY) - return -1; - - nw = len / sizeof(u32); - nb = len % sizeof(u32); - - /* use tmp buf if bufp is not word aligned */ - if ((int)bufp & 0x3) - wrdp = (u32 *)&tmp[0]; - else - wrdp = (u32 *)bufp; - - for (i = 0; i < nw; i++) { - writel(readl(fifo_ptr), wrdp); - wrdp++; - } - - bytp = (u8 *)wrdp; - for (i = 0; i < nb; i++) { - writeb(readb(fifo_ptr), bytp); - fifo_ptr++; - bytp++; - } - readl(&outep_regs_p[epNum].write_done); - - /* copy back tmp buffer to bufp if bufp is not word aligned */ - if ((int)bufp & 0x3) - memcpy(bufp, tmp, len); - - return 0; -} - -static void usbputpcktofifo(int epNum, u8 *bufp, u32 len) -{ - u32 i, nw, nb; - u32 *wrdp; - u8 *bytp; - u8 *fifo_ptr = get_fifo(epNum, 1); - - nw = len / sizeof(int); - nb = len % sizeof(int); - wrdp = (u32 *)bufp; - for (i = 0; i < nw; i++) { - writel(*wrdp, fifo_ptr); - wrdp++; - } - - bytp = (u8 *)wrdp; - for (i = 0; i < nb; i++) { - writeb(*bytp, fifo_ptr); - fifo_ptr++; - bytp++; - } -} - -/* - * dw_write_noniso_tx_fifo - Write the next packet to TxFIFO. - * @endpoint: Endpoint pointer. - * - * If the endpoint has an active tx_urb, then the next packet of data from the - * URB is written to the tx FIFO. The total amount of data in the urb is given - * by urb->actual_length. The maximum amount of data that can be sent in any - * one packet is given by endpoint->tx_packetSize. The number of data bytes - * from this URB that have already been transmitted is given by endpoint->sent. - * endpoint->last is updated by this routine with the number of data bytes - * transmitted in this packet. - * - */ -static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance - *endpoint) -{ - struct urb *urb = endpoint->tx_urb; - int align; - - if (urb) { - u32 last; - - UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d", - urb->buffer, urb->buffer_length, urb->actual_length); - - last = min_t(u32, urb->actual_length - endpoint->sent, - endpoint->tx_packetSize); - - if (last) { - u8 *cp = urb->buffer + endpoint->sent; - - /* - * This ensures that USBD packet fifo is accessed - * - through word aligned pointer or - * - through non word aligned pointer but only - * with a max length to make the next packet - * word aligned - */ - - align = ((ulong)cp % sizeof(int)); - if (align) - last = min(last, sizeof(int) - align); - - UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d", - endpoint->sent, endpoint->tx_packetSize, last); - - usbputpcktofifo(endpoint->endpoint_address & - USB_ENDPOINT_NUMBER_MASK, cp, last); - } - endpoint->last = last; - } -} - -/* - * Handle SETUP USB interrupt. - * This function implements TRM Figure 14-14. - */ -static void dw_udc_setup(struct usb_endpoint_instance *endpoint) -{ - u8 *datap = (u8 *)&ep0_urb->device_request; - int ep_addr = endpoint->endpoint_address; - - UDCDBG("-> Entering device setup"); - usbgetpckfromfifo(ep_addr, datap, 8); - - /* Try to process setup packet */ - if (ep0_recv_setup(ep0_urb)) { - /* Not a setup packet, stall next EP0 transaction */ - udc_stall_ep(0); - UDCDBG("can't parse setup packet, still waiting for setup"); - return; - } - - /* Check direction */ - if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) - == USB_REQ_HOST2DEVICE) { - UDCDBG("control write on EP0"); - if (le16_to_cpu(ep0_urb->device_request.wLength)) { - /* Stall this request */ - UDCDBG("Stalling unsupported EP0 control write data " - "stage."); - udc_stall_ep(0); - } - } else { - - UDCDBG("control read on EP0"); - /* - * The ep0_recv_setup function has already placed our response - * packet data in ep0_urb->buffer and the packet length in - * ep0_urb->actual_length. - */ - endpoint->tx_urb = ep0_urb; - endpoint->sent = 0; - /* - * Write packet data to the FIFO. dw_write_noniso_tx_fifo - * will update endpoint->last with the number of bytes written - * to the FIFO. - */ - dw_write_noniso_tx_fifo(endpoint); - - writel(0x0, &inep_regs_p[ep_addr].write_done); - } - - udc_unset_nak(endpoint->endpoint_address); - - UDCDBG("<- Leaving device setup"); -} - -/* - * Handle endpoint 0 RX interrupt - */ -static void dw_udc_ep0_rx(struct usb_endpoint_instance *endpoint) -{ - u8 dummy[64]; - - UDCDBG("RX on EP0"); - - /* Check direction */ - if ((ep0_urb->device_request.bmRequestType - & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) { - /* - * This rx interrupt must be for a control write data - * stage packet. - * - * We don't support control write data stages. - * We should never end up here. - */ - - UDCDBG("Stalling unexpected EP0 control write " - "data stage packet"); - udc_stall_ep(0); - } else { - /* - * This rx interrupt must be for a control read status - * stage packet. - */ - UDCDBG("ACK on EP0 control read status stage packet"); - u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff; - usbgetpckfromfifo(0, dummy, len); - } -} - -/* - * Handle endpoint 0 TX interrupt - */ -static void dw_udc_ep0_tx(struct usb_endpoint_instance *endpoint) -{ - struct usb_device_request *request = &ep0_urb->device_request; - int ep_addr; - - UDCDBG("TX on EP0"); - - /* Check direction */ - if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) == - USB_REQ_HOST2DEVICE) { - /* - * This tx interrupt must be for a control write status - * stage packet. - */ - UDCDBG("ACK on EP0 control write status stage packet"); - } else { - /* - * This tx interrupt must be for a control read data - * stage packet. - */ - int wLength = le16_to_cpu(request->wLength); - - /* - * Update our count of bytes sent so far in this - * transfer. - */ - endpoint->sent += endpoint->last; - - /* - * We are finished with this transfer if we have sent - * all of the bytes in our tx urb (urb->actual_length) - * unless we need a zero-length terminating packet. We - * need a zero-length terminating packet if we returned - * fewer bytes than were requested (wLength) by the host, - * and the number of bytes we returned is an exact - * multiple of the packet size endpoint->tx_packetSize. - */ - if ((endpoint->sent == ep0_urb->actual_length) && - ((ep0_urb->actual_length == wLength) || - (endpoint->last != endpoint->tx_packetSize))) { - /* Done with control read data stage. */ - UDCDBG("control read data stage complete"); - } else { - /* - * We still have another packet of data to send - * in this control read data stage or else we - * need a zero-length terminating packet. - */ - UDCDBG("ACK control read data stage packet"); - dw_write_noniso_tx_fifo(endpoint); - - ep_addr = endpoint->endpoint_address; - writel(0x0, &inep_regs_p[ep_addr].write_done); - } - } -} - -static struct usb_endpoint_instance *dw_find_ep(int ep) -{ - int i; - - for (i = 0; i < udc_device->bus->max_endpoints; i++) { - if ((udc_device->bus->endpoint_array[i].endpoint_address & - USB_ENDPOINT_NUMBER_MASK) == ep) - return &udc_device->bus->endpoint_array[i]; - } - return NULL; -} - -/* - * Handle RX transaction on non-ISO endpoint. - * The ep argument is a physical endpoint number for a non-ISO IN endpoint - * in the range 1 to 15. - */ -static void dw_udc_epn_rx(int ep) -{ - int nbytes = 0; - struct urb *urb; - struct usb_endpoint_instance *endpoint = dw_find_ep(ep); - - if (endpoint) { - urb = endpoint->rcv_urb; - - if (urb) { - u8 *cp = urb->buffer + urb->actual_length; - - nbytes = (readl(&outep_regs_p[ep].endp_status) >> 11) & - 0xfff; - usbgetpckfromfifo(ep, cp, nbytes); - usbd_rcv_complete(endpoint, nbytes, 0); - } - } -} - -/* - * Handle TX transaction on non-ISO endpoint. - * The ep argument is a physical endpoint number for a non-ISO IN endpoint - * in the range 16 to 30. - */ -static void dw_udc_epn_tx(int ep) -{ - struct usb_endpoint_instance *endpoint = dw_find_ep(ep); - - if (!endpoint) - return; - - /* - * We need to transmit a terminating zero-length packet now if - * we have sent all of the data in this URB and the transfer - * size was an exact multiple of the packet size. - */ - if (endpoint->tx_urb && - (endpoint->last == endpoint->tx_packetSize) && - (endpoint->tx_urb->actual_length - endpoint->sent - - endpoint->last == 0)) { - /* handle zero length packet here */ - writel(0x0, &inep_regs_p[ep].write_done); - - } - - if (endpoint->tx_urb && endpoint->tx_urb->actual_length) { - /* retire the data that was just sent */ - usbd_tx_complete(endpoint); - /* - * Check to see if we have more data ready to transmit - * now. - */ - if (endpoint->tx_urb && endpoint->tx_urb->actual_length) { - /* write data to FIFO */ - dw_write_noniso_tx_fifo(endpoint); - writel(0x0, &inep_regs_p[ep].write_done); - - } else if (endpoint->tx_urb - && (endpoint->tx_urb->actual_length == 0)) { - /* udc_set_nak(ep); */ - } - } -} - -/* - * Start of public functions. - */ - -/* Called to start packet transmission. */ -int udc_endpoint_write(struct usb_endpoint_instance *endpoint) -{ - udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK); - return 0; -} - -/* Start to initialize h/w stuff */ -int udc_init(void) -{ - int i; - u32 plug_st; - - udc_device = NULL; - - UDCDBG("starting"); - - readl(&plug_regs_p->plug_pending); - - for (i = 0; i < UDC_INIT_MDELAY; i++) - udelay(1000); - - plug_st = readl(&plug_regs_p->plug_state); - writel(plug_st | PLUG_STATUS_EN, &plug_regs_p->plug_state); - - writel(~0x0, &udc_regs_p->endp_int); - writel(~0x0, &udc_regs_p->dev_int_mask); - writel(~0x0, &udc_regs_p->endp_int_mask); - -#ifndef CONFIG_USBD_HS - writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW | - DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf); -#else - writel(DEV_CONF_HS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW | - DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf); -#endif - - writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl); - - /* Clear all interrupts pending */ - writel(DEV_INT_MSK, &udc_regs_p->dev_int); - - return 0; -} - -int is_usbd_high_speed(void) -{ - return (readl(&udc_regs_p->dev_stat) & DEV_STAT_ENUM) ? 0 : 1; -} - -/* - * udc_setup_ep - setup endpoint - * Associate a physical endpoint with endpoint_instance - */ -void udc_setup_ep(struct usb_device_instance *device, - u32 ep, struct usb_endpoint_instance *endpoint) -{ - UDCDBGA("setting up endpoint addr %x", endpoint->endpoint_address); - int ep_addr; - int ep_num, ep_type; - int packet_size; - int buffer_size; - int attributes; - char *tt; - u32 endp_intmask; - - if ((ep != 0) && (udc_device->device_state < STATE_ADDRESSED)) - return; - - tt = env_get("usbtty"); - if (!tt) - tt = "generic"; - - ep_addr = endpoint->endpoint_address; - ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - - if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - /* IN endpoint */ - packet_size = endpoint->tx_packetSize; - buffer_size = packet_size * 2; - attributes = endpoint->tx_attributes; - } else { - /* OUT endpoint */ - packet_size = endpoint->rcv_packetSize; - buffer_size = packet_size * 2; - attributes = endpoint->rcv_attributes; - } - - switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) { - case USB_ENDPOINT_XFER_CONTROL: - ep_type = ENDP_EPTYPE_CNTL; - break; - case USB_ENDPOINT_XFER_BULK: - default: - ep_type = ENDP_EPTYPE_BULK; - break; - case USB_ENDPOINT_XFER_INT: - ep_type = ENDP_EPTYPE_INT; - break; - case USB_ENDPOINT_XFER_ISOC: - ep_type = ENDP_EPTYPE_ISO; - break; - } - - struct udc_endp_regs *out_p = &outep_regs_p[ep_num]; - struct udc_endp_regs *in_p = &inep_regs_p[ep_num]; - - if (!ep_addr) { - /* Setup endpoint 0 */ - buffer_size = packet_size; - - writel(readl(&in_p->endp_cntl) | ENDP_CNTL_CNAK, - &in_p->endp_cntl); - - writel(readl(&out_p->endp_cntl) | ENDP_CNTL_CNAK, - &out_p->endp_cntl); - - writel(ENDP_CNTL_CONTROL | ENDP_CNTL_FLUSH, &in_p->endp_cntl); - - writel(buffer_size / sizeof(int), &in_p->endp_bsorfn); - - writel(packet_size, &in_p->endp_maxpacksize); - - writel(ENDP_CNTL_CONTROL | ENDP_CNTL_RRDY, &out_p->endp_cntl); - - writel(packet_size | ((buffer_size / sizeof(int)) << 16), - &out_p->endp_maxpacksize); - - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - /* Setup the IN endpoint */ - writel(0x0, &in_p->endp_status); - writel((ep_type << 4) | ENDP_CNTL_RRDY, &in_p->endp_cntl); - writel(buffer_size / sizeof(int), &in_p->endp_bsorfn); - writel(packet_size, &in_p->endp_maxpacksize); - - if (!strcmp(tt, "cdc_acm")) { - if (ep_type == ENDP_EPTYPE_INT) { - /* Conf no. 1 Interface no. 0 */ - writel((packet_size << 19) | - ENDP_EPDIR_IN | (1 << 7) | - (0 << 11) | (ep_type << 5) | ep_num, - &udc_regs_p->udc_endp_reg[ep_num]); - } else { - /* Conf no. 1 Interface no. 1 */ - writel((packet_size << 19) | - ENDP_EPDIR_IN | (1 << 7) | - (1 << 11) | (ep_type << 5) | ep_num, - &udc_regs_p->udc_endp_reg[ep_num]); - } - } else { - /* Conf no. 1 Interface no. 0 */ - writel((packet_size << 19) | - ENDP_EPDIR_IN | (1 << 7) | - (0 << 11) | (ep_type << 5) | ep_num, - &udc_regs_p->udc_endp_reg[ep_num]); - } - - } else { - /* Setup the OUT endpoint */ - writel(0x0, &out_p->endp_status); - writel((ep_type << 4) | ENDP_CNTL_RRDY, &out_p->endp_cntl); - writel(packet_size | ((buffer_size / sizeof(int)) << 16), - &out_p->endp_maxpacksize); - - if (!strcmp(tt, "cdc_acm")) { - writel((packet_size << 19) | - ENDP_EPDIR_OUT | (1 << 7) | - (1 << 11) | (ep_type << 5) | ep_num, - &udc_regs_p->udc_endp_reg[ep_num]); - } else { - writel((packet_size << 19) | - ENDP_EPDIR_OUT | (1 << 7) | - (0 << 11) | (ep_type << 5) | ep_num, - &udc_regs_p->udc_endp_reg[ep_num]); - } - - } - - endp_intmask = readl(&udc_regs_p->endp_int_mask); - endp_intmask &= ~((1 << ep_num) | 0x10000 << ep_num); - writel(endp_intmask, &udc_regs_p->endp_int_mask); -} - -/* Turn on the USB connection by enabling the pullup resistor */ -void udc_connect(void) -{ - u32 plug_st, dev_cntl; - - dev_cntl = readl(&udc_regs_p->dev_cntl); - dev_cntl |= DEV_CNTL_SOFTDISCONNECT; - writel(dev_cntl, &udc_regs_p->dev_cntl); - - udelay(1000); - - dev_cntl = readl(&udc_regs_p->dev_cntl); - dev_cntl &= ~DEV_CNTL_SOFTDISCONNECT; - writel(dev_cntl, &udc_regs_p->dev_cntl); - - plug_st = readl(&plug_regs_p->plug_state); - plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); - writel(plug_st, &plug_regs_p->plug_state); -} - -/* Turn off the USB connection by disabling the pullup resistor */ -void udc_disconnect(void) -{ - u32 plug_st; - - writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl); - - plug_st = readl(&plug_regs_p->plug_state); - plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); - writel(plug_st, &plug_regs_p->plug_state); -} - -/* Switch on the UDC */ -void udc_enable(struct usb_device_instance *device) -{ - UDCDBGA("enable device %p, status %d", device, device->status); - - /* Save the device structure pointer */ - udc_device = device; - - /* Setup ep0 urb */ - if (!ep0_urb) { - ep0_urb = - usbd_alloc_urb(udc_device, udc_device->bus->endpoint_array); - } else { - serial_printf("udc_enable: ep0_urb already allocated %p\n", - ep0_urb); - } - - writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask); -} - -/** - * udc_startup - allow udc code to do any additional startup - */ -void udc_startup_events(struct usb_device_instance *device) -{ - /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ - usbd_device_event_irq(device, DEVICE_INIT, 0); - - /* - * The DEVICE_CREATE event puts the USB device in the state - * STATE_ATTACHED. - */ - usbd_device_event_irq(device, DEVICE_CREATE, 0); - - /* - * Some USB controller driver implementations signal - * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. - * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, - * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. - * The DW USB client controller has the capability to detect when the - * USB cable is connected to a powered USB bus, so we will defer the - * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later. - */ - - udc_enable(device); -} - -/* - * Plug detection interrupt handling - */ -static void dw_udc_plug_irq(void) -{ - if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) { - /* - * USB cable attached - * Turn off PHY reset bit (PLUG detect). - * Switch PHY opmode to normal operation (PLUG detect). - */ - udc_connect(); - writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask); - - UDCDBG("device attached and powered"); - udc_state_transition(udc_device->device_state, STATE_POWERED); - } else { - writel(~0x0, &udc_regs_p->dev_int_mask); - - UDCDBG("device detached or unpowered"); - udc_state_transition(udc_device->device_state, STATE_ATTACHED); - } -} - -/* - * Device interrupt handling - */ -static void dw_udc_dev_irq(void) -{ - if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) { - writel(~0x0, &udc_regs_p->endp_int_mask); - - writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH, - &inep_regs_p[0].endp_cntl); - - writel(DEV_INT_USBRESET, &udc_regs_p->dev_int); - - /* - * This endpoint0 specific register can be programmed only - * after the phy clock is initialized - */ - writel((EP0_MAX_PACKET_SIZE << 19) | ENDP_EPTYPE_CNTL, - &udc_regs_p->udc_endp_reg[0]); - - UDCDBG("device reset in progess"); - udc_state_transition(udc_device->device_state, STATE_DEFAULT); - } - - /* Device Enumeration completed */ - if (readl(&udc_regs_p->dev_int) & DEV_INT_ENUM) { - writel(DEV_INT_ENUM, &udc_regs_p->dev_int); - - /* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */ - writel(readl(&udc_regs_p->endp_int_mask) & ~0x10001, - &udc_regs_p->endp_int_mask); - - UDCDBG("default -> addressed"); - udc_state_transition(udc_device->device_state, STATE_ADDRESSED); - } - - /* The USB will be in SUSPEND in 3 ms */ - if (readl(&udc_regs_p->dev_int) & DEV_INT_INACTIVE) { - writel(DEV_INT_INACTIVE, &udc_regs_p->dev_int); - - UDCDBG("entering inactive state"); - /* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */ - } - - /* SetConfiguration command received */ - if (readl(&udc_regs_p->dev_int) & DEV_INT_SETCFG) { - writel(DEV_INT_SETCFG, &udc_regs_p->dev_int); - - UDCDBG("entering configured state"); - udc_state_transition(udc_device->device_state, - STATE_CONFIGURED); - } - - /* SetInterface command received */ - if (readl(&udc_regs_p->dev_int) & DEV_INT_SETINTF) - writel(DEV_INT_SETINTF, &udc_regs_p->dev_int); - - /* USB Suspend detected on cable */ - if (readl(&udc_regs_p->dev_int) & DEV_INT_SUSPUSB) { - writel(DEV_INT_SUSPUSB, &udc_regs_p->dev_int); - - UDCDBG("entering suspended state"); - usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); - } - - /* USB Start-Of-Frame detected on cable */ - if (readl(&udc_regs_p->dev_int) & DEV_INT_SOF) - writel(DEV_INT_SOF, &udc_regs_p->dev_int); -} - -/* - * Endpoint interrupt handling - */ -static void dw_udc_endpoint_irq(void) -{ - while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) { - - writel(ENDP0_INT_CTRLOUT, &udc_regs_p->endp_int); - - if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK) - == ENDP_STATUS_OUT_SETUP) { - dw_udc_setup(udc_device->bus->endpoint_array + 0); - writel(ENDP_STATUS_OUT_SETUP, - &outep_regs_p[0].endp_status); - - } else if ((readl(&outep_regs_p[0].endp_status) & - ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) { - dw_udc_ep0_rx(udc_device->bus->endpoint_array + 0); - writel(ENDP_STATUS_OUT_DATA, - &outep_regs_p[0].endp_status); - - } else if ((readl(&outep_regs_p[0].endp_status) & - ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) { - /* NONE received */ - } - - writel(0x0, &outep_regs_p[0].endp_status); - } - - if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) { - dw_udc_ep0_tx(udc_device->bus->endpoint_array + 0); - - writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status); - writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int); - } - - if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) { - u32 epnum = 0; - u32 ep_int = readl(&udc_regs_p->endp_int) & - ENDP_INT_NONISOOUT_MSK; - - ep_int >>= 16; - while (0x0 == (ep_int & 0x1)) { - ep_int >>= 1; - epnum++; - } - - writel((1 << 16) << epnum, &udc_regs_p->endp_int); - - if ((readl(&outep_regs_p[epnum].endp_status) & - ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) { - - dw_udc_epn_rx(epnum); - writel(ENDP_STATUS_OUT_DATA, - &outep_regs_p[epnum].endp_status); - } else if ((readl(&outep_regs_p[epnum].endp_status) & - ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) { - writel(0x0, &outep_regs_p[epnum].endp_status); - } - } - - if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOIN_MSK) { - u32 epnum = 0; - u32 ep_int = readl(&udc_regs_p->endp_int) & - ENDP_INT_NONISOIN_MSK; - - while (0x0 == (ep_int & 0x1)) { - ep_int >>= 1; - epnum++; - } - - if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) { - writel(ENDP_STATUS_IN, - &outep_regs_p[epnum].endp_status); - dw_udc_epn_tx(epnum); - - writel(ENDP_STATUS_IN, - &outep_regs_p[epnum].endp_status); - } - - writel((1 << epnum), &udc_regs_p->endp_int); - } -} - -/* - * UDC interrupts - */ -void udc_irq(void) -{ - /* - * Loop while we have interrupts. - * If we don't do this, the input chain - * polling delay is likely to miss - * host requests. - */ - while (readl(&plug_regs_p->plug_pending)) - dw_udc_plug_irq(); - - while (readl(&udc_regs_p->dev_int)) - dw_udc_dev_irq(); - - if (readl(&udc_regs_p->endp_int)) - dw_udc_endpoint_irq(); -} - -/* Flow control */ -void udc_set_nak(int epid) -{ - writel(readl(&inep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK, - &inep_regs_p[epid].endp_cntl); - - writel(readl(&outep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK, - &outep_regs_p[epid].endp_cntl); -} - -void udc_unset_nak(int epid) -{ - u32 val; - - val = readl(&inep_regs_p[epid].endp_cntl); - val &= ~ENDP_CNTL_SNAK; - val |= ENDP_CNTL_CNAK; - writel(val, &inep_regs_p[epid].endp_cntl); - - val = readl(&outep_regs_p[epid].endp_cntl); - val &= ~ENDP_CNTL_SNAK; - val |= ENDP_CNTL_CNAK; - writel(val, &outep_regs_p[epid].endp_cntl); -} diff --git a/include/usb/designware_udc.h b/include/usb/designware_udc.h deleted file mode 100644 index f716f07dd0..0000000000 --- a/include/usb/designware_udc.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. - */ - -#ifndef __DW_UDC_H -#define __DW_UDC_H - -/* - * Defines for USBD - * - * The udc_ahb controller has three AHB slaves: - * - * 1. THe UDC registers - * 2. The plug detect - * 3. The RX/TX FIFO - */ - -#define MAX_ENDPOINTS 16 - -struct udc_endp_regs { - u32 endp_cntl; - u32 endp_status; - u32 endp_bsorfn; - u32 endp_maxpacksize; - u32 reserved_1; - u32 endp_desc_point; - u32 reserved_2; - u32 write_done; -}; - -/* Endpoint Control Register definitions */ - -#define ENDP_CNTL_STALL 0x00000001 -#define ENDP_CNTL_FLUSH 0x00000002 -#define ENDP_CNTL_SNOOP 0x00000004 -#define ENDP_CNTL_POLL 0x00000008 -#define ENDP_CNTL_CONTROL 0x00000000 -#define ENDP_CNTL_ISO 0x00000010 -#define ENDP_CNTL_BULK 0x00000020 -#define ENDP_CNTL_INT 0x00000030 -#define ENDP_CNTL_NAK 0x00000040 -#define ENDP_CNTL_SNAK 0x00000080 -#define ENDP_CNTL_CNAK 0x00000100 -#define ENDP_CNTL_RRDY 0x00000200 - -/* Endpoint Satus Register definitions */ - -#define ENDP_STATUS_PIDMSK 0x0000000f -#define ENDP_STATUS_OUTMSK 0x00000030 -#define ENDP_STATUS_OUT_NONE 0x00000000 -#define ENDP_STATUS_OUT_DATA 0x00000010 -#define ENDP_STATUS_OUT_SETUP 0x00000020 -#define ENDP_STATUS_IN 0x00000040 -#define ENDP_STATUS_BUFFNAV 0x00000080 -#define ENDP_STATUS_FATERR 0x00000100 -#define ENDP_STATUS_HOSTBUSERR 0x00000200 -#define ENDP_STATUS_TDC 0x00000400 -#define ENDP_STATUS_RXPKTMSK 0x003ff800 - -struct udc_regs { - struct udc_endp_regs in_regs[MAX_ENDPOINTS]; - struct udc_endp_regs out_regs[MAX_ENDPOINTS]; - u32 dev_conf; - u32 dev_cntl; - u32 dev_stat; - u32 dev_int; - u32 dev_int_mask; - u32 endp_int; - u32 endp_int_mask; - u32 reserved_3[0x39]; - u32 reserved_4; /* offset 0x500 */ - u32 udc_endp_reg[MAX_ENDPOINTS]; -}; - -/* Device Configuration Register definitions */ - -#define DEV_CONF_HS_SPEED 0x00000000 -#define DEV_CONF_LS_SPEED 0x00000002 -#define DEV_CONF_FS_SPEED 0x00000003 -#define DEV_CONF_REMWAKEUP 0x00000004 -#define DEV_CONF_SELFPOW 0x00000008 -#define DEV_CONF_SYNCFRAME 0x00000010 -#define DEV_CONF_PHYINT_8 0x00000020 -#define DEV_CONF_PHYINT_16 0x00000000 -#define DEV_CONF_UTMI_BIDIR 0x00000040 -#define DEV_CONF_STATUS_STALL 0x00000080 - -/* Device Control Register definitions */ - -#define DEV_CNTL_RESUME 0x00000001 -#define DEV_CNTL_TFFLUSH 0x00000002 -#define DEV_CNTL_RXDMAEN 0x00000004 -#define DEV_CNTL_TXDMAEN 0x00000008 -#define DEV_CNTL_DESCRUPD 0x00000010 -#define DEV_CNTL_BIGEND 0x00000020 -#define DEV_CNTL_BUFFILL 0x00000040 -#define DEV_CNTL_TSHLDEN 0x00000080 -#define DEV_CNTL_BURSTEN 0x00000100 -#define DEV_CNTL_DMAMODE 0x00000200 -#define DEV_CNTL_SOFTDISCONNECT 0x00000400 -#define DEV_CNTL_SCALEDOWN 0x00000800 -#define DEV_CNTL_BURSTLENU 0x00010000 -#define DEV_CNTL_BURSTLENMSK 0x00ff0000 -#define DEV_CNTL_TSHLDLENU 0x01000000 -#define DEV_CNTL_TSHLDLENMSK 0xff000000 - -/* Device Status Register definitions */ - -#define DEV_STAT_CFG 0x0000000f -#define DEV_STAT_INTF 0x000000f0 -#define DEV_STAT_ALT 0x00000f00 -#define DEV_STAT_SUSP 0x00001000 -#define DEV_STAT_ENUM 0x00006000 -#define DEV_STAT_ENUM_SPEED_HS 0x00000000 -#define DEV_STAT_ENUM_SPEED_FS 0x00002000 -#define DEV_STAT_ENUM_SPEED_LS 0x00004000 -#define DEV_STAT_RXFIFO_EMPTY 0x00008000 -#define DEV_STAT_PHY_ERR 0x00010000 -#define DEV_STAT_TS 0xf0000000 - -/* Device Interrupt Register definitions */ - -#define DEV_INT_MSK 0x0000007f -#define DEV_INT_SETCFG 0x00000001 -#define DEV_INT_SETINTF 0x00000002 -#define DEV_INT_INACTIVE 0x00000004 -#define DEV_INT_USBRESET 0x00000008 -#define DEV_INT_SUSPUSB 0x00000010 -#define DEV_INT_SOF 0x00000020 -#define DEV_INT_ENUM 0x00000040 - -/* Endpoint Interrupt Register definitions */ - -#define ENDP0_INT_CTRLIN 0x00000001 -#define ENDP1_INT_BULKIN 0x00000002 -#define ENDP_INT_NONISOIN_MSK 0x0000AAAA -#define ENDP2_INT_BULKIN 0x00000004 -#define ENDP0_INT_CTRLOUT 0x00010000 -#define ENDP1_INT_BULKOUT 0x00020000 -#define ENDP2_INT_BULKOUT 0x00040000 -#define ENDP_INT_NONISOOUT_MSK 0x55540000 - -/* Endpoint Register definitions */ -#define ENDP_EPDIR_OUT 0x00000000 -#define ENDP_EPDIR_IN 0x00000010 -#define ENDP_EPTYPE_CNTL 0x0 -#define ENDP_EPTYPE_ISO 0x1 -#define ENDP_EPTYPE_BULK 0x2 -#define ENDP_EPTYPE_INT 0x3 - -/* - * Defines for Plug Detect - */ - -struct plug_regs { - u32 plug_state; - u32 plug_pending; -}; - -/* Plug State Register definitions */ -#define PLUG_STATUS_EN 0x1 -#define PLUG_STATUS_ATTACHED 0x2 -#define PLUG_STATUS_PHY_RESET 0x4 -#define PLUG_STATUS_PHY_MODE 0x8 - -/* - * Defines for UDC FIFO (Slave Mode) - */ -struct udcfifo_regs { - u32 *fifo_p; -}; - -/* - * UDC endpoint definitions - */ -#define UDC_EP0 0 -#define UDC_EP1 1 -#define UDC_EP2 2 -#define UDC_EP3 3 - -#endif /* __DW_UDC_H */ From 1581f1737851f7e44dcf1eebbc52bdd6f1f7c9ca Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 9 Sep 2022 14:42:11 -0700 Subject: [PATCH 03/12] arm: dts: imx8mp-venice-gw74xx: add dsa phy handles to u-boot dtsi The upstream Linux DSA drivers do not require phy-handle nodes in the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and the mdio nodes to the u-boot.dtsi file so that future dts file syncrhonization between Linux and U-Boot don't break networking. Fixes: e0caa84ca685 ("imx8mp: synchronise device tree with linux") Signed-off-by: Tim Harvey --- arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi index 920246d577..caf5d3a7f6 100644 --- a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi @@ -162,6 +162,65 @@ u-boot,dm-spl; }; +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + lan1: port@0 { + phy-handle = <&sw_phy0>; + }; + + lan2: port@1 { + phy-handle = <&sw_phy1>; + }; + + lan3: port@2 { + phy-handle = <&sw_phy2>; + }; + + lan4: port@3 { + phy-handle = <&sw_phy3>; + }; + + lan5: port@4 { + phy-handle = <&sw_phy4>; + }; + }; + + mdios { + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0>; + compatible = "microchip,ksz-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sw_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + sw_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + sw_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + sw_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + + sw_phy4: ethernet-phy@4 { + reg = <0x4>; + }; + }; + }; +}; + &usdhc2 { assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; assigned-clock-rates = <400000000>; From 9bf0cbf396beaf3257698f672207ab7849134618 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 9 Sep 2022 14:42:38 -0700 Subject: [PATCH 04/12] arm: dts: imx8mm-venice-gw7901: add dsa phy handles to u-boot dtsi The upstream Linux DSA drivers do not require phy-handle nodes in the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and the mdio nodes to the u-boot.dtsi file so that future dts file syncrhonization between Linux and U-Boot don't break networking. Fixes: 24a7a3c1c042 ("imx8mm: synchronise device tree with linux") Signed-off-by: Tim Harvey --- arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi index 11c773bb70..dc99e7b9ac 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi @@ -129,6 +129,57 @@ phy-reset-post-delay = <1>; }; +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + lan1: port@0 { + phy-handle = <&sw_phy0>; + }; + + lan2: port@1 { + phy-handle = <&sw_phy1>; + }; + + lan3: port@2 { + phy-handle = <&sw_phy2>; + }; + + lan4: port@3 { + phy-handle = <&sw_phy3>; + }; + }; + + mdios { + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0>; + compatible = "microchip,ksz-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sw_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + sw_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + sw_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + sw_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + }; + }; +}; + &pinctrl_fec1 { u-boot,dm-spl; }; From fdf6bbb260c36bb54826bffb4dd4d62b90c3cede Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 19 Sep 2022 21:37:07 +0200 Subject: [PATCH 05/12] ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlock Pull this LPGPR unlock into common code, since it is used in multiple systems already. Signed-off-by: Marek Vasut --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 5 +++++ arch/arm/mach-imx/imx8m/soc.c | 12 ++++++++++++ .../imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c | 17 ----------------- .../dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c | 17 ----------------- board/menlo/mx8menlo/mx8menlo.c | 17 ----------------- 5 files changed, 17 insertions(+), 51 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index ff3b9ddd9f..29d5baaab8 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -27,6 +27,7 @@ #define IOMUXC_GPR_BASE_ADDR 0x30340000 #define OCOTP_BASE_ADDR 0x30350000 #define ANATOP_BASE_ADDR 0x30360000 +#define SNVS_BASE_ADDR 0x30370000 #define CCM_BASE_ADDR 0x30380000 #define SRC_BASE_ADDR 0x30390000 #define GPC_BASE_ADDR 0x303A0000 @@ -113,6 +114,10 @@ #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) +#define SNVS_LPSR 0x4c +#define SNVS_LPLVDR 0x64 +#define SNVS_LPPGDR_INIT 0x41736166 + struct iomuxc_gpr_base_regs { u32 gpr[47]; }; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index d115b25a5b..5739546c02 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -544,6 +544,16 @@ static int imx8m_check_clock(void *ctx, struct event *event) } EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock); +static void imx8m_setup_snvs(void) +{ + /* Enable SNVS clock */ + clock_enable(CCGR_SNVS, 1); + /* Initialize glitch detect */ + writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR); + /* Clear interrupt status */ + writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); +} + int arch_cpu_init(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -594,6 +604,8 @@ int arch_cpu_init(void) writel(0x200, &ocotp->ctrl_clr); } + imx8m_setup_snvs(); + return 0; } diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index 6dc4e6a9a2..dc0883002c 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -34,22 +34,6 @@ int board_phys_sdram_size(phys_size_t *size) return 0; } -/* IMX8M SNVS registers needed for the bootcount functionality */ -#define SNVS_BASE_ADDR 0x30370000 -#define SNVS_LPSR 0x4c -#define SNVS_LPLVDR 0x64 -#define SNVS_LPPGDR_INIT 0x41736166 - -static void setup_snvs(void) -{ - /* Enable SNVS clock */ - clock_enable(CCGR_SNVS, 1); - /* Initialize glitch detect */ - writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR); - /* Clear interrupt status */ - writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); -} - static void setup_mac_address(void) { unsigned char enetaddr[6]; @@ -99,7 +83,6 @@ static void setup_boot_device(void) int board_init(void) { - setup_snvs(); return 0; } diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 6f06daf86f..9d8e19d994 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -37,22 +37,6 @@ int board_phys_sdram_size(phys_size_t *size) return 0; } -/* IMX8M SNVS registers needed for the bootcount functionality */ -#define SNVS_BASE_ADDR 0x30370000 -#define SNVS_LPSR 0x4c -#define SNVS_LPLVDR 0x64 -#define SNVS_LPPGDR_INIT 0x41736166 - -static void setup_snvs(void) -{ - /* Enable SNVS clock */ - clock_enable(CCGR_SNVS, 1); - /* Initialize glitch detect */ - writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR); - /* Clear interrupt status */ - writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); -} - static void setup_eqos(void) { struct iomuxc_gpr_base_regs *gpr = @@ -145,7 +129,6 @@ int board_init(void) { setup_eqos(); setup_fec(); - setup_snvs(); return 0; } diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c index 9d3708a363..61fc4ec85f 100644 --- a/board/menlo/mx8menlo/mx8menlo.c +++ b/board/menlo/mx8menlo/mx8menlo.c @@ -12,24 +12,7 @@ #include #include -#define SNVS_BASE_ADDR 0x30370000 -#define SNVS_LPSR 0x4c -#define SNVS_LPLVDR 0x64 -#define SNVS_LPPGDR_INIT 0x41736166 - -static void setup_snvs(void) -{ - /* Enable SNVS clock */ - clock_enable(CCGR_SNVS, 1); - /* Initialize glitch detect */ - writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR); - /* Clear interrupt status */ - writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); -} - void board_early_init(void) { init_uart_clk(1); - - setup_snvs(); } From 13982ced2ccce0838afb6db87f05b2cd74355b56 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 Jul 2022 23:50:43 +0200 Subject: [PATCH 06/12] cmd: fdt: Add support for reading stringlist property values The fdt command currently handles stringlists as strings in 'fdt get value' subcommand. Since strings in FDT stringlists are separated by '\0', only the first value gets inserted into the environment variable passed to the 'fdt get value' command. Example, consider the following DT snippet: / { compatible = "foo", "bar" }; The following command only reports the first string in stringlist: => fdt get value var / compatible ; print var foo It is not possible to assign list of null-terminated strings into U-Boot environment variable. Add optional 'index' parameter to the subcommand 'fdt get value []' which lets user specify which string within the stringlist should be assigned into the 'var' variable. The default value of 'index' is 0 in case it is not present. This way the 'fdt' command API does not change and existing scripts are not broken. The following command now reports the Nth string in stringlist, counting from zero: => fdt get value var / compatible 1 ; print var bar Signed-off-by: Marek Vasut Cc: Heinrich Schuchardt Cc: Simon Glass Cc: Tom Rini --- cmd/fdt.c | 34 ++++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/cmd/fdt.c b/cmd/fdt.c index 842e6cb634..6fbd9205d3 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -48,11 +48,27 @@ void set_working_fdt_addr(ulong addr) /* * Get a value from the fdt and format it to be set in the environment */ -static int fdt_value_env_set(const void *nodep, int len, const char *var) +static int fdt_value_env_set(const void *nodep, int len, + const char *var, int index) { - if (is_printable_string(nodep, len)) - env_set(var, (void *)nodep); - else if (len == 4) { + if (is_printable_string(nodep, len)) { + const char *nodec = (const char *)nodep; + int i; + + /* + * Iterate over all members in stringlist and find the one at + * offset $index. If no such index exists, indicate failure. + */ + for (i = 0; i < len; i += strlen(nodec) + 1) { + if (index-- > 0) + continue; + + env_set(var, nodec + i); + return 0; + } + + return 1; + } else if (len == 4) { char buf[11]; sprintf(buf, "0x%08X", fdt32_to_cpu(*(fdt32_t *)nodep)); @@ -426,10 +442,14 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return 0; } else if (nodep && len > 0) { if (subcmd[0] == 'v') { + int index = 0; int ret; + if (argc == 7) + index = simple_strtoul(argv[6], NULL, 10); + ret = fdt_value_env_set(nodep, len, - var); + var, index); if (ret != 0) return ret; } else if (subcmd[0] == 'a') { @@ -1085,7 +1105,9 @@ static char fdt_help_text[] = "fdt resize [] - Resize fdt to size + padding to 4k addr + some optional if needed\n" "fdt print [] - Recursive print starting at \n" "fdt list [] - Print one level starting at \n" - "fdt get value - Get and store in \n" + "fdt get value [] - Get and store in \n" + " In case of stringlist property, use optional \n" + " to select string within the stringlist. Default is 0.\n" "fdt get name - Get name of node and store in \n" "fdt get addr - Get start address of and store in \n" "fdt get size [] - Get size of [] or num nodes and store in \n" From d64af08f19132c85422b442657920f4024b5caf7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 17 Sep 2022 09:01:19 -0600 Subject: [PATCH 07/12] binman: Get futility by building it A binary download is not great, since it depends on libraries being present in the system. Build futility from source instead. Signed-off-by: Simon Glass --- tools/binman/bintool.py | 10 +++++++--- tools/binman/btool/futility.py | 17 +++++++++++++---- 2 files changed, 20 insertions(+), 7 deletions(-) diff --git a/tools/binman/bintool.py b/tools/binman/bintool.py index 032179a99d..a582d9d344 100644 --- a/tools/binman/bintool.py +++ b/tools/binman/bintool.py @@ -319,7 +319,7 @@ class Bintool: return result.stdout @classmethod - def build_from_git(cls, git_repo, make_target, bintool_path): + def build_from_git(cls, git_repo, make_target, bintool_path, flags=None): """Build a bintool from a git repo This clones the repo in a temporary directory, builds it with 'make', @@ -330,6 +330,7 @@ class Bintool: make_target (str): Target to pass to 'make' to build the tool bintool_path (str): Relative path of the tool in the repo, after build is complete + flags (list of str): Flags or variables to pass to make, or None Returns: tuple: @@ -341,8 +342,11 @@ class Bintool: print(f"- clone git repo '{git_repo}' to '{tmpdir}'") tools.run('git', 'clone', '--depth', '1', git_repo, tmpdir) print(f"- build target '{make_target}'") - tools.run('make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}', - make_target) + cmd = ['make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}', + make_target] + if flags: + cmd += flags + tools.run(*cmd) fname = os.path.join(tmpdir, bintool_path) if not os.path.exists(fname): print(f"- File '{fname}' was not produced") diff --git a/tools/binman/btool/futility.py b/tools/binman/btool/futility.py index 75a05c2ac6..04c9aefe9b 100644 --- a/tools/binman/btool/futility.py +++ b/tools/binman/btool/futility.py @@ -160,8 +160,17 @@ class Bintoolfutility(bintool.Bintool): Raises: Valuerror: Fetching could not be completed """ - if method != bintool.FETCH_BIN: + if method != bintool.FETCH_BUILD: return None - fname, tmpdir = self.fetch_from_drive( - '1hdsInzsE4aJbmBeJ663kYgjOQyW1I-E0') - return fname, tmpdir + + # The Chromium OS repo is here: + # https://chromium.googlesource.com/chromiumos/platform/vboot_reference/ + # + # Unfortunately this requires logging in and obtaining a line for the + # .gitcookies file. So use a mirror instead. + result = self.build_from_git( + 'https://github.com/sjg20/vboot_reference.git', + 'all', + 'build/futility/futility', + flags=['USE_FLASHROM=0']) + return result From 8b9d90d6349f99cb9d95584e65dc04f080720fbd Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 13 Aug 2022 09:03:10 -0300 Subject: [PATCH 08/12] mx8m: csf.sh: Fix the calculation of fit_block_size When running the script to sign SPL/U-Boot on a kontron-sl-mx8mm board, the fit_block_size was calculated as 0x1000 instead of 0x1020. Add an extra parenthesis pair to fix it. Signed-off-by: Fabio Estevam Reviewed-by: Marek Vasut --- doc/imx/habv4/csf_examples/mx8m/csf.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh index 6898513be5..7d267a7218 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf.sh +++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh @@ -40,7 +40,7 @@ dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc # fitImage tree fit_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SYS_TEXT_BASE=/ s@.*=@@p" .config) - $(sed -n "/CONFIG_FIT_EXTERNAL_OFFSET=/ s@.*=@@p" .config) - 0x200 - 0x40)) ) fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset)) -fit_block_size=$(printf "0x%x" $(( ( $(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1) + 0x20 )) ) +fit_block_size=$(printf "0x%x" $(( ( ($(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) ) sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\", \\\\@" csf_fit.tmp # U-Boot From 1d8f4c85e3c04f596b0464542221b3507af0014e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 23 Aug 2022 22:09:34 -0300 Subject: [PATCH 09/12] kontron-sl-mx8mm: Let CONFIG_SPL_FIT_IMAGE_TINY be selected When CONFIG_IMX_HAB is selected the 'hab_status' command reports several error events, indicating that the BootROM failed to authenticate the SPL. After inspecting the content of the memory location that corresponds to the DTB load address, the content did not match with the DTB binary, showing that some kind of memory corruption/overlap occurred. Letting the CONFIG_SPL_FIT_IMAGE_TINY option to be selected causes the DTB to be properly placed into RAM and no more overlap occurs. With this change, the 'hab_status' command returns no more error events, which indicates that the BootROM succeeded to authenticate the SPL. Signed-off-by: Fabio Estevam Reviewed-by: Frieder Schrempf --- configs/kontron-sl-mx8mm_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 5387f65926..f8589b010c 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -39,7 +39,6 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 -# CONFIG_SPL_FIT_IMAGE_TINY is not set CONFIG_SPL_I2C=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y From c2bdf02c9d40da7154fea46b7d10343fe9f14209 Mon Sep 17 00:00:00 2001 From: Nikita Shubin Date: Fri, 2 Sep 2022 11:47:39 +0300 Subject: [PATCH 10/12] spl: introduce SPL_XIP to config U-Boot and SPL don't necessary share the same location, so we might end with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory. In case of non XIP boot mode, we rely on such variables as "hart_lottery" and "available_harts_lock" which we use as atomics. The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL, so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes. This adds an option special for SPL to behave it in XIP manner and we don't use hart_lottery and available_harts_lock, during start proccess. Signed-off-by: Nikita Shubin Reviewed-by: Rick Chen --- arch/riscv/Kconfig | 7 +++++++ arch/riscv/cpu/cpu.c | 2 +- arch/riscv/cpu/start.S | 4 ++-- arch/riscv/include/asm/global_data.h | 2 +- arch/riscv/lib/asm-offsets.c | 2 +- arch/riscv/lib/smp.c | 2 +- configs/ae350_rv32_spl_xip_defconfig | 2 +- configs/ae350_rv64_spl_xip_defconfig | 2 +- 8 files changed, 15 insertions(+), 8 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 78e964db12..c042506a64 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -269,6 +269,13 @@ config XIP from a NOR flash memory without copying the code to ram. Say yes here if U-Boot boots from flash directly. +config SPL_XIP + bool "Enable XIP mode for SPL" + help + If SPL starts in read-only memory (XIP for example) then we shouldn't + rely on lock variables (for example hart_lottery and available_harts_lock), + this affects only SPL, other stages should proceed as non-XIP. + config SHOW_REGS bool "Show registers on unhandled exception" diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 3ffcbbd23f..0f323b26b3 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -19,7 +19,7 @@ * The variables here must be stored in the data section since they are used * before the bss section is available. */ -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) u32 hart_lottery __section(".data") = 0; /* diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index b7f21ab63e..de9d078da1 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -122,7 +122,7 @@ call_board_init_f_0: call_harts_early_init: jal harts_early_init -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) /* * Pick hart to initialize global data and run U-Boot. The other harts * wait for initialization to complete. @@ -152,7 +152,7 @@ call_harts_early_init: /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp) -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) la t0, available_harts_lock amoswap.w.rl zero, zero, 0(t0) diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 095484a635..b3c79e1760 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -27,7 +27,7 @@ struct arch_global_data { #if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; #endif -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) ulong available_harts; #endif }; diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index f1fe089b3d..c4f48c8373 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -16,7 +16,7 @@ int main(void) { DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr)); -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); #endif diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ba992100ad..f8b756291f 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -45,7 +45,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) continue; } -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) /* skip if hart is not available */ if (!(gd->arch.available_harts & (1 << reg))) continue; diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index c7b6ea4730..67c1e35c55 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -11,7 +11,7 @@ CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_AX25_AE350=y CONFIG_RISCV_SMODE=y -CONFIG_XIP=y +CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00 diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index a197c97736..baee9bfe4a 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -12,7 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_AX25_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y -CONFIG_XIP=y +CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70 From e0465f80bd33f239612ee9f0ee7b6cf13d2f5b4d Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 21 Sep 2022 14:34:54 +0800 Subject: [PATCH 11/12] riscv: Introduce AVAILABLE_HARTS In SMP all harts will register themself in available_hart during start up. Then main hart will send IPI to other harts according to this variables. But this mechanism may not guarantee that all other harts can jump to next stage. When main hart is sending IPI to other hart according to available_harts, but other harts maybe still not finish the registration. Then the SMP booting will miss some harts finally. So let it become an option and it will be enabled by default. Please refer to the discussion: https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 7 +++++++ arch/riscv/cpu/cpu.c | 2 ++ arch/riscv/cpu/start.S | 13 ++++++++----- arch/riscv/include/asm/global_data.h | 2 ++ arch/riscv/lib/asm-offsets.c | 2 ++ arch/riscv/lib/smp.c | 2 ++ 6 files changed, 23 insertions(+), 5 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c042506a64..32a90b83b5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -276,6 +276,13 @@ config SPL_XIP rely on lock variables (for example hart_lottery and available_harts_lock), this affects only SPL, other stages should proceed as non-XIP. +config AVAILABLE_HARTS + bool "Send IPI by available harts" + default y + help + By default, IPI sending mechanism will depend on available_harts. + If disable this, it will send IPI by CPUs node numbers of device tree. + config SHOW_REGS bool "Show registers on unhandled exception" diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 0f323b26b3..52ab02519f 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -22,12 +22,14 @@ #if !CONFIG_IS_ENABLED(XIP) u32 hart_lottery __section(".data") = 0; +#ifdef CONFIG_AVAILABLE_HARTS /* * The main hart running U-Boot has acquired available_harts_lock until it has * finished initialization of global data. */ u32 available_harts_lock = 1; #endif +#endif static inline bool supports_extension(char ext) { diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index de9d078da1..4687bca3c9 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -153,21 +153,23 @@ call_harts_early_init: SREG tp, GD_BOOT_HART(gp) #if !CONFIG_IS_ENABLED(XIP) +#ifdef CONFIG_AVAILABLE_HARTS la t0, available_harts_lock amoswap.w.rl zero, zero, 0(t0) +#endif wait_for_gd_init: - la t0, available_harts_lock - li t1, 1 -1: amoswap.w.aq t1, t1, 0(t0) - bnez t1, 1b - /* * Set the global data pointer only when gd_t has been initialized. * This was already set by arch_setup_gd on the boot hart, but all other * harts' global data pointers gets set here. */ mv gp, s0 +#ifdef CONFIG_AVAILABLE_HARTS + la t0, available_harts_lock + li t1, 1 +1: amoswap.w.aq t1, t1, 0(t0) + bnez t1, 1b /* register available harts in the available_harts mask */ li t1, 1 @@ -177,6 +179,7 @@ wait_for_gd_init: SREG t2, GD_AVAILABLE_HARTS(gp) amoswap.w.rl zero, zero, 0(t0) +#endif /* * Continue on hart lottery winner, others branch to diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index b3c79e1760..858594a191 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -28,8 +28,10 @@ struct arch_global_data { struct ipi_data ipi[CONFIG_NR_CPUS]; #endif #if !CONFIG_IS_ENABLED(XIP) +#ifdef CONFIG_AVAILABLE_HARTS ulong available_harts; #endif +#endif }; #include diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index c4f48c8373..452dfcea97 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -17,7 +17,9 @@ int main(void) DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr)); #if !CONFIG_IS_ENABLED(XIP) +#ifdef CONFIG_AVAILABLE_HARTS DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); +#endif #endif return 0; diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index f8b756291f..c0f65af191 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -46,9 +46,11 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) } #if !CONFIG_IS_ENABLED(XIP) +#ifdef CONFIG_AVAILABLE_HARTS /* skip if hart is not available */ if (!(gd->arch.available_harts & (1 << reg))) continue; +#endif #endif gd->arch.ipi[reg].addr = ipi->addr; From 3c1ec13317292933fd01d9c60aae3ff1d5bc171e Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 21 Sep 2022 14:34:55 +0800 Subject: [PATCH 12/12] riscv: ae350: Disable AVAILABLE_HARTS Disable AVAILABLE_HARTS mechanism to make sure that all harts can boot to Kernel shell successfully. Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv64_spl_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 9b79cc41b5..1cc98a2653 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -48,3 +48,4 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_AVAILABLE_HARTS is not set diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 4c33ca2383..4318300300 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -49,3 +49,4 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_ATCSPI200_SPI=y # CONFIG_BINMAN_FDT is not set +# CONFIG_AVAILABLE_HARTS is not set