* Patch by Leif Lindholm, 23 Sep 2004:
add support for the AMD db1550 board * Patch by Travis Sawyer, 15 Sep 2004: Add CONFIG_SERIAL_MULTI support for ppc4xx, update README.serial_multi
This commit is contained in:
wdenk
@@ -132,6 +132,27 @@ static __inline__ int au_ffs(int x)
|
||||
#define CP0_DEBUG $23
|
||||
|
||||
/* SDRAM Controller */
|
||||
#ifdef CONFIG_AU1550
|
||||
|
||||
#define MEM_SDMODE0 0xB4000800
|
||||
#define MEM_SDMODE1 0xB4000808
|
||||
#define MEM_SDMODE2 0xB4000810
|
||||
|
||||
#define MEM_SDADDR0 0xB4000820
|
||||
#define MEM_SDADDR1 0xB4000828
|
||||
#define MEM_SDADDR2 0xB4000830
|
||||
|
||||
#define MEM_SDCONFIGA 0xB4000840
|
||||
#define MEM_SDCONFIGB 0xB4000848
|
||||
#define MEM_SDPRECMD 0xB40008c0
|
||||
#define MEM_SDAUTOREF 0xB40008c8
|
||||
|
||||
#define MEM_SDWRMD0 0xB4000880
|
||||
#define MEM_SDWRMD1 0xB4000888
|
||||
#define MEM_SDWRMD2 0xB4000890
|
||||
|
||||
#else /* CONFIG_AU1550 */
|
||||
|
||||
#define MEM_SDMODE0 0xB4000000
|
||||
#define MEM_SDMODE1 0xB4000004
|
||||
#define MEM_SDMODE2 0xB4000008
|
||||
@@ -148,6 +169,8 @@ static __inline__ int au_ffs(int x)
|
||||
#define MEM_SDWRMD1 0xB4000028
|
||||
#define MEM_SDWRMD2 0xB400002C
|
||||
|
||||
#endif /* CONFIG_AU1550 */
|
||||
|
||||
#define MEM_SDSLEEP 0xB4000030
|
||||
#define MEM_SDSMCKE 0xB4000034
|
||||
|
||||
@@ -474,6 +497,8 @@ static __inline__ int au_ffs(int x)
|
||||
#define AU1500_ETH0_BASE 0xB1500000
|
||||
#define AU1500_ETH1_BASE 0xB1510000
|
||||
#define AU1100_ETH0_BASE 0xB0500000
|
||||
#define AU1550_ETH0_BASE 0xB0500000
|
||||
#define AU1550_ETH1_BASE 0xB0510000
|
||||
|
||||
/* 4 byte offsets from AU1000_ETH_BASE */
|
||||
#define MAC_CONTROL 0x0
|
||||
@@ -523,6 +548,8 @@ static __inline__ int au_ffs(int x)
|
||||
#define AU1500_MAC0_ENABLE 0xB1520000
|
||||
#define AU1500_MAC1_ENABLE 0xB1520004
|
||||
#define AU1100_MAC0_ENABLE 0xB0520000
|
||||
#define AU1550_MAC0_ENABLE 0xB0520000
|
||||
#define AU1550_MAC1_ENABLE 0xB0520004
|
||||
|
||||
#define MAC_EN_CLOCK_ENABLE (1<<0)
|
||||
#define MAC_EN_RESET0 (1<<1)
|
||||
@@ -979,6 +1006,15 @@ static __inline__ int au_ffs(int x)
|
||||
#define AC97C_RS (1<<1)
|
||||
#define AC97C_CE (1<<0)
|
||||
|
||||
#define DB1000_BCSR_ADDR 0xAE000000
|
||||
#define DB1550_BCSR_ADDR 0xAF000000
|
||||
|
||||
#ifdef CONFIG_DBAU1550
|
||||
#define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR
|
||||
#else
|
||||
#define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AU1500
|
||||
/* Au1500 PCI Controller */
|
||||
#define Au1500_CFG_BASE 0xB4005000 /* virtual, kseg0 addr */
|
||||
|
||||
@@ -42,10 +42,15 @@
|
||||
#ifdef CONFIG_DBAU1500
|
||||
#define CONFIG_AU1500 1
|
||||
#else
|
||||
#ifdef CONFIG_DBAU1550
|
||||
/* Cabernet */
|
||||
#define CONFIG_AU1550 1
|
||||
#else
|
||||
#error "No valid board set"
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
|
||||
|
||||
@@ -66,23 +71,34 @@
|
||||
"bootfile=/tftpboot/vmlinux.srec\0" \
|
||||
"load=tftp 80500000 $(u-boot)\0" \
|
||||
""
|
||||
|
||||
#ifdef CONFIG_DBAU1550
|
||||
/* Boot from flash by default, revert to bootp */
|
||||
#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
|
||||
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_NET) & \
|
||||
~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \
|
||||
CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C))
|
||||
#else /* CONFIG_DBAU1550 */
|
||||
/* Boot from Compact flash partition 2 as default */
|
||||
#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;bootm"
|
||||
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_ELF ) & \
|
||||
~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
|
||||
CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \
|
||||
CFG_CMD_BDI | CFG_CMD_BEDBUG))
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \
|
||||
~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
|
||||
CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | \
|
||||
CFG_CMD_ELF | CFG_CMD_BDI | CFG_CMD_BEDBUG))
|
||||
#endif /* CONFIG_DBAU1550 */
|
||||
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "DbAu1x00 # " /* Monitor Command Prompt */
|
||||
|
||||
#define CFG_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
|
||||
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args*/
|
||||
@@ -91,7 +107,13 @@
|
||||
|
||||
#define CFG_BOOTPARAMS_LEN 128*1024
|
||||
|
||||
#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */
|
||||
#define CFG_MHZ 396
|
||||
|
||||
#if (CFG_MHZ % 12) != 0
|
||||
#error "Invalid CPU frequency - must be multiple of 12!"
|
||||
#endif
|
||||
|
||||
#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
|
||||
|
||||
#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
|
||||
|
||||
@@ -103,12 +125,29 @@
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#ifdef CONFIG_DBAU1550
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
|
||||
|
||||
#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
|
||||
|
||||
#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
|
||||
|
||||
#else /* CONFIG_DBAU1550 */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
|
||||
|
||||
#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
|
||||
|
||||
#endif /* CONFIG_DBAU1550 */
|
||||
|
||||
#define CFG_FLASH_CFI 1
|
||||
#define CFG_FLASH_CFI_DRIVER 1
|
||||
|
||||
/* The following #defines are needed to get flash environment right */
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#define CFG_MONITOR_LEN (192 << 10)
|
||||
@@ -134,8 +173,15 @@
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
|
||||
#ifdef CONFIG_DBAU1550
|
||||
#define MEM_SIZE 192
|
||||
#else
|
||||
#define MEM_SIZE 64
|
||||
#endif
|
||||
|
||||
#define CONFIG_MEMSIZE_IN_BYTES
|
||||
|
||||
#ifndef CONFIG_DBAU1550
|
||||
/*---ATA PCMCIA ------------------------------------*/
|
||||
#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
|
||||
#define CFG_PCMCIA_MEM_ADDR 0x20000000
|
||||
@@ -166,6 +212,7 @@
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CFG_ATA_ALT_OFFSET 0x0100
|
||||
#endif /* CONFIG_DBAU1550 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
@@ -174,6 +221,4 @@
|
||||
#define CFG_ICACHE_SIZE 16384
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
|
||||
#define DB1000_BCSR_ADDR 0xAE000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
@@ -22,6 +22,13 @@ extern struct serial_device serial_smc_device;
|
||||
extern struct serial_device serial_scc_device;
|
||||
extern struct serial_device * default_serial_console (void);
|
||||
|
||||
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|
||||
|| defined(CONFIG_405EP)
|
||||
extern struct serial_device serial0_device;
|
||||
extern struct serial_device serial1_device;
|
||||
#endif
|
||||
|
||||
|
||||
extern void serial_initialize(void);
|
||||
extern void serial_devices_init(void);
|
||||
extern int serial_assign(char * name);
|
||||
|
||||
Reference in New Issue
Block a user