Merge git://git.denx.de/u-boot-net
This commit is contained in:
@@ -44,7 +44,6 @@
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#define CONFIG_SPI_FLASH_QUAD
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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@@ -18,7 +18,6 @@
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (0)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
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#define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII)
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@@ -88,7 +88,6 @@
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x0
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#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
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@@ -44,7 +44,6 @@
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#define CONFIG_SH_I2C_CLOCK 41666666
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (0)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
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#define CONFIG_PHY_SMSC 1
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@@ -77,7 +77,6 @@
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#define CONFIG_SYS_TMU_CLK_DIV 4
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (1)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
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#define CONFIG_BITBANGMII
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@@ -44,7 +44,6 @@
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#define CONFIG_SH_QSPI
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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@@ -44,7 +44,6 @@
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#define CONFIG_SH_QSPI
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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@@ -44,7 +44,6 @@
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#define CONFIG_SH_QSPI
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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@@ -45,7 +45,6 @@
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#define CONFIG_SPI_FLASH_QUAD
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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@@ -18,7 +18,6 @@
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (0)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
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#define CONFIG_PHY_SMSC 1
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@@ -47,7 +47,6 @@
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 18
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
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@@ -47,7 +47,6 @@
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 18
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
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@@ -48,7 +48,6 @@
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 1
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
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@@ -77,7 +77,6 @@
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#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (1)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
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#define CONFIG_BITBANGMII
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@@ -45,7 +45,6 @@
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#define CONFIG_SPI_FLASH_QUAD
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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@@ -48,7 +48,6 @@
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#define CONFIG_SPI_FLASH_QUAD
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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@@ -257,6 +257,7 @@ int gen10g_startup(struct phy_device *phydev);
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int gen10g_shutdown(struct phy_device *phydev);
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int gen10g_discover_mmds(struct phy_device *phydev);
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int phy_b53_init(void);
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int phy_mv88e61xx_init(void);
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int phy_aquantia_init(void);
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int phy_atheros_init(void);
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