Fix Bamboo DDR SDRAM initialization (problem with onboard SDRAM)
Patch by Stefan Roese, 15 Nov 2005
This commit is contained in:
Stefan Roese
@@ -650,6 +650,17 @@ const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
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0xAA55AA55, 0xAA55AA55}
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};
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/* bank_parms is used to sort the bank sizes by descending order */
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struct bank_param {
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unsigned long cr;
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unsigned long bank_size_bytes;
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};
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typedef struct bank_param BANKPARMS;
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#ifdef CFG_SIMULATE_SPD_EEPROM
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extern unsigned char cfg_simulate_spd_eeprom[128];
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#endif
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unsigned char spd_read(uchar chip, uint addr);
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@@ -806,9 +817,19 @@ long int spd_sdram(void) {
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return total_size;
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}
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unsigned char spd_read(uchar chip, uint addr) {
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unsigned char spd_read(uchar chip, uint addr)
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{
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unsigned char data[2];
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#ifdef CFG_SIMULATE_SPD_EEPROM
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if (chip == CFG_SIMULATE_SPD_EEPROM) {
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/*
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* Onboard spd eeprom requested -> simulate values
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*/
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return cfg_simulate_spd_eeprom[addr];
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}
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#endif /* CFG_SIMULATE_SPD_EEPROM */
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if (i2c_probe(chip) == 0) {
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if (i2c_read(chip, addr, 1, data, 1) == 0) {
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return data[0];
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@@ -849,12 +870,10 @@ void get_spd_info(unsigned long* dimm_populated,
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}
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}
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#ifndef CONFIG_BAMBOO /* bamboo has onboard DDR _and_ DDR DIMM's */
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if (dimm_found == FALSE) {
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printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
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hang();
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}
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#endif /* CONFIG_BAMBOO */
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}
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void check_mem_type(unsigned long* dimm_populated,
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@@ -1593,35 +1612,56 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
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{
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unsigned long dimm_num;
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unsigned long bank_base_addr;
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unsigned long bank_size_bytes;
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unsigned long cr;
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unsigned long i;
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unsigned long j;
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unsigned long temp;
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unsigned char num_row_addr;
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unsigned char num_col_addr;
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unsigned char num_banks;
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unsigned char bank_size_id;
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#ifndef CONFIG_BAMBOO
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unsigned long bxcr_num;
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unsigned long ctrl_bank_num[MAXBANKS];
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unsigned long bx_cr_num;
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unsigned long largest_size_index;
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unsigned long largest_size;
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unsigned long current_size_index;
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BANKPARMS bank_parms[MAXBXCR];
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unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
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unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
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/*
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* Set the BxCR regs. First, wipe out the bank config registers.
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*/
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for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
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mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
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for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
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mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2));
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mtdcr(memcfgd, 0x00000000);
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bank_parms[bx_cr_num].bank_size_bytes = 0;
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}
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#ifdef CONFIG_BAMBOO
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/*
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* This next section is hardware dependent and must be programmed
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* to match the hardware. For bammboo, the following holds...
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* 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0
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* 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
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* 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
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* 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
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* ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
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*/
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ctrl_bank_num[0] = 0;
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ctrl_bank_num[1] = 1;
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ctrl_bank_num[2] = 3;
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#else
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ctrl_bank_num[0] = 0;
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ctrl_bank_num[1] = 1;
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ctrl_bank_num[2] = 2;
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ctrl_bank_num[3] = 3;
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#endif
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/*
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* reset the bank_base address
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*/
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#ifndef CONFIG_BAMBOO
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bank_base_addr = CFG_SDRAM_BASE;
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#else
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bank_base_addr = CFG_SDRAM_ONBOARD_SIZE;
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#endif
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for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
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if (dimm_populated[dimm_num] == TRUE) {
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@@ -1634,7 +1674,6 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
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* Set the SDRAM0_BxCR regs
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*/
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cr = 0;
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bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
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switch (bank_size_id) {
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case 0x02:
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cr |= SDRAM_BXCR_SDSZ_8;
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@@ -1693,46 +1732,56 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
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*/
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cr |= SDRAM_BXCR_SDBE;
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/*------------------------------------------------------------------
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| This next section is hardware dependent and must be programmed
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| to match the hardware.
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+-----------------------------------------------------------------*/
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if (dimm_num == 0) {
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for (i = 0; i < num_banks; i++) {
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#ifndef CONFIG_BAMBOO
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mtdcr(memcfga, mem_b0cr + (i << 2));
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#else
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mtdcr(memcfga, mem_b1cr + (i << 2));
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#endif
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temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
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SDRAM_BXCR_SDSZ_MASK |
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SDRAM_BXCR_SDAM_MASK |
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SDRAM_BXCR_SDBE);
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cr |= temp;
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cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
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mtdcr(memcfgd, cr);
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bank_base_addr += bank_size_bytes;
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}
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} else {
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for (i = 0; i < num_banks; i++) {
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#ifndef CONFIG_BAMBOO
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mtdcr(memcfga, mem_b2cr + (i << 2));
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#else
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mtdcr(memcfga, mem_b3cr + (i << 2));
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#endif
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temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
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SDRAM_BXCR_SDSZ_MASK |
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SDRAM_BXCR_SDAM_MASK |
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SDRAM_BXCR_SDBE);
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cr |= temp;
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cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
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mtdcr(memcfgd, cr);
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bank_base_addr += bank_size_bytes;
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}
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for (i = 0; i < num_banks; i++) {
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bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
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(4 * 1024 * 1024) * bank_size_id;
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bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
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}
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}
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}
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/* Initialize sort tables */
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for (i = 0; i < MAXBXCR; i++) {
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sorted_bank_num[i] = i;
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sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
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}
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for (i = 0; i < MAXBXCR-1; i++) {
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largest_size = sorted_bank_size[i];
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largest_size_index = 255;
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/* Find the largest remaining value */
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for (j = i + 1; j < MAXBXCR; j++) {
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if (sorted_bank_size[j] > largest_size) {
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/* Save largest remaining value and its index */
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largest_size = sorted_bank_size[j];
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largest_size_index = j;
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}
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}
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if (largest_size_index != 255) {
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/* Swap the current and largest values */
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current_size_index = sorted_bank_num[largest_size_index];
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sorted_bank_size[largest_size_index] = sorted_bank_size[i];
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sorted_bank_size[i] = largest_size;
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sorted_bank_num[largest_size_index] = sorted_bank_num[i];
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sorted_bank_num[i] = current_size_index;
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}
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}
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/* Set the SDRAM0_BxCR regs thanks to sort tables */
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for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
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if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
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mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
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temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
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SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
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temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
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bank_parms[sorted_bank_num[bx_cr_num]].cr;
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mtdcr(memcfgd, temp);
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bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
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}
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}
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return(bank_base_addr);
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}
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