Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
This commit is contained in:
Wolfgang Denk
316
include/configs/dlvision-10g.h
Normal file
316
include/configs/dlvision-10g.h
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@@ -0,0 +1,316 @@
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/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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||||
* See file CREDITS for list of people who contributed to this
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||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
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||||
|
||||
#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_405EP 1 /* this is a PPC405 CPU */
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#define CONFIG_4xx 1 /* member of PPC4xx family */
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#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
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#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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||||
#define CONFIG_HOSTNAME dlvsion-10g
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#define CONFIG_IDENT_STRING " dlvision-10g 0.01"
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#include "amcc-common.h"
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||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
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#define CONFIG_LAST_STAGE_INIT
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||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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||||
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||||
/*
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||||
* Configure PLL
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||||
*/
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||||
#define PLLMR0_DEFAULT PLLMR0_266_133_66
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||||
#define PLLMR1_DEFAULT PLLMR1_266_133_66
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||||
|
||||
/* new uImage format support */
|
||||
#define CONFIG_FIT
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||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
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||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
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||||
|
||||
/*
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* Default environment variables
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||||
*/
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||||
#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=fc000000\0" \
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"fdt_addr=fc1e0000\0" \
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"ramdisk_addr=fc200000\0" \
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""
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||||
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#define CONFIG_PHY_ADDR 4 /* PHY address */
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||||
#define CONFIG_HAS_ETH0
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||||
#define CONFIG_HAS_ETH1
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#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
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#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
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||||
|
||||
/*
|
||||
* Commands additional to the ones defined in amcc-common.h
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||||
*/
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||||
#define CONFIG_CMD_CACHE
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||||
#undef CONFIG_CMD_EEPROM
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||||
|
||||
/*
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||||
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
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||||
*/
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||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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||||
|
||||
/* SDRAM timings used in datasheet */
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#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
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#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
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#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
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#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
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#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
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/*
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* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
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* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
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||||
* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
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||||
* The Linux BASE_BAUD define should match this configuration.
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||||
* baseBaud = cpuClock/(uartDivisor*16)
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||||
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
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||||
* set Linux BASE_BAUD to 403200.
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||||
*/
|
||||
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
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||||
#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
|
||||
#define CONFIG_SYS_BASE_BAUD 691200
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||||
|
||||
/*
|
||||
* I2C stuff
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
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||||
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||||
/* Temp sensor/hwmon/dtt */
|
||||
#define CONFIG_DTT_LM63 1 /* National LM63 */
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||||
#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
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||||
#define CONFIG_DTT_PWM_LOOKUPTABLE \
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{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
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||||
#define CONFIG_DTT_TACH_LIMIT 0xa10
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||||
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||||
/* EBC peripherals */
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||||
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#define CONFIG_SYS_FLASH_BASE 0xFC000000
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#define CONFIG_SYS_FPGA0_BASE 0x7f100000
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#define CONFIG_SYS_FPGA1_BASE 0x7f200000
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#define CONFIG_SYS_LATCH_BASE 0x7f300000
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#define CONFIG_SYS_FPGA_BASE(k) \
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(k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
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#define CONFIG_SYS_FPGA_DONE(k) \
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(k ? 0x2000 : 0x1000)
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#define CONFIG_SYS_FPGA_COUNT 2
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||||
#define CONFIG_SYS_LATCH0_RESET 0xffff
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||||
#define CONFIG_SYS_LATCH0_BOOT 0xffff
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||||
#define CONFIG_SYS_LATCH1_RESET 0xffcf
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||||
#define CONFIG_SYS_LATCH1_BOOT 0xffff
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||||
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||||
/*
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||||
* FLASH organization
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||||
*/
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||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
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||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
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||||
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
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||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
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||||
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||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
||||
#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
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||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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||||
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||||
/* Address and size of Redundant Environment Sector */
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||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif
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/*
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||||
* PPC405 GPIO Configuration
|
||||
*/
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||||
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
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||||
{ \
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||||
/* GPIO Core 0 */ \
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||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
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||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
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} \
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}
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/*
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory (OCM) for temperary stack until sdram is tested */
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
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#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
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#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* External Bus Controller (EBC) Setup
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*/
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/* Memory Bank 0 (NOR-flash) */
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#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
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EBC_BXAP_FWT_ENCODE(8) | \
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EBC_BXAP_BWT_ENCODE(7) | \
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EBC_BXAP_BCE_DISABLE | \
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EBC_BXAP_BCT_2TRANS | \
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||||
EBC_BXAP_CSN_ENCODE(0) | \
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||||
EBC_BXAP_OEN_ENCODE(2) | \
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||||
EBC_BXAP_WBN_ENCODE(2) | \
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||||
EBC_BXAP_WBF_ENCODE(2) | \
|
||||
EBC_BXAP_TH_ENCODE(4) | \
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EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_NONDELAYED | \
|
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EBC_BXAP_BEM_WRITEONLY | \
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||||
EBC_BXAP_PEN_DISABLED)
|
||||
#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
|
||||
EBC_BXCR_BS_64MB | \
|
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EBC_BXCR_BU_RW | \
|
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EBC_BXCR_BW_16BIT)
|
||||
|
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/* Memory Bank 1 (FPGA0) */
|
||||
#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
|
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EBC_BXAP_TWT_ENCODE(5) | \
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||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(2) | \
|
||||
EBC_BXAP_WBN_ENCODE(1) | \
|
||||
EBC_BXAP_WBF_ENCODE(1) | \
|
||||
EBC_BXAP_TH_ENCODE(0) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_NONDELAYED | \
|
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EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED)
|
||||
#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
|
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EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT)
|
||||
|
||||
/* Memory Bank 2 (FPGA1) */
|
||||
#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
|
||||
EBC_BXAP_TWT_ENCODE(6) | \
|
||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(2) | \
|
||||
EBC_BXAP_WBN_ENCODE(1) | \
|
||||
EBC_BXAP_WBF_ENCODE(1) | \
|
||||
EBC_BXAP_TH_ENCODE(0) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_NONDELAYED | \
|
||||
EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED)
|
||||
#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
|
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT)
|
||||
|
||||
/* Memory Bank 3 (Latches) */
|
||||
#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
|
||||
EBC_BXAP_FWT_ENCODE(8) | \
|
||||
EBC_BXAP_BWT_ENCODE(4) | \
|
||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(1) | \
|
||||
EBC_BXAP_WBN_ENCODE(1) | \
|
||||
EBC_BXAP_WBF_ENCODE(1) | \
|
||||
EBC_BXAP_TH_ENCODE(2) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_NONDELAYED | \
|
||||
EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED)
|
||||
#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
|
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT)
|
||||
|
||||
/*
|
||||
* OSD Setup
|
||||
*/
|
||||
#define CONFIG_SYS_ICS8N3QV01
|
||||
#define CONFIG_SYS_SIL1178
|
||||
#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -229,13 +229,15 @@
|
||||
#define CONFIG_SYS_EBC_PB1CR 0x7f318000
|
||||
|
||||
/* Memory Bank 2 (FPGA) initialization */
|
||||
#define CONFIG_SYS_FPGA_BASE 0x7f100000
|
||||
#define CONFIG_SYS_FPGA0_BASE 0x7f100000
|
||||
#define CONFIG_SYS_EBC_PB2AP 0x02025080
|
||||
/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
|
||||
#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
|
||||
|
||||
#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
|
||||
#define CONFIG_SYS_FPGA_RFL_HIGH 0x3ffe
|
||||
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
|
||||
#define CONFIG_SYS_FPGA_DONE(k) 0x0010
|
||||
|
||||
#define CONFIG_SYS_FPGA_COUNT 1
|
||||
|
||||
/* Memory Bank 3 (Latches) initialization */
|
||||
#define CONFIG_SYS_LATCH_BASE 0x7f200000
|
||||
|
||||
@@ -130,6 +130,12 @@ int fpga_gpio_get(int pin);
|
||||
else fpga_gpio_clear(0x0020)
|
||||
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
|
||||
|
||||
/*
|
||||
* OSD hardware
|
||||
*/
|
||||
#define CONFIG_SYS_MPC92469AC
|
||||
#define CONFIG_SYS_CH7301
|
||||
|
||||
/*
|
||||
* FLASH organization
|
||||
*/
|
||||
@@ -231,13 +237,15 @@ int fpga_gpio_get(int pin);
|
||||
#define CONFIG_SYS_EBC_PB1AP 0x92015480
|
||||
#define CONFIG_SYS_EBC_PB1CR 0xFB858000
|
||||
|
||||
/* Memory Bank 2 (FPGA) initialization */
|
||||
#define CONFIG_SYS_FPGA_BASE 0x7f100000
|
||||
/* Memory Bank 2 (FPGA0) initialization */
|
||||
#define CONFIG_SYS_FPGA0_BASE 0x7f100000
|
||||
#define CONFIG_SYS_EBC_PB2AP 0x02825080
|
||||
#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x1a000)
|
||||
#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
|
||||
|
||||
#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
|
||||
#define CONFIG_SYS_FPGA_RFL_HIGH 0x00fe
|
||||
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
|
||||
#define CONFIG_SYS_FPGA_DONE(k) 0x0010
|
||||
|
||||
#define CONFIG_SYS_FPGA_COUNT 1
|
||||
|
||||
/* Memory Bank 3 (Latches) initialization */
|
||||
#define CONFIG_SYS_LATCH_BASE 0x7f200000
|
||||
@@ -249,4 +257,11 @@ int fpga_gpio_get(int pin);
|
||||
#define CONFIG_SYS_LATCH1_RESET 0xffff
|
||||
#define CONFIG_SYS_LATCH1_BOOT 0xffff
|
||||
|
||||
/*
|
||||
* OSD Setup
|
||||
*/
|
||||
#define CONFIG_SYS_MPC92469AC
|
||||
#define CONFIG_SYS_CH7301
|
||||
#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
108
include/gdsys_fpga.h
Normal file
108
include/gdsys_fpga.h
Normal file
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* (C) Copyright 2010
|
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __GDSYS_FPGA_H
|
||||
#define __GDSYS_FPGA_H
|
||||
|
||||
enum {
|
||||
FPGA_STATE_DONE_FAILED = 1 << 0,
|
||||
FPGA_STATE_REFLECTION_FAILED = 1 << 1,
|
||||
};
|
||||
|
||||
int get_fpga_state(unsigned dev);
|
||||
void print_fpga_state(unsigned dev);
|
||||
|
||||
typedef struct ihs_gpio {
|
||||
u16 read;
|
||||
u16 clear;
|
||||
u16 set;
|
||||
} ihs_gpio_t;
|
||||
|
||||
typedef struct ihs_i2c {
|
||||
u16 write_mailbox;
|
||||
u16 write_mailbox_ext;
|
||||
u16 read_mailbox;
|
||||
u16 read_mailbox_ext;
|
||||
} ihs_i2c_t;
|
||||
|
||||
typedef struct ihs_osd {
|
||||
u16 version;
|
||||
u16 features;
|
||||
u16 control;
|
||||
u16 xy_size;
|
||||
} ihs_osd_t;
|
||||
|
||||
#ifdef CONFIG_IO
|
||||
typedef struct ihs_fpga {
|
||||
u16 reflection_low; /* 0x0000 */
|
||||
u16 versions; /* 0x0002 */
|
||||
u16 fpga_features; /* 0x0004 */
|
||||
u16 fpga_version; /* 0x0006 */
|
||||
u16 reserved_0[5]; /* 0x0008 */
|
||||
u16 quad_serdes_reset; /* 0x0012 */
|
||||
u16 reserved_1[8181]; /* 0x0014 */
|
||||
u16 reflection_high; /* 0x3ffe */
|
||||
} ihs_fpga_t;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IOCON
|
||||
typedef struct ihs_fpga {
|
||||
u16 reflection_low; /* 0x0000 */
|
||||
u16 versions; /* 0x0002 */
|
||||
u16 fpga_version; /* 0x0004 */
|
||||
u16 fpga_features; /* 0x0006 */
|
||||
u16 reserved_0[6]; /* 0x0008 */
|
||||
ihs_gpio_t gpio; /* 0x0014 */
|
||||
u16 mpc3w_control; /* 0x001a */
|
||||
u16 reserved_1[19]; /* 0x001c */
|
||||
u16 videocontrol; /* 0x0042 */
|
||||
u16 reserved_2[93]; /* 0x0044 */
|
||||
u16 reflection_high; /* 0x00fe */
|
||||
ihs_osd_t osd; /* 0x0100 */
|
||||
u16 reserved_3[892]; /* 0x0108 */
|
||||
u16 videomem; /* 0x0800 */
|
||||
} ihs_fpga_t;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DLVISION_10G
|
||||
typedef struct ihs_fpga {
|
||||
u16 reflection_low; /* 0x0000 */
|
||||
u16 versions; /* 0x0002 */
|
||||
u16 fpga_version; /* 0x0004 */
|
||||
u16 fpga_features; /* 0x0006 */
|
||||
u16 reserved_0[10]; /* 0x0008 */
|
||||
u16 extended_interrupt; /* 0x001c */
|
||||
u16 reserved_1[9]; /* 0x001e */
|
||||
ihs_i2c_t i2c; /* 0x0030 */
|
||||
u16 reserved_2[35]; /* 0x0038 */
|
||||
u16 reflection_high; /* 0x007e */
|
||||
u16 reserved_3[15]; /* 0x0080 */
|
||||
u16 videocontrol; /* 0x009e */
|
||||
u16 reserved_4[176]; /* 0x00a0 */
|
||||
ihs_osd_t osd; /* 0x0200 */
|
||||
u16 reserved_5[764]; /* 0x0208 */
|
||||
u16 videomem; /* 0x0800 */
|
||||
} ihs_fpga_t;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user