Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
This commit is contained in:
@@ -143,6 +143,8 @@
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#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
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#define CONFIG_SYS_NAND_QUIET 1
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#define CONFIG_SYS_NAND_MAX_OOBFREE 2
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#define CONFIG_SYS_NAND_MAX_ECCPOS 56
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/*-----------------------------------------------------------------------
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* PCI stuff
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@@ -191,13 +191,14 @@
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| CSPR_MSEL_NAND \
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| CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2k */ \
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| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
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| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
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| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
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| CSOR_NAND_PGS_8K /* Page Size = 8K */ \
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| CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
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| CSOR_NAND_PB(128)) /*128 Pages Per Block*/
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
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FTIM0_NAND_TWP(0x0c) | \
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FTIM0_NAND_TWCHT(0x08) | \
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@@ -224,6 +225,7 @@
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
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@@ -322,6 +322,8 @@
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#define CONFIG_CMD_NAND 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_SYS_NAND_MAX_OOBFREE 5
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#define CONFIG_SYS_NAND_MAX_ECCPOS 56
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/* NAND boot: 4K NAND loader config */
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#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
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@@ -229,6 +229,8 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_CMD_NAND
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_SYS_NAND_MAX_OOBFREE 2
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#define CONFIG_SYS_NAND_MAX_ECCPOS 256
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#if defined(CONFIG_NAND)
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
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@@ -324,6 +324,8 @@
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \
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CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
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#define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */
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#define CONFIG_SYS_NAND_MAX_OOBFREE 2
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#define CONFIG_SYS_NAND_MAX_ECCPOS 56
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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@@ -220,6 +220,8 @@
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
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#ifdef CONFIG_NAND
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_NAND_OMAP_ELM
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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@@ -237,7 +239,8 @@
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 14
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#endif
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@@ -187,6 +187,7 @@
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/* NAND support */
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#define CONFIG_NAND
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_NAND_OMAP_ELM
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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@@ -263,6 +264,7 @@
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 14
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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@@ -340,6 +340,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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@@ -334,6 +334,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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@@ -327,6 +327,7 @@
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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@@ -353,7 +353,6 @@
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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@@ -395,6 +394,7 @@
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56, 57, 58, 59, 60, 61, 62, 63}
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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@@ -431,6 +431,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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@@ -107,6 +107,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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@@ -86,6 +86,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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@@ -362,6 +362,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#endif
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@@ -324,6 +324,7 @@
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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@@ -195,6 +195,7 @@
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 14
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
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#define CONFIG_SYS_NAND_ECCSTEPS 4
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#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
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@@ -430,6 +431,7 @@
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"\0"
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_NAND_OMAP_ELM
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
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/* to access nand at */
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@@ -224,7 +224,6 @@
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_CONSOLE
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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@@ -261,6 +260,7 @@
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56, 57, 58, 59, 60, 61, 62, 63}
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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@@ -138,8 +138,9 @@
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_NAND_OMAP_BCH8
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#define CONFIG_BCH
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#define CONFIG_SYS_NAND_MAX_OOBFREE 2
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#define CONFIG_SYS_NAND_MAX_ECCPOS 56
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/* commands to include */
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#include <config_cmd_default.h>
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@@ -374,6 +375,7 @@
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 13
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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@@ -96,6 +96,29 @@ struct mtd_oob_ops {
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uint8_t *oobbuf;
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};
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#ifdef CONFIG_SYS_NAND_MAX_OOBFREE
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#define MTD_MAX_OOBFREE_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_OOBFREE
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#else
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#define MTD_MAX_OOBFREE_ENTRIES_LARGE 32
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#endif
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#ifdef CONFIG_SYS_NAND_MAX_ECCPOS
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#define MTD_MAX_ECCPOS_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_ECCPOS
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#else
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#define MTD_MAX_ECCPOS_ENTRIES_LARGE 640
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#endif
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/*
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* ECC layout control structure. Exported to userspace for
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* diagnosis and to allow creation of raw images
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*/
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struct nand_ecclayout {
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uint32_t eccbytes;
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uint32_t eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
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uint32_t oobavail;
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struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE];
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};
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struct mtd_info {
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u_char type;
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u_int32_t flags;
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@@ -155,18 +155,6 @@ struct nand_oobfree {
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uint32_t length;
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};
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#define MTD_MAX_OOBFREE_ENTRIES 8
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/*
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* ECC layout control structure. Exported to userspace for
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* diagnosis and to allow creation of raw images
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*/
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struct nand_ecclayout {
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uint32_t eccbytes;
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uint32_t eccpos[128];
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uint32_t oobavail;
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struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
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};
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/**
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* struct mtd_ecc_stats - error correction stats
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*
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