From f301ba55c877707e15378401247cc828740ba00e Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Sun, 3 Feb 2019 15:15:38 +0200 Subject: [PATCH 1/5] arm: mvebu: mcbin: dts: fix PCIe reset polarity The PCIe slot PERST signal is active low. Fix the gpio signal description in the dts. This happened to work because the pcie_dw_mvebu driver sets the reset gpio level to 1 (high) to release the reset. The following commit will fix that. Signed-off-by: Baruch Siach Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/dts/armada-8040-mcbin.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 7e8e2f707c..5a046d9de4 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -132,7 +132,7 @@ num-lanes = <4>; pinctrl-names = "default"; pinctrl-0 = <&cpm_pcie_reset_pins>; - marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */ + marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ status = "okay"; }; From 6664a0e5f3694592966c92ec4a0547ad77b84a9a Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Sun, 3 Feb 2019 15:15:39 +0200 Subject: [PATCH 2/5] pcie: designware: mvebu: fix reset release polarity The dm_gpio_set_value() routine sets signal logical level, with GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1 (asserted), while reset inactive value is 0 (de-asserted). Fix the reset toggle code to set the correct reset logic value. Reported-by: Sven Auhagen Signed-off-by: Baruch Siach Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- drivers/pci/pcie_dw_mvebu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 8081005c27..95fb41966f 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -489,7 +489,9 @@ static int pcie_dw_mvebu_probe(struct udevice *dev) * using this GPIO. */ if (dm_gpio_is_valid(&reset_gpio)) { - dm_gpio_set_value(&reset_gpio, 1); + dm_gpio_set_value(&reset_gpio, 1); /* assert */ + mdelay(200); + dm_gpio_set_value(&reset_gpio, 0); /* de-assert */ mdelay(200); } #else From d7f165cf676f4ae8aafd7adfc6dbe0f851026e46 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Sun, 3 Feb 2019 15:15:40 +0200 Subject: [PATCH 3/5] arm: mvebu: cf gt-8k: dts: add PCIe slot reset support Describe the mini-PCIe slot gpio reset signal. This enables PCIe devices on Clearfog GT-8K. Signed-off-by: Baruch Siach Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index 498105f25f..cdff44aca5 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -99,6 +99,11 @@ 0 0 0 0 0 0 0xe 0xe 0xe 0xe 0xe 0xe 0 >; + cpm_pcie_reset_pins: cpm-pcie-reset-pins { + marvell,pins = < 32 >; + marvell,function = <0>; + }; + cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { marvell,pins = < 47 >; marvell,function = <0>; @@ -120,6 +125,9 @@ &cpm_pcie0 { num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_reset_pins>; + marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>; status = "okay"; }; From 0ef692084363f2de8547db93397c6a69123d26ca Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 7 Feb 2019 13:21:16 +0200 Subject: [PATCH 4/5] Kconfig: fix BUILD_TARGET for ARCH_MVEBU Commit dc146ca11187 ("Kconfig: Migrate CONFIG_BUILD_TARGET") made the mvebu default build target depend on CONFIG_SPL_BUILD. Unfortunately, there is no such Kconfig symbol. Use the CONFIG_SPL symbol instead to fix that. Cc: Jagan Teki Signed-off-by: Baruch Siach Reviewed-by: Stefan Roese Reviewed-by: Jagan Teki Signed-off-by: Stefan Roese --- Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Kconfig b/Kconfig index 2a48f53256..512c7beb89 100644 --- a/Kconfig +++ b/Kconfig @@ -227,7 +227,7 @@ config BUILD_ROM config BUILD_TARGET string "Build target special images" default "u-boot-with-spl.sfp" if ARCH_SOCFPGA - default "u-boot-spl.kwb" if ARCH_MVEBU && SPL_BUILD + default "u-boot-spl.kwb" if ARCH_MVEBU && SPL default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI default "u-boot.kwb" if KIRKWOOD From a6ac775bae7fad1534ffe2b20244b7e7106b12b0 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Mon, 11 Feb 2019 14:19:56 +1300 Subject: [PATCH 5/5] ARM: mvebu: x530: use MV_DDR_FREQ_SAR MV_DDR_FREQ_SAR lets the DDR frequency be determined by hardware strapping. This also has the side effect of running the DDR clock in synchronous mode with the CPU core clock rather than from an independent PLL. We've seen this improve reliability in operation across a number of boards and temperature ranges. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- board/alliedtelesis/x530/x530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index b34ae51345..d7d1942fe6 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -57,7 +57,7 @@ static struct mv_ddr_topology_map board_topology_map = { SPEED_BIN_DDR_1866M, /* speed_bin */ MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */ MV_DDR_DIE_CAP_4GBIT, /* die capacity */ - MV_DDR_FREQ_933, /* frequency */ + MV_DDR_FREQ_SAR, /* frequency */ 0, 0, /* cas_l cas_wl */ MV_DDR_TEMP_LOW, /* temperature */ MV_DDR_TIM_2T} }, /* timing */