From 455a5a8086b17bd6fb60c86ec34299cae6ce2950 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 31 May 2017 01:04:12 -0700 Subject: [PATCH 1/6] x86: baytrail: Change "fsp, mrc-init-tseg-size" default value to 1 The default value of "fsp,mrc-init-tseg-size" should be 1 (1MB) per FSP default settings. 0 is not valid. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass --- arch/x86/cpu/baytrail/fsp_configs.c | 2 +- arch/x86/dts/bayleybay.dts | 2 +- arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 +- arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +- arch/x86/dts/dfi-bt700.dtsi | 2 +- arch/x86/dts/minnowmax.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index d49b8d2737..365e0dd682 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -148,7 +148,7 @@ void update_fsp_configs(struct fsp_config_data *config, fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node, "fsp,mrc-init-tseg-size", - 0); + 1); fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node, "fsp,mrc-init-mmio-size", 0x800); diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 1ae058d7a9..42a8131bd5 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -236,7 +236,7 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-tseg-size = <1>; fsp,mrc-init-mmio-size = <0x800>; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index aa8bfb8651..d4199a3c46 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -259,7 +259,7 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-tseg-size = <1>; fsp,mrc-init-mmio-size = <0x800>; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 898e9c9b5f..904197a101 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -246,7 +246,7 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-tseg-size = <1>; fsp,mrc-init-mmio-size = <0x800>; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index 546981a9ac..a369e7322e 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -248,7 +248,7 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-tseg-size = <1>; fsp,mrc-init-mmio-size = <0x800>; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index af64c6859c..4d55abba34 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -260,7 +260,7 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-tseg-size = <1>; fsp,mrc-init-mmio-size = <0x800>; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; From 6702488cfa90831454d83a63eb0b4a0bb82a3a1f Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 31 May 2017 01:04:13 -0700 Subject: [PATCH 2/6] x86: baytrail: Remove "serial-debug-port-*" settings "serial-debug-port-address" and "serial-debug-port-type" settings are actually reserved in the FSP UPD data structure. Remove them. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass --- arch/x86/cpu/baytrail/fsp_configs.c | 4 ---- arch/x86/dts/bayleybay.dts | 2 -- arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 -- arch/x86/dts/minnowmax.dts | 2 -- arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 3 +-- doc/device-tree-bindings/misc/intel,baytrail-fsp.txt | 2 -- 6 files changed, 1 insertion(+), 14 deletions(-) diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 365e0dd682..977d5fe706 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -193,10 +193,6 @@ void update_fsp_configs(struct fsp_config_data *config, fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size", 2); fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", 2); - fsp_upd->serial_debug_port_address = fdtdec_get_int(blob, node, - "fsp,serial-debug-port-address", 0x3f8); - fsp_upd->serial_debug_port_type = fdtdec_get_int(blob, node, - "fsp,serial-debug-port-type", 1); fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node, "fsp,mrc-debug-msg"); fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable"); diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 42a8131bd5..1916991077 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -263,8 +263,6 @@ fsp,igd-dvmt50-pre-alloc = <2>; fsp,aperture-size = <2>; fsp,gtt-size = <2>; - fsp,serial-debug-port-address = <0x3f8>; - fsp,serial-debug-port-type = <1>; fsp,scc-enable-pci-mode; fsp,os-selection = <4>; fsp,emmc45-ddr50-enabled; diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index d4199a3c46..61af6366e0 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -285,8 +285,6 @@ fsp,scc-enable-pci-mode; fsp,os-selection = <4>; fsp,enable-igd; - fsp,serial-debug-port-address = <0x3f8>; - fsp,serial-debug-port-type = <1>; }; microcode { diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 4d55abba34..75d27610d4 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -287,8 +287,6 @@ fsp,igd-dvmt50-pre-alloc = <2>; fsp,aperture-size = <2>; fsp,gtt-size = <2>; - fsp,serial-debug-port-address = <0x3f8>; - fsp,serial-debug-port-type = <1>; fsp,scc-enable-pci-mode; fsp,os-selection = <4>; fsp,emmc45-ddr50-enabled; diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h index 3c782a86e3..b083b6e5ec 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h @@ -64,8 +64,7 @@ struct __packed upd_region { uint8_t igd_dvmt50_pre_alloc; /* Offset 0x0043 */ uint8_t aperture_size; /* Offset 0x0044 */ uint8_t gtt_size; /* Offset 0x0045 */ - uint32_t serial_debug_port_address; /* Offset 0x0046 */ - uint8_t serial_debug_port_type; /* Offset 0x004a */ + uint8_t reserved2[5]; /* Offset 0x0046 */ uint8_t mrc_debug_msg; /* Offset 0x004b */ uint8_t isp_enable; /* Offset 0x004c */ uint8_t scc_enable_pci_mode; /* Offset 0x004d */ diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt index 07fa46ef7e..f40011edef 100644 --- a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt +++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt @@ -60,8 +60,6 @@ discovered by the FSP and used to setup main memory. - fsp,igd-dvmt50-pre-alloc - fsp,aperture-size - fsp,gtt-size -- fsp,serial-debug-port-address -- fsp,serial-debug-port-type - fsp,os-selection - fsp,emmc45-retune-timer-value From 5e74e5a6826f8cf194ef5a569d6cafd2ed924f5c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 31 May 2017 01:04:14 -0700 Subject: [PATCH 3/6] x86: baytrail: Use macros instead of magic numbers for FSP settings Introduce various meaningful macros for FSP settings and switch over to use them instead of magic numbers. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass --- arch/x86/cpu/baytrail/fsp_configs.c | 35 +++++---- arch/x86/dts/bayleybay.dts | 17 ++-- arch/x86/dts/baytrail_som-db5800-som-6867.dts | 15 ++-- arch/x86/dts/conga-qeval20-qa3-e3845.dts | 29 +++---- arch/x86/dts/dfi-bt700.dtsi | 29 +++---- arch/x86/dts/minnowmax.dts | 29 +++---- .../asm/arch-baytrail/fsp/fsp_configs.h | 77 +++++++++++++++++++ .../misc/intel,baytrail-fsp.txt | 74 ++++++------------ 8 files changed, 181 insertions(+), 124 deletions(-) diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 977d5fe706..c48ac07385 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -148,10 +148,10 @@ void update_fsp_configs(struct fsp_config_data *config, fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node, "fsp,mrc-init-tseg-size", - 1); + MRC_INIT_TSEG_SIZE_1MB); fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node, "fsp,mrc-init-mmio-size", - 0x800); + MRC_INIT_MMIO_SIZE_2048MB); fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node, "fsp,mrc-init-spd-addr1", 0xa0); @@ -159,7 +159,8 @@ void update_fsp_configs(struct fsp_config_data *config, "fsp,mrc-init-spd-addr2", 0xa2); fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node, - "fsp,emmc-boot-mode", 2); + "fsp,emmc-boot-mode", + EMMC_BOOT_MODE_EMMC41); fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio"); fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node, "fsp,enable-sdcard"); @@ -169,7 +170,8 @@ void update_fsp_configs(struct fsp_config_data *config, "fsp,enable-hsuart1"); fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi"); fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata"); - fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", 1); + fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", + SATA_MODE_AHCI); fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, "fsp,enable-azalia"); fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci"); @@ -189,10 +191,11 @@ void update_fsp_configs(struct fsp_config_data *config, fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1"); fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi"); fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node, - "fsp,igd-dvmt50-pre-alloc", 2); + "fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_64MB); fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size", - 2); - fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", 2); + APERTURE_SIZE_256MB); + fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", + GTT_SIZE_2MB); fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node, "fsp,mrc-debug-msg"); fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable"); @@ -203,7 +206,7 @@ void update_fsp_configs(struct fsp_config_data *config, fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node, "fsp,txe-uma-enable"); fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection", - 4); + OS_SELECTION_LINUX); fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node, "fsp,emmc45-ddr50-enabled"); fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node, @@ -224,30 +227,32 @@ void update_fsp_configs(struct fsp_config_data *config, } else { mem->dram_speed = fdtdec_get_int(blob, node, "fsp,dram-speed", - 0x02); + DRAM_SPEED_1333MTS); mem->dram_type = fdtdec_get_int(blob, node, - "fsp,dram-type", 0x01); + "fsp,dram-type", + DRAM_TYPE_DDR3L); mem->dimm_0_enable = fdtdec_get_bool(blob, node, "fsp,dimm-0-enable"); mem->dimm_1_enable = fdtdec_get_bool(blob, node, "fsp,dimm-1-enable"); mem->dimm_width = fdtdec_get_int(blob, node, "fsp,dimm-width", - 0x00); + DIMM_WIDTH_X8); mem->dimm_density = fdtdec_get_int(blob, node, "fsp,dimm-density", - 0x01); + DIMM_DENSITY_2GBIT); mem->dimm_bus_width = fdtdec_get_int(blob, node, - "fsp,dimm-bus-width", 0x03); + "fsp,dimm-bus-width", + DIMM_BUS_WIDTH_64BITS); mem->dimm_sides = fdtdec_get_int(blob, node, "fsp,dimm-sides", - 0x00); + DIMM_SIDES_1RANKS); mem->dimm_tcl = fdtdec_get_int(blob, node, "fsp,dimm-tcl", 0x09); mem->dimm_trpt_rcd = fdtdec_get_int(blob, node, "fsp,dimm-trpt-rcd", 0x09); mem->dimm_twr = fdtdec_get_int(blob, node, - "fsp,dimm-twr", 0x0A); + "fsp,dimm-twr", 0x0a); mem->dimm_twtr = fdtdec_get_int(blob, node, "fsp,dimm-twtr", 0x05); mem->dimm_trrd = fdtdec_get_int(blob, node, diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 1916991077..a577b9371b 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include #include #include @@ -236,17 +237,17 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <1>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <1>; + fsp,emmc-boot-mode = ; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; + fsp,sata-mode = ; fsp,enable-lpe; fsp,lpss-sio-enable-pci-mode; fsp,enable-dma0; @@ -260,11 +261,11 @@ fsp,enable-i2c6; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; fsp,enable-igd; diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index 61af6366e0..3fc36f19c3 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include #include #include @@ -259,13 +260,13 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <1>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; + fsp,sata-mode = ; fsp,enable-azalia; fsp,lpss-sio-enable-pci-mode; fsp,enable-dma0; @@ -279,11 +280,11 @@ fsp,enable-i2c6; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,os-selection = ; fsp,enable-igd; }; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 904197a101..369cea6b58 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include #include #include @@ -246,42 +247,42 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <1>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <1>; + fsp,emmc-boot-mode = ; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; + fsp,sata-mode = ; fsp,enable-lpe; fsp,lpss-sio-enable-pci-mode; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; fsp,enable-igd; fsp,enable-memory-down; fsp,memory-down-params { compatible = "intel,baytrail-fsp-mdp"; - fsp,dram-speed = <2>; /* 2=1333MHz */ - fsp,dram-type = <1>; /* 1=DDR3L */ + fsp,dram-speed = ; + fsp,dram-type = ; fsp,dimm-0-enable; fsp,dimm-1-enable; - fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ - fsp,dimm-density = <2>; /* 2=4Gbit */ - fsp,dimm-bus-width = <3>; /* 3=64bits */ - fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */ + fsp,dimm-width = ; + fsp,dimm-density = ; + fsp,dimm-bus-width = ; + fsp,dimm-sides = ; /* These following values might need a re-visit */ fsp,dimm-tcl = <8>; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index a369e7322e..33f2a9c7a2 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include @@ -248,18 +249,18 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <1>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <1>; + fsp,emmc-boot-mode = ; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart0; fsp,enable-hsuart1; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; + fsp,sata-mode = ; fsp,enable-lpe; fsp,lpss-sio-enable-pci-mode; fsp,enable-dma0; @@ -273,24 +274,24 @@ fsp,enable-i2c6; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; fsp,enable-igd; fsp,enable-memory-down; fsp,memory-down-params { compatible = "intel,baytrail-fsp-mdp"; - fsp,dram-speed = <2>; /* 2=1333MHz */ - fsp,dram-type = <1>; /* 1=DDR3L */ + fsp,dram-speed = ; + fsp,dram-type = ; fsp,dimm-0-enable; - fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ - fsp,dimm-density = <3>; /* 3=8Gbit */ - fsp,dimm-bus-width = <3>; /* 3=64bits */ - fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */ + fsp,dimm-width = ; + fsp,dimm-density = ; + fsp,dimm-bus-width = ; + fsp,dimm-sides = ; /* These following values might need a re-visit */ fsp,dimm-tcl = <8>; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 75d27610d4..a4e2fa211c 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include #include #include @@ -260,17 +261,17 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <1>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <1>; + fsp,emmc-boot-mode = ; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; + fsp,sata-mode = ; fsp,enable-lpe; fsp,lpss-sio-enable-pci-mode; fsp,enable-dma0; @@ -284,24 +285,24 @@ fsp,enable-i2c6; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; fsp,enable-igd; fsp,enable-memory-down; fsp,memory-down-params { compatible = "intel,baytrail-fsp-mdp"; - fsp,dram-speed = <1>; - fsp,dram-type = <1>; + fsp,dram-speed = ; + fsp,dram-type = ; fsp,dimm-0-enable; - fsp,dimm-width = <1>; - fsp,dimm-density = <2>; - fsp,dimm-bus-width = <3>; - fsp,dimm-sides = <0>; + fsp,dimm-width = ; + fsp,dimm-density = ; + fsp,dimm-bus-width = ; + fsp,dimm-sides = ; fsp,dimm-tcl = <0xb>; fsp,dimm-trpt-rcd = <0xb>; fsp,dimm-twr = <0xc>; diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h index e539890c33..382cb79700 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h @@ -7,6 +7,7 @@ #ifndef __FSP_CONFIGS_H__ #define __FSP_CONFIGS_H__ +#ifndef __ASSEMBLY__ struct fsp_config_data { struct fsp_cfg_common common; struct upd_region fsp_upd; @@ -15,5 +16,81 @@ struct fsp_config_data { struct fspinit_rtbuf { struct common_buf common; /* FSP common runtime data structure */ }; +#endif + +/* FSP user configuration settings */ + +#define MRC_INIT_TSEG_SIZE_1MB 1 +#define MRC_INIT_TSEG_SIZE_2MB 2 +#define MRC_INIT_TSEG_SIZE_4MB 4 +#define MRC_INIT_TSEG_SIZE_8MB 8 + +#define MRC_INIT_MMIO_SIZE_1024MB 0x400 +#define MRC_INIT_MMIO_SIZE_1536MB 0x600 +#define MRC_INIT_MMIO_SIZE_2048MB 0x800 + +#define EMMC_BOOT_MODE_DISABLED 0 +#define EMMC_BOOT_MODE_AUTO 1 +#define EMMC_BOOT_MODE_EMMC41 2 +#define EMMC_BOOT_MODE_EMCC45 3 + +#define SATA_MODE_IDE 0 +#define SATA_MODE_AHCI 1 + +#define IGD_DVMT50_PRE_ALLOC_32MB 0x01 +#define IGD_DVMT50_PRE_ALLOC_64MB 0x02 +#define IGD_DVMT50_PRE_ALLOC_96MB 0x03 +#define IGD_DVMT50_PRE_ALLOC_128MB 0x04 +#define IGD_DVMT50_PRE_ALLOC_160MB 0x05 +#define IGD_DVMT50_PRE_ALLOC_192MB 0x06 +#define IGD_DVMT50_PRE_ALLOC_224MB 0x07 +#define IGD_DVMT50_PRE_ALLOC_256MB 0x08 +#define IGD_DVMT50_PRE_ALLOC_288MB 0x09 +#define IGD_DVMT50_PRE_ALLOC_320MB 0x0a +#define IGD_DVMT50_PRE_ALLOC_352MB 0x0b +#define IGD_DVMT50_PRE_ALLOC_384MB 0x0c +#define IGD_DVMT50_PRE_ALLOC_416MB 0x0d +#define IGD_DVMT50_PRE_ALLOC_448MB 0x0e +#define IGD_DVMT50_PRE_ALLOC_480MB 0x0f +#define IGD_DVMT50_PRE_ALLOC_512MB 0x10 + +#define APERTURE_SIZE_128MB 1 +#define APERTURE_SIZE_256MB 2 +#define APERTURE_SIZE_512MB 3 + +#define GTT_SIZE_1MB 1 +#define GTT_SIZE_2MB 2 + +#define OS_SELECTION_ANDROID 1 +#define OS_SELECTION_LINUX 4 + +#define DRAM_SPEED_800MTS 0 +#define DRAM_SPEED_1066MTS 1 +#define DRAM_SPEED_1333MTS 2 +#define DRAM_SPEED_1600MTS 3 + +#define DRAM_TYPE_DDR3 0 +#define DRAM_TYPE_DDR3L 1 +#define DRAM_TYPE_DDR3ECC 2 +#define DRAM_TYPE_LPDDR2 4 +#define DRAM_TYPE_LPDDR3 5 +#define DRAM_TYPE_DDR4 6 + +#define DIMM_WIDTH_X8 0 +#define DIMM_WIDTH_X16 1 +#define DIMM_WIDTH_X32 2 + +#define DIMM_DENSITY_1GBIT 0 +#define DIMM_DENSITY_2GBIT 1 +#define DIMM_DENSITY_4GBIT 2 +#define DIMM_DENSITY_8GBIT 3 + +#define DIMM_BUS_WIDTH_8BITS 0 +#define DIMM_BUS_WIDTH_16BITS 1 +#define DIMM_BUS_WIDTH_32BITS 2 +#define DIMM_BUS_WIDTH_64BITS 3 + +#define DIMM_SIDES_1RANKS 0 +#define DIMM_SIDES_2RANKS 1 #endif /* __FSP_CONFIGS_H__ */ diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt index f40011edef..691ae53b65 100644 --- a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt +++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt @@ -6,8 +6,8 @@ UPD data for configuring the SoC. All properties can be found within the `upd-region` struct in arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in -Intel's FSP Binary Configuration Tool for Bay Trail. This list of properties is -matched up to Intel's E3800 FSPv4 release. +Intel's FSP Binary Configuration Tool for Bay Trail. This list of properties +is matched up to Intel's E3800 FSPv4 release. # Boolean properties: @@ -44,8 +44,8 @@ matched up to Intel's E3800 FSPv4 release. - fsp,enable-memory-down If you set "fsp,enable-memory-down" you are strongly encouraged to provide an -"fsp,memory-down-params{};" to specify how your memory is configured. If you do -not set "fsp,enable-memory-down", then the DIMM SPD information will be +"fsp,memory-down-params{};" to specify how your memory is configured. If you +do not set "fsp,enable-memory-down", then the DIMM SPD information will be discovered by the FSP and used to setup main memory. @@ -72,41 +72,12 @@ discovered by the FSP and used to setup main memory. # Integer properties: - - fsp,dram-speed: - 0x0: "800 MHz" - 0x1: "1066 MHz" - 0x2: "1333 MHz" - 0x3: "1600 MHz" - + - fsp,dram-speed - fsp,dram-type - 0x0: "DDR3" - 0x1: "DDR3L" - 0x2: "DDR3U" - 0x4: "LPDDR2" - 0x5: "LPDDR3" - 0x6: "DDR4" - - fsp,dimm-width - 0x0: "x8" - 0x1: "x16" - 0x2: "x32" - - fsp,dimm-density - 0x0: "1 Gbit" - 0x1: "2 Gbit" - 0x2: "4 Gbit" - 0x3: "8 Gbit" - - fsp,dimm-bus-width - 0x0: "8 bits" - 0x1: "16 bits" - 0x2: "32 bits" - 0x3: "64 bits" - - fsp,dimm-sides - 0x0: "1 rank" - 0x1: "2 ranks" - - fsp,dimm-tcl - fsp,dimm-trpt-rcd - fsp,dimm-twr @@ -116,6 +87,9 @@ discovered by the FSP and used to setup main memory. - fsp,dimm-tfaw }; +For all integer properties, available options are listed in fsp_configs.h in +arch/x86/include/asm/arch-baytrail/fsp directory (eg: MRC_INIT_TSEG_SIZE_1MB). + Example (from MinnowMax Dual Core): ----------------------------------- @@ -125,18 +99,17 @@ Example (from MinnowMax Dual Core): fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <2>; + fsp,emmc-boot-mode = ; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; - fsp,enable-xhci; + fsp,sata-mode = ; fsp,enable-lpe; fsp,lpss-sio-enable-pci-mode; fsp,enable-dma0; @@ -150,27 +123,24 @@ Example (from MinnowMax Dual Core): fsp,enable-i2c6; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; - fsp,serial-debug-port-address = <0x3f8>; - fsp,serial-debug-port-type = <1>; - fsp,mrc-debug-msg; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; fsp,enable-igd; fsp,enable-memory-down; fsp,memory-down-params { compatible = "intel,baytrail-fsp-mdp"; - fsp,dram-speed = <1>; - fsp,dram-type = <1>; + fsp,dram-speed = ; + fsp,dram-type = ; fsp,dimm-0-enable; - fsp,dimm-width = <1>; - fsp,dimm-density = <2>; - fsp,dimm-bus-width = <3>; - fsp,dimm-sides = <0>; + fsp,dimm-width = ; + fsp,dimm-density = ; + fsp,dimm-bus-width = ; + fsp,dimm-sides = ; fsp,dimm-tcl = <0xb>; fsp,dimm-trpt-rcd = <0xb>; fsp,dimm-twr = <0xc>; From f8f291b0962c795fcb025338d5c2284e2357a669 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 31 May 2017 01:04:15 -0700 Subject: [PATCH 4/6] x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer At present lpe/lpss-sio/scc FSP properties are all boolean, but in fact for "enable-lpe" it has 3 possible options. This adds macros for these options and change the property from a boolean type to an integer type, and change their names to explicitly indicate what the property is really for. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass --- arch/x86/cpu/baytrail/fsp_configs.c | 11 ++++++----- arch/x86/dts/bayleybay.dts | 6 +++--- arch/x86/dts/baytrail_som-db5800-som-6867.dts | 4 ++-- arch/x86/dts/conga-qeval20-qa3-e3845.dts | 6 +++--- arch/x86/dts/dfi-bt700.dtsi | 6 +++--- arch/x86/dts/minnowmax.dts | 6 +++--- arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h | 10 ++++++++++ arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 6 +++--- doc/device-tree-bindings/misc/intel,baytrail-fsp.txt | 12 ++++++------ 9 files changed, 39 insertions(+), 28 deletions(-) diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index c48ac07385..45f9bf95da 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -175,9 +175,10 @@ void update_fsp_configs(struct fsp_config_data *config, fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, "fsp,enable-azalia"); fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci"); - fsp_upd->enable_lpe = fdtdec_get_bool(blob, node, "fsp,enable-lpe"); - fsp_upd->lpss_sio_enable_pci_mode = fdtdec_get_bool(blob, node, - "fsp,lpss-sio-enable-pci-mode"); + fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode", + LPE_MODE_PCI); + fsp_upd->lpss_sio_mode = fdtdec_get_int(blob, node, "fsp,lpss-sio-mode", + LPSS_SIO_MODE_PCI); fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0"); fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1"); fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0"); @@ -199,8 +200,8 @@ void update_fsp_configs(struct fsp_config_data *config, fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node, "fsp,mrc-debug-msg"); fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable"); - fsp_upd->scc_enable_pci_mode = fdtdec_get_bool(blob, node, - "fsp,scc-enable-pci-mode"); + fsp_upd->scc_mode = fdtdec_get_int(blob, node, "fsp,scc-mode", + SCC_MODE_PCI); fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node, "fsp,igd-render-standby"); fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node, diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index a577b9371b..0c314e0688 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -248,8 +248,8 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = ; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -264,7 +264,7 @@ fsp,igd-dvmt50-pre-alloc = ; fsp,aperture-size = ; fsp,gtt-size = ; - fsp,scc-enable-pci-mode; + fsp,scc-mode = ; fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index 3fc36f19c3..171e7ffee6 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -268,7 +268,7 @@ fsp,enable-sata; fsp,sata-mode = ; fsp,enable-azalia; - fsp,lpss-sio-enable-pci-mode; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -283,7 +283,7 @@ fsp,igd-dvmt50-pre-alloc = ; fsp,aperture-size = ; fsp,gtt-size = ; - fsp,scc-enable-pci-mode; + fsp,scc-mode = ; fsp,os-selection = ; fsp,enable-igd; }; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 369cea6b58..ae11ccc25a 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -258,8 +258,8 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = ; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-pwm0; @@ -267,7 +267,7 @@ fsp,igd-dvmt50-pre-alloc = ; fsp,aperture-size = ; fsp,gtt-size = ; - fsp,scc-enable-pci-mode; + fsp,scc-mode = ; fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index 33f2a9c7a2..04aa95ad52 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -261,8 +261,8 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = ; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -277,7 +277,7 @@ fsp,igd-dvmt50-pre-alloc = ; fsp,aperture-size = ; fsp,gtt-size = ; - fsp,scc-enable-pci-mode; + fsp,scc-mode = ; fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index a4e2fa211c..4c0a8fe26f 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -272,8 +272,8 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = ; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -288,7 +288,7 @@ fsp,igd-dvmt50-pre-alloc = ; fsp,aperture-size = ; fsp,gtt-size = ; - fsp,scc-enable-pci-mode; + fsp,scc-mode = ; fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h index 382cb79700..1c6c2479f0 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h @@ -93,4 +93,14 @@ struct fspinit_rtbuf { #define DIMM_SIDES_1RANKS 0 #define DIMM_SIDES_2RANKS 1 +#define LPE_MODE_DISABLED 0 +#define LPE_MODE_PCI 1 +#define LPE_MODE_ACPI 2 + +#define LPSS_SIO_MODE_ACPI 0 +#define LPSS_SIO_MODE_PCI 1 + +#define SCC_MODE_ACPI 0 +#define SCC_MODE_PCI 1 + #endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h index b083b6e5ec..8c07b3747f 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h @@ -47,8 +47,8 @@ struct __packed upd_region { uint8_t enable_azalia; /* Offset 0x002f */ uint32_t azalia_config_ptr; /* Offset 0x0030 */ uint8_t enable_xhci; /* Offset 0x0034 */ - uint8_t enable_lpe; /* Offset 0x0035 */ - uint8_t lpss_sio_enable_pci_mode; /* Offset 0x0036 */ + uint8_t lpe_mode; /* Offset 0x0035 */ + uint8_t lpss_sio_mode; /* Offset 0x0036 */ uint8_t enable_dma0; /* Offset 0x0037 */ uint8_t enable_dma1; /* Offset 0x0038 */ uint8_t enable_i2_c0; /* Offset 0x0039 */ @@ -67,7 +67,7 @@ struct __packed upd_region { uint8_t reserved2[5]; /* Offset 0x0046 */ uint8_t mrc_debug_msg; /* Offset 0x004b */ uint8_t isp_enable; /* Offset 0x004c */ - uint8_t scc_enable_pci_mode; /* Offset 0x004d */ + uint8_t scc_mode; /* Offset 0x004d */ uint8_t igd_render_standby; /* Offset 0x004e */ uint8_t txe_uma_enable; /* Offset 0x004f */ uint8_t os_selection; /* Offset 0x0050 */ diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt index 691ae53b65..929ae88c58 100644 --- a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt +++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt @@ -19,8 +19,6 @@ is matched up to Intel's E3800 FSPv4 release. - fsp,enable-sata - fsp,enable-azalia - fsp,enable-xhci -- fsp,enable-lpe -- fsp,lpss-sio-enable-pci-mode - fsp,enable-dma0 - fsp,enable-dma1 - fsp,enable-i2-c0 @@ -35,7 +33,6 @@ is matched up to Intel's E3800 FSPv4 release. - fsp,enable-hsi - fsp,mrc-debug-msg - fsp,isp-enable -- fsp,scc-enable-pci-mode - fsp,igd-render-standby - fsp,txe-uma-enable - fsp,emmc45-ddr50-enabled @@ -57,9 +54,12 @@ discovered by the FSP and used to setup main memory. - fsp,mrc-init-spd-addr2 - fsp,emmc-boot-mode - fsp,sata-mode +- fsp,lpe-mode +- fsp,lpss-sio-mode - fsp,igd-dvmt50-pre-alloc - fsp,aperture-size - fsp,gtt-size +- fsp,scc-mode - fsp,os-selection - fsp,emmc45-retune-timer-value @@ -110,8 +110,8 @@ Example (from MinnowMax Dual Core): fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = ; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -126,7 +126,7 @@ Example (from MinnowMax Dual Core): fsp,igd-dvmt50-pre-alloc = ; fsp,aperture-size = ; fsp,gtt-size = ; - fsp,scc-enable-pci-mode; + fsp,scc-mode = ; fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; From 37d1023264e7b73b72e0c42fd55de91c7018135d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 1 Jun 2017 03:41:13 -0700 Subject: [PATCH 5/6] x86: baytrail: Fix boot hang with a debug build It was observed that when -DDEBUG is used to generate a debug build, U-Boot does not boot on MinnowMax board. A workaround is to disable CONFIG_DEBUG_UART. The real issue is that in order to have the debug uart to work, BayTrail SoC needs to be configured so that its internal uart is available to be used as the debug uart. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass --- arch/x86/cpu/baytrail/Kconfig | 4 ++++ arch/x86/cpu/baytrail/early_uart.c | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig index 1c8ac370b3..6c85186486 100644 --- a/arch/x86/cpu/baytrail/Kconfig +++ b/arch/x86/cpu/baytrail/Kconfig @@ -17,4 +17,8 @@ config INTERNAL_UART reason, it is recommended that the UART port be used for debug purposes only, eg: U-Boot console. +config DEBUG_UART + bool + select DEBUG_UART_BOARD_INIT + endif diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c index 471d592b49..afab21f1dd 100644 --- a/arch/x86/cpu/baytrail/early_uart.c +++ b/arch/x86/cpu/baytrail/early_uart.c @@ -80,3 +80,8 @@ int setup_internal_uart(int enable) return 0; } + +void board_debug_uart_init(void) +{ + setup_internal_uart(1); +} From d7f7ba36b2edecb16393f8373cca833adb8ea6c3 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 1 Jun 2017 03:41:14 -0700 Subject: [PATCH 6/6] x86: fsp: Remove the call to set up internal uart in fsp_init() First of all, it's inappropriate to call setup_internal_uart() in a generic API fsp_init(), as CONFIG_INTERNAL_UART is an option that is only available on BayTrail platform. Secondly even for BayTrail, there is no need to call setup_internal_uart() at all, as Intel FSP will do this for us. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass --- arch/x86/lib/fsp/fsp_support.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index a480361211..ab8340c871 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -110,10 +110,6 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) struct upd_region *fsp_upd; #endif -#ifdef CONFIG_INTERNAL_UART - setup_internal_uart(1); -#endif - fsp_hdr = find_fsp_header(); if (fsp_hdr == NULL) { /* No valid FSP info header was found */