From 3ef2050a6a121d9b3cb3490695c8f863b72095e9 Mon Sep 17 00:00:00 2001 From: "Radu Pirea (NXP OSS)" Date: Fri, 18 Jun 2021 21:58:30 +0300 Subject: [PATCH 01/13] phy: add nxp tja1103 phy driver Add nxp tja1103 phy driver. Signed-off-by: Radu Pirea (NXP OSS) Reviewed-by: Ramon Fried --- MAINTAINERS | 5 + drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/nxp-c45-tja11xx.c | 348 ++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 + include/phy.h | 5 + 6 files changed, 368 insertions(+) create mode 100644 drivers/net/phy/nxp-c45-tja11xx.c diff --git a/MAINTAINERS b/MAINTAINERS index 4be95cc845..fbe6623d99 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -922,6 +922,11 @@ F: cmd/nvme.c F: include/nvme.h F: doc/develop/driver-model/nvme.rst +NXP C45 TJA11XX PHY DRIVER +M: Radu Pirea +S: Maintained +F: drivers/net/phy/nxp-c45-tja11xx.c + ONENAND #M: Lukasz Majewski S: Orphaned (Since 2017-01) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 070ffa82cb..405bf76753 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -197,6 +197,12 @@ config PHY_MSCC config PHY_NATSEMI bool "National Semiconductor Ethernet PHYs support" +config PHY_NXP_C45_TJA11XX + tristate "NXP C45 TJA11XX PHYs" + help + Enable support for NXP C45 TJA11XX PHYs. + Currently supports only the TJA1103 PHY. + config PHY_REALTEK bool "Realtek Ethernet PHYs support" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index e967f82201..218b8c7669 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o +obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c new file mode 100644 index 0000000000..f86e31f0d9 --- /dev/null +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NXP C45 PHY driver + * + * Copyright 2021 NXP + * Author: Radu Pirea + */ +#include +#include +#include +#include +#include +#include +#include + +#define PHY_ID_TJA_1103 0x001BB010 + +#define VEND1_DEVICE_CONTROL 0x0040 +#define DEVICE_CONTROL_RESET BIT(15) +#define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14) +#define DEVICE_CONTROL_CONFIG_ALL_EN BIT(13) + +#define VEND1_PORT_CONTROL 0x8040 +#define PORT_CONTROL_EN BIT(14) + +#define VEND1_PHY_CONTROL 0x8100 +#define PHY_CONFIG_EN BIT(14) +#define PHY_START_OP BIT(0) + +#define VEND1_PHY_CONFIG 0x8108 +#define PHY_CONFIG_AUTO BIT(0) + +#define VEND1_PORT_INFRA_CONTROL 0xAC00 +#define PORT_INFRA_CONTROL_EN BIT(14) + +#define VEND1_RXID 0xAFCC +#define VEND1_TXID 0xAFCD +#define ID_ENABLE BIT(15) + +#define VEND1_ABILITIES 0xAFC4 +#define RGMII_ID_ABILITY BIT(15) +#define RGMII_ABILITY BIT(14) +#define RMII_ABILITY BIT(10) +#define REVMII_ABILITY BIT(9) +#define MII_ABILITY BIT(8) +#define SGMII_ABILITY BIT(0) + +#define VEND1_MII_BASIC_CONFIG 0xAFC6 +#define MII_BASIC_CONFIG_REV BIT(8) +#define MII_BASIC_CONFIG_SGMII 0x9 +#define MII_BASIC_CONFIG_RGMII 0x7 +#define MII_BASIC_CONFIG_RMII 0x5 +#define MII_BASIC_CONFIG_MII 0x4 + +#define RGMII_PERIOD_PS 8000U +#define PS_PER_DEGREE div_u64(RGMII_PERIOD_PS, 360) +#define MIN_ID_PS 1644U +#define MAX_ID_PS 2260U +#define DEFAULT_ID_PS 2000U + +#define RESET_DELAY_MS 25 +#define CONF_EN_DELAY_US 450 + +struct nxp_c45_phy { + u32 tx_delay; + u32 rx_delay; +}; + +static int nxp_c45_soft_reset(struct phy_device *phydev) +{ + int tries = 10, ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, + DEVICE_CONTROL_RESET); + if (ret) + return ret; + + do { + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, + VEND1_DEVICE_CONTROL); + if (!(ret & DEVICE_CONTROL_RESET)) + return 0; + mdelay(RESET_DELAY_MS); + } while (tries--); + + return -EIO; +} + +static int nxp_c45_start_op(struct phy_device *phydev) +{ + return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, + PHY_START_OP); +} + +static int nxp_c45_config_enable(struct phy_device *phydev) +{ + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, + DEVICE_CONTROL_CONFIG_GLOBAL_EN | + DEVICE_CONTROL_CONFIG_ALL_EN); + udelay(CONF_EN_DELAY_US); + + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL, + PORT_CONTROL_EN); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, + PHY_CONFIG_EN); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL, + PORT_INFRA_CONTROL_EN); + + return 0; +} + +static u64 nxp_c45_get_phase_shift(u64 phase_offset_raw) +{ + /* The delay in degree phase is 73.8 + phase_offset_raw * 0.9. + * To avoid floating point operations we'll multiply by 10 + * and get 1 decimal point precision. + */ + phase_offset_raw *= 10; + phase_offset_raw -= 738; + return div_u64(phase_offset_raw, 9); +} + +static void nxp_c45_disable_delays(struct phy_device *phydev) +{ + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, 0); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, 0); +} + +static int nxp_c45_check_delay(struct phy_device *phydev, u32 delay) +{ + if (delay < MIN_ID_PS) { + pr_err("%s: delay value smaller than %u\n", + phydev->drv->name, MIN_ID_PS); + return -EINVAL; + } + + if (delay > MAX_ID_PS) { + pr_err("%s: delay value higher than %u\n", + phydev->drv->name, MAX_ID_PS); + return -EINVAL; + } + + return 0; +} + +static int nxp_c45_get_delays(struct phy_device *phydev) +{ + struct nxp_c45_phy *priv = phydev->priv; + int ret; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { + ret = dev_read_u32(phydev->dev, "tx-internal-delay-ps", + &priv->tx_delay); + if (ret) + priv->tx_delay = DEFAULT_ID_PS; + + ret = nxp_c45_check_delay(phydev, priv->tx_delay); + if (ret) { + pr_err("%s: tx-internal-delay-ps invalid value\n", + phydev->drv->name); + return ret; + } + } + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { + ret = dev_read_u32(phydev->dev, "rx-internal-delay-ps", + &priv->rx_delay); + if (ret) + priv->rx_delay = DEFAULT_ID_PS; + + ret = nxp_c45_check_delay(phydev, priv->rx_delay); + if (ret) { + pr_err("%s: rx-internal-delay-ps invalid value\n", + phydev->drv->name); + return ret; + } + } + + return 0; +} + +static void nxp_c45_set_delays(struct phy_device *phydev) +{ + struct nxp_c45_phy *priv = phydev->priv; + u64 tx_delay = priv->tx_delay; + u64 rx_delay = priv->rx_delay; + u64 degree; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { + degree = div_u64(tx_delay, PS_PER_DEGREE); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, + ID_ENABLE | nxp_c45_get_phase_shift(degree)); + } else { + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, 0); + } + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { + degree = div_u64(rx_delay, PS_PER_DEGREE); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, + ID_ENABLE | nxp_c45_get_phase_shift(degree)); + } else { + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, 0); + } +} + +static int nxp_c45_set_phy_mode(struct phy_device *phydev) +{ + int ret; + + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES); + pr_debug("%s: Clause 45 managed PHY abilities 0x%x\n", + phydev->drv->name, ret); + + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII: + if (!(ret & RGMII_ABILITY)) { + pr_err("%s: rgmii mode not supported\n", + phydev->drv->name); + return -EINVAL; + } + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, + MII_BASIC_CONFIG_RGMII); + nxp_c45_disable_delays(phydev); + break; + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + if (!(ret & RGMII_ID_ABILITY)) { + pr_err("%s: rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n", + phydev->drv->name); + return -EINVAL; + } + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, + MII_BASIC_CONFIG_RGMII); + ret = nxp_c45_get_delays(phydev); + if (ret) + return ret; + + nxp_c45_set_delays(phydev); + break; + case PHY_INTERFACE_MODE_MII: + if (!(ret & MII_ABILITY)) { + pr_err("%s: mii mode not supported\n", + phydev->drv->name); + return -EINVAL; + } + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, + MII_BASIC_CONFIG_MII); + break; + case PHY_INTERFACE_MODE_RMII: + if (!(ret & RMII_ABILITY)) { + pr_err("%s: rmii mode not supported\n", + phydev->drv->name); + return -EINVAL; + } + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, + MII_BASIC_CONFIG_RMII); + break; + case PHY_INTERFACE_MODE_SGMII: + if (!(ret & SGMII_ABILITY)) { + pr_err("%s: sgmii mode not supported\n", + phydev->drv->name); + return -EINVAL; + } + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, + MII_BASIC_CONFIG_SGMII); + break; + case PHY_INTERFACE_MODE_INTERNAL: + break; + default: + return -EINVAL; + } + + return 0; +} + +static int nxp_c45_config(struct phy_device *phydev) +{ + int ret; + + ret = nxp_c45_soft_reset(phydev); + if (ret) + return ret; + + ret = nxp_c45_config_enable(phydev); + if (ret) { + pr_err("%s: Failed to enable config\n", phydev->drv->name); + return ret; + } + + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG, + PHY_CONFIG_AUTO); + + ret = nxp_c45_set_phy_mode(phydev); + if (ret) { + pr_err("%s: Failed to set phy mode\n", phydev->drv->name); + return ret; + } + + phydev->autoneg = AUTONEG_DISABLE; + + return nxp_c45_start_op(phydev); +} + +static int nxp_c45_startup(struct phy_device *phydev) +{ + u32 reg; + + reg = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); + phydev->link = !!(reg & MDIO_STAT1_LSTATUS); + phydev->speed = SPEED_100; + phydev->duplex = DUPLEX_FULL; + return 0; +} + +static int nxp_c45_probe(struct phy_device *phydev) +{ + struct nxp_c45_phy *priv; + + priv = devm_kzalloc(phydev->priv, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + phydev->priv = priv; + + return 0; +} + +static struct phy_driver nxp_tja11xx = { + .name = "NXP C45 TJA1103", + .uid = PHY_ID_TJA_1103, + .mask = 0xfffff0, + .features = PHY_100BT1_FEATURES, + .probe = &nxp_c45_probe, + .config = &nxp_c45_config, + .startup = &nxp_c45_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_nxp_tja11xx_init(void) +{ + phy_register(&nxp_tja11xx); + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index ed197fa46d..69acb69460 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -529,6 +529,9 @@ int phy_init(void) #ifdef CONFIG_PHY_NATSEMI phy_natsemi_init(); #endif +#ifdef CONFIG_NXP_C45_TJA11XX_PHY + phy_nxp_tja11xx_init(); +#endif #ifdef CONFIG_PHY_REALTEK phy_realtek_init(); #endif diff --git a/include/phy.h b/include/phy.h index 2754421ed4..6b928636b6 100644 --- a/include/phy.h +++ b/include/phy.h @@ -51,6 +51,10 @@ struct udevice; PHY_100BT_FEATURES | \ PHY_DEFAULT_FEATURES) +#define PHY_100BT1_FEATURES (SUPPORTED_TP | \ + SUPPORTED_MII | \ + SUPPORTED_100baseT_Full) + #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ PHY_1000BT_FEATURES) @@ -523,6 +527,7 @@ int phy_micrel_ksz8xxx_init(void); int phy_micrel_ksz90x1_init(void); int phy_meson_gxl_init(void); int phy_natsemi_init(void); +int phy_nxp_tja11xx_init(void); int phy_realtek_init(void); int phy_smsc_init(void); int phy_teranetics_init(void); From 8a3987f47ad749fc2e37687bab6a049d92fe42e8 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 18 Jun 2021 15:26:21 -0700 Subject: [PATCH 02/13] cmd: net: add a 'net list' command to list network devs In a system with multiple network controllers it can be difficult to know the names of the various devices available. This is especially true for USB ether devices as they do not display device names upon detection. This is being added as a net sub-system in case other commands may want to be added or moved here. Note that this is only enabled for DM_ETH Example: U-Boot > net net - NET sub-system Usage: net list - list available devices U-Boot > net list eth0 : ethernet@2188000 00:d0:12:98:f5:47 active eth1 : e1000#0 00:d0:12:98:f5:48 eth2 : asix_eth 8c:ae:4c:f5:84:9d eth3 : asix_eth 8c:ae:4c:f9:41:e3 Signed-off-by: Tim Harvey Reviewed-by: Stefan Roese Reviewed-by: Ramon Fried --- cmd/net.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/cmd/net.c b/cmd/net.c index beb2877dfd..76c7e75125 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -480,3 +481,48 @@ U_BOOT_CMD( ); #endif /* CONFIG_CMD_LINK_LOCAL */ + +#ifdef CONFIG_DM_ETH +static int do_net_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + const struct udevice *current = eth_get_dev(); + unsigned char env_enetaddr[ARP_HLEN]; + const struct udevice *dev; + struct uclass *uc; + + uclass_id_foreach_dev(UCLASS_ETH, dev, uc) { + eth_env_get_enetaddr_by_index("eth", dev_seq(dev), env_enetaddr); + printf("eth%d : %s %pM %s\n", dev_seq(dev), dev->name, env_enetaddr, + current == dev ? "active" : ""); + } + return CMD_RET_SUCCESS; +} + +static struct cmd_tbl cmd_net[] = { + U_BOOT_CMD_MKENT(list, 1, 0, do_net_list, "", ""), +}; + +static int do_net(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct cmd_tbl *cp; + + cp = find_cmd_tbl(argv[1], cmd_net, ARRAY_SIZE(cmd_net)); + + /* Drop the net command */ + argc--; + argv++; + + if (!cp || argc > cp->maxargs) + return CMD_RET_USAGE; + if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp)) + return CMD_RET_SUCCESS; + + return cp->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD( + net, 2, 1, do_net, + "NET sub-system", + "list - list available devices\n" +); +#endif // CONFIG_DM_ETH From f26c9d7fedb6dce4dcd8f0e763adda707dcbeca6 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 28 Jun 2021 14:30:30 +0100 Subject: [PATCH 03/13] net: smc911x: Drop redundant CONFIG_SMC911X_16_BIT Kconfig symbol The SMC911x Ethernet driver needs to know which accessor functions it can use to access the MMIO registers. For that reason we have a Kconfig choice between 16 and 32-bit bus width. Since it's only those two options that we (and the Linux kernel) support, and there does not seem to be any evidence of another bus width anywhere, limit the Kconfig construct to a simple symbol. This simplifies the code and allows a later rework to be much easier. Signed-off-by: Andre Przywara Reviewed-by: Ramon Fried --- drivers/net/Kconfig | 17 +++++------------ drivers/net/smc911x.c | 12 ++---------- 2 files changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 9fc28b149d..2a7c8f9a7f 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -548,21 +548,14 @@ config SMC911X_BASE of the device (I/O space) endif #DM_ETH -choice - prompt "SMC911X bus width" - default SMC911X_16_BIT - config SMC911X_32_BIT - bool "Enable 32-bit interface" - -config SMC911X_16_BIT - bool "Enable 16-bit interface" + bool "Enable SMC911X 32-bit interface" + default n help - Define this if data bus is 16 bits. If your processor - automatically converts one 32 bit word to two 16 bit - words you may also try CONFIG_SMC911X_32_BIT. + Define this if data bus is 32 bits. If your processor use a + narrower 16 bit bus or cannot convert one 32 bit word to two 16 bit + words, leave this to "n". -endchoice endif #SMC911X config SUN7I_GMAC diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 7b79831c28..d596d96f4b 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -48,12 +48,6 @@ static const struct chip_id chip_ids[] = { #define DRIVERNAME "smc911x" -#if defined (CONFIG_SMC911X_32_BIT) && \ - defined (CONFIG_SMC911X_16_BIT) -#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \ - CONFIG_SMC911X_16_BIT shall be set" -#endif - #if defined (CONFIG_SMC911X_32_BIT) static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset) { @@ -64,7 +58,7 @@ static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val) { writel(val, priv->iobase + offset); } -#elif defined (CONFIG_SMC911X_16_BIT) +#else static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset) { return (readw(priv->iobase + offset) & 0xffff) | @@ -75,9 +69,7 @@ static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val) writew(val & 0xffff, priv->iobase + offset); writew(val >> 16, priv->iobase + offset + 2); } -#else -#error "SMC911X: undefined bus width" -#endif /* CONFIG_SMC911X_16_BIT */ +#endif /* CONFIG_SMC911X_32_BIT */ static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg) { From c08d4d792a099b3cdd4e726de89e9c6c0f0b4881 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 28 Jun 2021 14:30:31 +0100 Subject: [PATCH 04/13] net: smc911x: Determine bus width at runtime The SMC911x Ethernet MACs can be integrated using a 16 or 32-bit bus. The driver needs to know about this choice, which is the reason for us having a Kconfig symbol for that. Now this bus width is already described using a devicetree property, and since the driver is DM compliant and is using the DT now, we should query this at runtime. We leave the Kconfig choice around, in case the DT is missing this property. Signed-off-by: Andre Przywara Reviewed-by: Ramon Fried --- drivers/net/smc911x.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index d596d96f4b..3afebee440 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -28,6 +28,7 @@ struct smc911x_priv { phys_addr_t iobase; const struct chip_id *chipid; unsigned char enetaddr[6]; + bool use_32_bit_io; }; static const struct chip_id chip_ids[] = { @@ -48,28 +49,24 @@ static const struct chip_id chip_ids[] = { #define DRIVERNAME "smc911x" -#if defined (CONFIG_SMC911X_32_BIT) static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset) { - return readl(priv->iobase + offset); + if (priv->use_32_bit_io) + return readl(priv->iobase + offset); + + return (readw(priv->iobase + offset) & 0xffff) | + (readw(priv->iobase + offset + 2) << 16); } static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val) { - writel(val, priv->iobase + offset); + if (priv->use_32_bit_io) { + writel(val, priv->iobase + offset); + } else { + writew(val & 0xffff, priv->iobase + offset); + writew(val >> 16, priv->iobase + offset + 2); + } } -#else -static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset) -{ - return (readw(priv->iobase + offset) & 0xffff) | - (readw(priv->iobase + offset + 2) << 16); -} -static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val) -{ - writew(val & 0xffff, priv->iobase + offset); - writew(val >> 16, priv->iobase + offset + 2); -} -#endif /* CONFIG_SMC911X_32_BIT */ static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg) { @@ -493,6 +490,8 @@ int smc911x_initialize(u8 dev_num, int base_addr) priv->iobase = base_addr; priv->dev.iobase = base_addr; + priv->use_32_bit_io = CONFIG_IS_ENABLED(SMC911X_32_BIT); + /* Try to detect chip. Will fail if not present. */ ret = smc911x_detect_chip(priv); if (ret) { @@ -603,10 +602,18 @@ static int smc911x_of_to_plat(struct udevice *dev) { struct smc911x_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); + u32 io_width; + int ret; pdata->iobase = dev_read_addr(dev); priv->iobase = pdata->iobase; + ret = dev_read_u32(dev, "reg-io-width", &io_width); + if (!ret) + priv->use_32_bit_io = (io_width == 4); + else + priv->use_32_bit_io = CONFIG_IS_ENABLED(SMC911X_32_BIT); + return 0; } From 39dca76c34ebd06a1d7f9832598f697ff0dc8127 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 29 Jun 2021 20:53:11 +0300 Subject: [PATCH 05/13] arm: dts: ls1028a: enable the switch CPU port for the LS1028A-QDS Due to an upstream change, the ls1028a.dtsi bindings for the mscc_felix switch got accepted with all ports disabled by default and with no link to the DSA master - this needs to be done on a per board basis. Note that enetc-2 is not currently disabled in the ls1028a.dtsi, but presumably at some point it might become. Explicitly enable it in the QDS device trees anyway, to proactively avoid issues when that happens. Fixes: a7fdac7e2a2a ("arm: dts: ls1028a: define QDS networking protocol combinations") Signed-off-by: Vladimir Oltean Reviewed-by: Ramon Fried --- arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 9 +++++++++ arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 9 +++++++++ arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi | 9 +++++++++ arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi | 9 +++++++++ arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi | 9 +++++++++ arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi | 9 +++++++++ arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 9 +++++++++ arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 9 +++++++++ 8 files changed, 72 insertions(+) diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi index fb1836a8ae..5a0f060c16 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi @@ -20,6 +20,10 @@ #include "fsl-sch-30841.dtsi" }; +&enetc2 { + status = "okay"; +}; + &mscc_felix { status = "okay"; }; @@ -47,3 +51,8 @@ phy-mode = "sgmii-2500"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; }; + +&mscc_felix_port4 { + ethernet = <&enetc2>; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi index 1d02a3e11d..39a83e10c4 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi @@ -9,6 +9,10 @@ #include "fsl-sch-30841.dtsi" }; +&enetc2 { + status = "okay"; +}; + &mscc_felix { status = "okay"; }; @@ -24,3 +28,8 @@ phy-mode = "sgmii-2500"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; }; + +&mscc_felix_port4 { + ethernet = <&enetc2>; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi index c92dd1bd2e..021fe3fbc6 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi @@ -34,6 +34,10 @@ #include "fsl-sch-24801.dtsi" }; +&enetc2 { + status = "okay"; +}; + &mscc_felix { status = "okay"; }; @@ -61,3 +65,8 @@ phy-mode = "sgmii"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; }; + +&mscc_felix_port4 { + ethernet = <&enetc2>; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi index 941f7472eb..b6704d8089 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi @@ -19,6 +19,10 @@ #include "fsl-sch-24801.dtsi" }; +&enetc2 { + status = "okay"; +}; + &mscc_felix { status = "okay"; }; @@ -46,3 +50,8 @@ phy-mode = "sgmii"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; }; + +&mscc_felix_port4 { + ethernet = <&enetc2>; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi index 7e483e656e..8c10897e56 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi @@ -19,6 +19,10 @@ #include "fsl-sch-30841.dtsi" }; +&enetc2 { + status = "okay"; +}; + &mscc_felix { status = "okay"; }; @@ -46,3 +50,8 @@ phy-mode = "usxgmii"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>; }; + +&mscc_felix_port4 { + ethernet = <&enetc2>; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi index 49fffdb9cb..1d800dacef 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi @@ -13,6 +13,10 @@ #include "fsl-sch-28021.dtsi" }; +&enetc2 { + status = "okay"; +}; + &mscc_felix { status = "okay"; }; @@ -40,3 +44,8 @@ phy-mode = "qsgmii"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>; }; + +&mscc_felix_port4 { + ethernet = <&enetc2>; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi index 8347462f4c..1fb2cdf0c2 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi @@ -9,6 +9,10 @@ #include "fsl-sch-30842.dtsi" }; +&enetc2 { + status = "okay"; +}; + &mscc_felix { status = "okay"; }; @@ -18,3 +22,8 @@ phy-mode = "sgmii-2500"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; }; + +&mscc_felix_port4 { + ethernet = <&enetc2>; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi index 6be3b5094c..2333f74e5a 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi @@ -9,6 +9,10 @@ #include "fsl-sch-30842.dtsi" }; +&enetc2 { + status = "okay"; +}; + &mscc_felix { status = "okay"; }; @@ -18,3 +22,8 @@ phy-mode = "sgmii-2500"; phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>; }; + +&mscc_felix_port4 { + ethernet = <&enetc2>; + status = "okay"; +}; From aee4479a856dabd39ede99ecb80525ed70954c05 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 29 Jun 2021 20:53:12 +0300 Subject: [PATCH 06/13] arm: dts: ls1028a: enable internal RGMII delays for the LS1028A-QDS AR8035 PHY There are no PCB trace delays on this board, so the PHY needs to enable its internal ones in order to have a proper electrical connection to the enetc MAC. Fixes: b32e9a757837 ("arm: dts: ls1028a updates for network interfaces") Signed-off-by: Vladimir Oltean Reviewed-by: Ramon Fried --- arch/arm/dts/fsl-ls1028a-qds.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index da89ff96e9..69632fa796 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -251,7 +251,7 @@ &enetc1 { status = "okay"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <&qds_phy0>; }; From 9feb6366809942cfd29eeadb9b1c935d1c2dfc3f Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 29 Jun 2021 20:53:13 +0300 Subject: [PATCH 07/13] arm: dts: ls1028a: declare the fixed-link speeds for the internal ENETC ports To comply with the device tree bindings expectations for an Ethernet controller, as well as to simplify the driver code, declare fixed-link nodes for the internal ENETC ports (attached to the mscc_felix switch). Signed-off-by: Vladimir Oltean Reviewed-by: Ramon Fried --- arch/arm/dts/fsl-ls1028a.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index c7c725a4fc..21f4ef78a0 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -144,12 +144,22 @@ reg = <0x000200 0 0 0 0>; status = "okay"; phy-mode = "internal"; + + fixed-link { + speed = <2500>; + full-duplex; + }; }; mdio0: pci@0,3 { #address-cells=<0>; #size-cells=<1>; reg = <0x000300 0 0 0 0>; status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; }; mscc_felix: pci@0,5 { From bec7d5342d031ddfc4558aaafc1e6e63e5652917 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 29 Jun 2021 20:53:14 +0300 Subject: [PATCH 08/13] arm: dts: ls1028a: disable enetc-2 by default The enetc-2 port is used as DSA master (connected back-to-back to mscc_felix_port4). Since the convention is to not enable ports in the common SoC dtsi unless they are used on the board, then enable enetc-2 only when mscc_felix_port4 itself is enabled. All existing device trees appear to adhere to this rule, so disable enetc-2 in the SoC dtsi. Signed-off-by: Vladimir Oltean Reviewed-by: Ramon Fried --- arch/arm/dts/fsl-ls1028a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 21f4ef78a0..50f9b527cd 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -142,7 +142,7 @@ }; enetc2: pci@0,2 { reg = <0x000200 0 0 0 0>; - status = "okay"; + status = "disabled"; phy-mode = "internal"; fixed-link { From cd8817ac73bab6fd352b93bbd675cc50083f241d Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 29 Jun 2021 20:53:15 +0300 Subject: [PATCH 09/13] net: enetc: require a PHY device when probing Given that even a fixed-link has an associated phy_device, there is no reason to operate in a mode when dm_eth_phy_connect fails. Remove the driver checks for a NULL priv->phy and just return -ENODEV when that happens. Copyright updated according to corporate requirements. Signed-off-by: Vladimir Oltean Reviewed-by: Ramon Fried --- drivers/net/fsl_enetc.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index f6fc7801b9..9c198a1039 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * ENETC ethernet controller driver - * Copyright 2017-2019 NXP + * Copyright 2017-2021 NXP */ #include @@ -281,21 +281,20 @@ static void enetc_start_pcs(struct udevice *dev) } /* Configure the actual/external ethernet PHY, if one is found */ -static void enetc_config_phy(struct udevice *dev) +static int enetc_config_phy(struct udevice *dev) { struct enetc_priv *priv = dev_get_priv(dev); int supported; priv->phy = dm_eth_phy_connect(dev); - if (!priv->phy) - return; + return -ENODEV; supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full; priv->phy->supported &= supported; priv->phy->advertising &= supported; - phy_config(priv->phy); + return phy_config(priv->phy); } /* @@ -335,9 +334,8 @@ static int enetc_probe(struct udevice *dev) dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); enetc_start_pcs(dev); - enetc_config_phy(dev); - return 0; + return enetc_config_phy(dev); } /* @@ -550,8 +548,7 @@ static int enetc_start(struct udevice *dev) enetc_setup_mac_iface(dev); - if (priv->phy) - phy_startup(priv->phy); + phy_startup(priv->phy); return 0; } From 71346a84860c67827ef4852bc1c0ad31ac3f46ed Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 29 Jun 2021 20:53:16 +0300 Subject: [PATCH 10/13] net: enetc: force the RGMII MAC speed/duplex instead of using in-band signaling The RGMII spec supports optional in-band status reporting for the speed and duplex negotiated on the copper side, and the ENETC driver enables this feature by default. However, this does not work when the PHY does not implement the in-band reporting, or when there is a MAC-to-MAC connection described using a fixed-link. In that case, it would be better to disable the feature in the ENETC MAC and always force the speed and duplex to the values that were negotiated and retrieved over MDIO once the autoneg is finished. Since this works always, we just do it unconditionally and drop the in-band code. Note that because we need to wait for the autoneg to complete, we need to move enetc_setup_mac_iface() after phy_startup() returns, and then pass the phydev pointer all the way to enetc_init_rgmii(). The same considerations have led to a similar Linux driver patch as well: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c76a97218dcbb2cb7cec1404ace43ef96c87d874 Signed-off-by: Vladimir Oltean Reviewed-by: Ramon Fried --- drivers/net/fsl_enetc.c | 44 ++++++++++++++++++++++++++++++----------- drivers/net/fsl_enetc.h | 7 ++++++- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 9c198a1039..6a5a38c1ff 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -178,21 +178,43 @@ static int enetc_init_sgmii(struct udevice *dev) } /* set up MAC for RGMII */ -static int enetc_init_rgmii(struct udevice *dev) +static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) { struct enetc_priv *priv = dev_get_priv(dev); - u32 if_mode; + u32 old_val, val; - /* enable RGMII AN */ - if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE); - if_mode |= ENETC_PM_IF_MODE_AN_ENA; - enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode); + old_val = val = enetc_read_port(priv, ENETC_PM_IF_MODE); - return 0; + /* disable unreliable RGMII in-band signaling and force the MAC into + * the speed negotiated by the PHY. + */ + val &= ~ENETC_PM_IF_MODE_AN_ENA; + + if (phydev->speed == SPEED_1000) { + val &= ~ENETC_PM_IFM_SSP_MASK; + val |= ENETC_PM_IFM_SSP_1000; + } else if (phydev->speed == SPEED_100) { + val &= ~ENETC_PM_IFM_SSP_MASK; + val |= ENETC_PM_IFM_SSP_100; + } else if (phydev->speed == SPEED_10) { + val &= ~ENETC_PM_IFM_SSP_MASK; + val |= ENETC_PM_IFM_SSP_10; + } + + if (phydev->duplex == DUPLEX_FULL) + val |= ENETC_PM_IFM_FULL_DPX; + else + val &= ~ENETC_PM_IFM_FULL_DPX; + + if (val == old_val) + return; + + enetc_write_port(priv, ENETC_PM_IF_MODE, val); } /* set up MAC configuration for the given interface type */ -static void enetc_setup_mac_iface(struct udevice *dev) +static void enetc_setup_mac_iface(struct udevice *dev, + struct phy_device *phydev) { struct enetc_priv *priv = dev_get_priv(dev); u32 if_mode; @@ -202,7 +224,7 @@ static void enetc_setup_mac_iface(struct udevice *dev) case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: - enetc_init_rgmii(dev); + enetc_init_rgmii(dev, phydev); break; case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_USXGMII: @@ -546,10 +568,10 @@ static int enetc_start(struct udevice *dev) enetc_setup_tx_bdr(dev); enetc_setup_rx_bdr(dev); - enetc_setup_mac_iface(dev); - phy_startup(priv->phy); + enetc_setup_mac_iface(dev, priv->phy); + return 0; } diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h index 110c1d78fb..69f2f4aaff 100644 --- a/drivers/net/fsl_enetc.h +++ b/drivers/net/fsl_enetc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * ENETC ethernet controller driver - * Copyright 2017-2019 NXP + * Copyright 2017-2021 NXP */ #ifndef _ENETC_H @@ -77,6 +77,11 @@ enum enetc_bdr_type {TX, RX}; #define ENETC_PM_IF_MODE 0x8300 #define ENETC_PM_IF_MODE_RG BIT(2) #define ENETC_PM_IF_MODE_AN_ENA BIT(15) +#define ENETC_PM_IFM_SSP_MASK GENMASK(14, 13) +#define ENETC_PM_IFM_SSP_1000 (2 << 13) +#define ENETC_PM_IFM_SSP_100 (0 << 13) +#define ENETC_PM_IFM_SSP_10 (1 << 13) +#define ENETC_PM_IFM_FULL_DPX BIT(12) #define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0) /* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */ From c4428507683d2abb840e0752feea8f2fa465ca94 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 29 Jun 2021 20:53:17 +0300 Subject: [PATCH 11/13] net: enetc: propagate the return code from phy_startup() to eth_ops::start Make sure that errors in the PHY driver .startup() method, such as no link, are propagated and not ignored. Signed-off-by: Vladimir Oltean Reviewed-by: Ramon Fried --- drivers/net/fsl_enetc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 6a5a38c1ff..566cdc7e54 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -568,11 +568,9 @@ static int enetc_start(struct udevice *dev) enetc_setup_tx_bdr(dev); enetc_setup_rx_bdr(dev); - phy_startup(priv->phy); - enetc_setup_mac_iface(dev, priv->phy); - return 0; + return phy_startup(priv->phy); } /* From 515ed9df24c91d4447986cf35c249aaf04a71f5a Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 23 Jun 2021 13:56:02 +0200 Subject: [PATCH 12/13] board: sl28: add DSA support for variant 2 Now that u-boot gained DSA support, and it is already enabled for the kontron_sl28 board, add the last missing piece and enable the corresponding devices it in the device tree. Signed-off-by: Michael Walle --- .../fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi | 7 ++++ .../arm/dts/fsl-ls1028a-kontron-sl28-var2.dts | 40 +++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi index 79b771e074..4e0ce3f77d 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi @@ -1,2 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ #include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" + +/ { + aliases { + ethernet0 = &mscc_felix_port0; + ethernet1 = &mscc_felix_port1; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts index 1ea1265bcf..7a3aa21408 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts @@ -22,4 +22,44 @@ /delete-property/ phy-handle; }; +&enetc2 { + status = "okay"; +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + label = "gbe0"; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + status = "okay"; +}; + +&mscc_felix_port1 { + label = "gbe1"; + phy-handle = <&phy1>; + phy-mode = "sgmii"; + status = "okay"; +}; + +&mscc_felix_port4 { + ethernet = <&enetc2>; + status = "okay"; +}; + /delete-node/ &phy0; +&mdio0 { + phy0: ethernet-phy@5 { + reg = <0x5>; + eee-broken-1000t; + eee-broken-100tx; + }; + + phy1: ethernet-phy@4 { + reg = <0x4>; + eee-broken-1000t; + eee-broken-100tx; + }; +}; From 036e3622bf8394ff229ea0d348aa9a9a60e2c27a Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 30 Mar 2021 14:34:50 +0200 Subject: [PATCH 13/13] net: dwc_eth_qos: cosmetic: remove unused define EQOS_DESCRIPTOR_ALIGN Remove the define EQOS_DESCRIPTOR_ALIGN unused since the commit 6f1e668d964e ("net: dwc_eth_qos: Pad descriptors to cacheline size") Signed-off-by: Patrick Delaunay Acked-by: Marek Vasut Reviewed-by: Ramon Fried --- drivers/net/dwc_eth_qos.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index b012bed517..f048e9d585 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -238,8 +238,6 @@ struct eqos_tegra186_regs { #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31) /* Descriptors */ -/* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */ -#define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN #define EQOS_DESCRIPTORS_TX 4 #define EQOS_DESCRIPTORS_RX 4 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)