nxp: Migrate CONFIG_DDR_CLK_FREQ to Kconfig

As this symbol can either be a fixed value or the function
get_board_ddr_clk, migration is tricky.  Introduce a choice of DYNAMIC
or STATIC_DDR_CLK_FREQ.  If DYNAMIC, we continue to use the board
defined get_board_ddr_clk function.  If STATIC, set CONFIG_DDR_CLK_FREQ
to that value and now include/clock_legacy.h contains the function
prototype or defines get_board_ddr_clk() to that static value.  Update
callers to test for DYNAMIC or STATIC.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2021-08-21 13:50:17 -04:00
parent 222d22a39a
commit efb5dab7ba
152 changed files with 166 additions and 89 deletions

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@@ -11,4 +11,15 @@ int get_clocks(void);
unsigned long get_bus_freq(unsigned long dummy);
int get_serial_clock(void);
/*
* If we have CONFIG_DYNAMIC_DDR_CLK_FREQ then there will be an
* implentation of get_board_ddr_clk() somewhere. Otherwise we have
* a static value to use now.
*/
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void);
#else
#define get_board_ddr_clk() CONFIG_DDR_CLK_FREQ
#endif
#endif

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@@ -153,7 +153,6 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
#define CONFIG_HWCONFIG

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@@ -134,11 +134,9 @@
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
/*
* These can be toggled for performance analysis, otherwise use default.

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@@ -164,7 +164,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 66666666
/*
* These can be toggled for performance analysis, otherwise use default.

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@@ -109,11 +109,9 @@
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
/*
* Config the L3 Cache as L3 SRAM

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@@ -98,11 +98,9 @@
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ 66660000
#define CONFIG_DDR_CLK_FREQ 133330000
/*
* Config the L3 Cache as L3 SRAM

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@@ -242,11 +242,9 @@
"bootm 0x01000000 - 0x00f00000"
#define CONFIG_SYS_CLK_FREQ 66666666
#define CONFIG_DDR_CLK_FREQ 133333333
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
/*

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@@ -149,7 +149,6 @@
#define CONFIG_LBA48
#define CONFIG_SYS_CLK_FREQ 66666666
#define CONFIG_DDR_CLK_FREQ 66666666
#define CONFIG_HWCONFIG

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@@ -26,12 +26,6 @@
CONFIG_KM_RESERVED_PRAM) >> 10)
#define CONFIG_SYS_CLK_FREQ 66666666
/*
* Take into account default implementation where DDR_FDBK_MULTI is consider as
* configured for DDR_PLL = 2*MEM_PLL_RAT.
* In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT.
*/
#define CONFIG_DDR_CLK_FREQ (100000000 >> 1)
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)

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@@ -177,7 +177,6 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DDR_CLK_FREQ 66666666
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

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@@ -53,7 +53,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
/* ethernet */

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@@ -20,7 +20,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
/*
* DDR: 800 MHz ( 1600 MT/s data rate )

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@@ -25,16 +25,13 @@
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define CONFIG_QIXIS_I2C_ACCESS
#else
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#endif
#ifdef CONFIG_RAMBOOT_PBL

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@@ -22,7 +22,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf

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@@ -23,7 +23,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf

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@@ -9,7 +9,6 @@
#include "ls1028a_common.h"
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
/* DDR */

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@@ -9,7 +9,6 @@
#include "ls1028a_common.h"
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
#define CONFIG_SYS_RTC_BUS_NUM 0

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@@ -10,11 +10,9 @@
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -9,7 +9,6 @@
#include "ls1043a_common.h"
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define CONFIG_LAYERSCAPE_NS_ACCESS

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@@ -9,7 +9,6 @@
#include "ls1046a_common.h"
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define CONFIG_LAYERSCAPE_NS_ACCESS

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@@ -10,11 +10,9 @@
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -10,7 +10,6 @@
#include "ls1046a_common.h"
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define CONFIG_LAYERSCAPE_NS_ACCESS

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@@ -11,7 +11,6 @@
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
#ifdef CONFIG_TFABOOT
@@ -23,11 +22,9 @@ unsigned long get_board_ddr_clk(void);
#define SYS_NO_FLASH
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#else
#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#endif
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)

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@@ -17,7 +17,6 @@
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */

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@@ -11,7 +11,6 @@
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
#ifdef CONFIG_FSL_QSPI
@@ -21,7 +20,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
#define CONFIG_DDR_SPD

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@@ -36,7 +36,6 @@ unsigned long get_board_sys_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ 133333333
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
#define CONFIG_DDR_SPD

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@@ -151,11 +151,9 @@
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
#define CONFIG_HWCONFIG

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@@ -157,7 +157,6 @@
#else
#define CONFIG_SYS_CLK_FREQ 66666666
#endif
#define CONFIG_DDR_CLK_FREQ 66666666
#define CONFIG_HWCONFIG
/*