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* Add start-up delay to make sure power has stabilized before

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attempting to switch on USB on SX1 board.

* Patch by Josef Wagner, 18 Mar 2004:
  - Add support for MicroSys XM250 board (PXA255)
  - Add support for MicroSys PM828 board (MPC8280)
  - Add support for 32 MB Flash on PM825/826
  - new SDRAM refresh rate for PM825/PM826
  - added support for MicroSys PM520 (MPC5200)
  - replaced Query by Identify command in CPU86/flash.c
    to support 28F160F3B

* Fix wrap around problem with udelay() on ARM920T

* Add support for Macronix flash on TRAB board
This commit is contained in:
wdenk
2004-03-23 20:18:25 +00:00
parent 7d7ce4125f
commit efa329cb89
35 changed files with 4510 additions and 78 deletions
Download Patch File Download Diff File Expand all files Collapse all files

239
include/configs/PM520.h Normal file
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@@ -0,0 +1,239 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5200
#define CONFIG_MPC5XXX 1 /* This is an MPC5xxx CPU */
#define CONFIG_PM520 1 /* ... on PM520 board */
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_NET_MULTI 1
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#undef CONFIG_NS8382X
#define ADD_PCI_CMD CFG_CMD_PCI
#else /* MPC5100 */
#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
#endif
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_DATE)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/ram rw"
#if defined(CONFIG_MPC5200)
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#endif
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
#define CFG_I2C_SPEED 100000 /* 100 kHz */
#define CFG_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
#define CFG_I2C_EEPROM_ADDR 0x58
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/*
* RTC configuration
*/
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR 0x51
/*
* Flash configuration
*/
#define CFG_FLASH_BASE 0xff800000
#define CFG_FLASH_SIZE 0x00800000
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x10000
#define CFG_ENV_SECT_SIZE 0x40000
#define CONFIG_ENV_OVERWRITE 1
/*
* Memory map
*/
#define CFG_MBAR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_DEFAULT_MBAR 0x80000000
/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT 1
#endif
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5XXX_FEC 1
#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
#define CONFIG_PHY_ADDR 0x00
/*
* GPIO configuration
*/
#define CFG_GPS_PORT_CONFIG 0x10000004
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* Various low-level settings
*/
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL HID0_ICE
#else
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL 0
#endif
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG 0x0004fb00
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
#define CFG_RESET_ADDRESS 0xff000000
#endif /* __CONFIG_H */

28
include/configs/PM826.h
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@@ -1,5 +1,5 @@
/*
* (C) Copyright 2001
* (C) Copyright 2001-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -220,15 +220,18 @@
/*-----------------------------------------------------------------------
* Flash and Boot ROM mapping
*/
#ifdef CONFIG_FLASH_32MB
#define CFG_FLASH0_BASE 0x40000000
#define CFG_FLASH0_SIZE 0x02000000
#else
#define CFG_FLASH0_BASE 0xFF000000
#define CFG_FLASH0_SIZE 0x00800000
#endif
#define CFG_BOOTROM_BASE 0xFF800000
#define CFG_BOOTROM_SIZE 0x00080000
#define CFG_FLASH0_BASE 0xFF000000
#define CFG_FLASH0_SIZE 0x02000000
#define CFG_DOC_BASE 0xFF800000
#define CFG_DOC_SIZE 0x00100000
/* Flash bank size (for preliminary settings)
*/
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
@@ -237,8 +240,11 @@
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
#ifdef CONFIG_FLASH_32MB
#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */
#else
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#endif
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
@@ -426,7 +432,6 @@
* ---- --- ------- ------ ------
* 0 60x GPCM 64 bit FLASH
* 1 60x SDRAM 64 bit SDRAM
* 2 Local SDRAM 32 bit SDRAM
*
*/
@@ -440,7 +445,12 @@
*/
#define CFG_MIN_AM_MASK 0xC0000000
#define CFG_MPTPR 0x1F00
/*
* we use the same values for 32 MB and 128 MB SDRAM
* refresh rate = 7.73 uS (64 MHz Bus Clock)
*/
#define CFG_MPTPR 0x2000
#define CFG_PSRT 0x0E
#define CFG_MRS_OFFS 0x00000000
@@ -512,7 +522,7 @@
/* Bank 2 - SDRAM
*/
#define CFG_PSRT 0x0F
#ifndef CFG_RAMBOOT
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\

565
include/configs/PM828.h Normal file
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@@ -0,0 +1,565 @@
/*
* (C) Copyright 2001-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#undef CFG_RAMBOOT
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#define CONFIG_PM828 1 /* ...on a PM828 module */
#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp;" \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
"bootm"
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
# define CFG_I2C_SPEED 50000
# define CFG_I2C_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
else iop->pdat &= ~0x00010000
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR 0x51
/*
* select serial console configuration
*
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
* for SCC).
*
* if CONFIG_CONS_NONE is defined, then the serial console routines must
* defined elsewhere (for example, on the cogent platform, there are serial
* ports on the motherboard which are used for the serial console - see
* cogent/cma101/serial.[ch]).
*/
#define CONFIG_CONS_ON_SMC /* define if console on SMC */
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
#undef CONFIG_CONS_NONE /* define if console on something else*/
#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
/*
* select ethernet configuration
*
* if CONFIG_ETHER_ON_SCC is selected, then
* - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
* - CONFIG_NET_MULTI must not be defined
*
* if CONFIG_ETHER_ON_FCC is selected, then
* - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
* - CONFIG_NET_MULTI must be defined
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
* from CONFIG_COMMANDS to remove support for networking.
*/
#define CONFIG_NET_MULTI
#undef CONFIG_ETHER_NONE /* define if ether on something else */
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
/*
* - Rx-CLK is CLK11
* - Tx-CLK is CLK10
*/
#define CONFIG_ETHER_ON_FCC1
# define CFG_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
#ifndef CONFIG_DB_CR826_J30x_ON
# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
#else
# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
#endif
/*
* - Rx-CLK is CLK15
* - Tx-CLK is CLK14
*/
#define CONFIG_ETHER_ON_FCC2
# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
/*
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
* - Enable Full Duplex in FSMR
*/
# define CFG_CPMFCR_RAMTYPE 0
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN 100000000 /* in Hz */
#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE 230400
#else
#define CONFIG_BAUDRATE 9600
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
#ifdef CONFIG_PCI
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_BEDBUG | \
CFG_CMD_DATE | \
CFG_CMD_DOC | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_PCI)
#else /* ! PCI */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_BEDBUG | \
CFG_CMD_DATE | \
CFG_CMD_DOC | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C )
#endif /* CONFIG_PCI */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Disk-On-Chip configuration
*/
#define CFG_DOC_SHORT_TIMEOUT
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Flash and Boot ROM mapping
*/
#define CFG_BOOTROM_BASE 0xFF800000
#define CFG_BOOTROM_SIZE 0x00080000
#define CFG_FLASH0_BASE 0x40000000
#define CFG_FLASH0_SIZE 0x02000000
#define CFG_DOC_BASE 0xFF800000
#define CFG_DOC_SIZE 0x00100000
/* Flash bank size (for preliminary settings)
*/
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
#if 0
/* Start port with environment in flash; switch to EEPROM later */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
#define CFG_ENV_SIZE 0x40000
#define CFG_ENV_SECT_SIZE 0x40000
#else
/* Final version: environment in EEPROM */
#define CFG_ENV_IS_IN_EEPROM 1
#define CFG_I2C_EEPROM_ADDR 0x58
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_ENV_OFFSET 512
#define CFG_ENV_SIZE (2048 - 512)
#endif
/*-----------------------------------------------------------------------
* Hard Reset Configuration Words
*
* if you change bits in the HRCW, you must also change the CFG_*
* defines for the various registers affected by the HRCW e.g. changing
* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
*/
#if defined(CONFIG_BOOT_ROM)
#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
#else
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
#endif
/* no slaves so just fill with zeros */
#define CFG_HRCW_SLAVE1 0
#define CFG_HRCW_SLAVE2 0
#define CFG_HRCW_SLAVE3 0
#define CFG_HRCW_SLAVE4 0
#define CFG_HRCW_SLAVE5 0
#define CFG_HRCW_SLAVE6 0
#define CFG_HRCW_SLAVE7 0
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xF0000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*
* 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
* is mapped at SDRAM_BASE2_PRELIM.
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE CFG_FLASH0_BASE
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT
#endif
#ifdef CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* HIDx - Hardware Implementation-dependent Registers 2-11
*-----------------------------------------------------------------------
* HID0 also contains cache control - initially enable both caches and
* invalidate contents, then the final state leaves only the instruction
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
* but Soft reset does not.
*
* HID1 has only read-only information - nothing to set.
*/
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
#define CFG_HID2 0
/*-----------------------------------------------------------------------
* RMR - Reset Mode Register 5-5
*-----------------------------------------------------------------------
* turn on Checkstop Reset Enable
*/
#define CFG_RMR RMR_CSRE
/*-----------------------------------------------------------------------
* BCR - Bus Configuration 4-25
*-----------------------------------------------------------------------
*/
#define BCR_APD01 0x10000000
#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 4-31
*-----------------------------------------------------------------------
*/
#if 0
#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
#else
#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 4-35
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */
/*-----------------------------------------------------------------------
* TMCNTSC - Time Counter Status and Control 4-40
*-----------------------------------------------------------------------
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
* and enable Time Counter
*/
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 4-42
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
* Periodic timer
*/
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
/*-----------------------------------------------------------------------
* SCCR - System Clock Control 9-8
*-----------------------------------------------------------------------
*/
#define CFG_SCCR (SCCR_DFBRG00)
/*-----------------------------------------------------------------------
* RCCR - RISC Controller Configuration 13-7
*-----------------------------------------------------------------------
*/
#define CFG_RCCR 0
/*
* Init Memory Controller:
*
* Bank Bus Machine PortSz Device
* ---- --- ------- ------ ------
* 0 60x GPCM 64 bit FLASH
* 1 60x SDRAM 64 bit SDRAM
*
*/
/* Initialize SDRAM on local bus
*/
#define CFG_INIT_LOCAL_SDRAM
/* Minimum mask to separate preliminary
* address ranges for CS[0:2]
*/
#define CFG_MIN_AM_MASK 0xC0000000
/*
* we use the same values for 32 MB and 128 MB SDRAM
* refresh rate = 7.68 uS (100 MHz Bus Clock)
*/
#define CFG_MPTPR 0x2000
#define CFG_PSRT 0x16
#define CFG_MRS_OFFS 0x00000000
#if defined(CONFIG_BOOT_ROM)
/*
* Bank 0 - Boot ROM (8 bit wide)
*/
#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
BRx_PS_8 |\
BRx_MS_GPCM_P |\
BRx_V)
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_5_CLK |\
ORxG_EHTR |\
ORxG_TRLX)
/*
* Bank 1 - Flash (64 bit wide)
*/
#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_MS_GPCM_P |\
BRx_V)
#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_5_CLK |\
ORxG_EHTR |\
ORxG_TRLX)
#else /* ! CONFIG_BOOT_ROM */
/*
* Bank 0 - Flash (64 bit wide)
*/
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_MS_GPCM_P |\
BRx_V)
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_5_CLK |\
ORxG_EHTR |\
ORxG_TRLX)
/*
* Bank 1 - Disk-On-Chip
*/
#define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
BRx_PS_8 |\
BRx_MS_GPCM_P |\
BRx_V)
#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_5_CLK |\
ORxG_EHTR |\
ORxG_TRLX)
#endif /* CONFIG_BOOT_ROM */
/* Bank 2 - SDRAM
*/
#ifndef CFG_RAMBOOT
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_MS_SDRAM_P |\
BRx_V)
/* SDRAM initialization values for 8-column chips
*/
#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
ORxS_BPD_4 |\
ORxS_ROWST_PBI0_A9 |\
ORxS_NUMR_12)
#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
PSDMR_BSMA_A14_A16 |\
PSDMR_SDA10_PBI0_A10 |\
PSDMR_RFRC_7_CLK |\
PSDMR_PRETOACT_2W |\
PSDMR_ACTTORW_2W |\
PSDMR_LDOTOPRE_1C |\
PSDMR_WRC_1C |\
PSDMR_CL_2)
/* SDRAM initialization values for 9-column chips
*/
#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
ORxS_BPD_4 |\
ORxS_ROWST_PBI0_A7 |\
ORxS_NUMR_13)
#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
PSDMR_BSMA_A13_A15 |\
PSDMR_SDA10_PBI0_A9 |\
PSDMR_RFRC_7_CLK |\
PSDMR_PRETOACT_2W |\
PSDMR_ACTTORW_2W |\
PSDMR_LDOTOPRE_1C |\
PSDMR_WRC_1C |\
PSDMR_CL_2)
#define CFG_OR2_PRELIM CFG_OR2_9COL
#define CFG_PSDMR CFG_PSDMR_9COL
#endif /* CFG_RAMBOOT */
#endif /* __CONFIG_H */

4
include/configs/trab.h
View File

@@ -250,7 +250,7 @@
"add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
"add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \
"u-boot=/tftpboot/TRAB/u-boot.bin-old\0" \
"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
"load=tftp C100000 ${u-boot}\0" \
"update=protect off 0 3FFFF;era 0 3FFFF;" \
"cp.b C100000 0 $filesize;" \
@@ -273,7 +273,7 @@
"add_net=setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \
"add_misc=setenv bootargs $(bootargs) console=ttyS0 panic=1\0" \
"u-boot=/tftpboot/TRAB/u-boot.bin-old\0" \
"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
"load=tftp C100000 $(u-boot)\0" \
"update=protect off 0 3FFFF;era 0 3FFFF;" \
"cp.b C100000 0 $(filesize);" \

355
include/configs/xm250.h Normal file
View File

@@ -0,0 +1,355 @@
/*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
#define CONFIG_INIT_CRITICAL /* undef for developing */
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/*
* Size of malloc() pool; this lives below the uppermost 128 KiB which are
* used for the RAM copy of the uboot code
*
*/
#define CFG_MALLOC_LEN (256*1024)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
*/
#define CONFIG_DRIVER_SMC91111
#define CONFIG_SMC91111_BASE 0x04000300
#undef CONFIG_SMC91111_EXT_PHY
#define CONFIG_SMC_USE_32_BIT
#undef CONFIG_SHOW_ACTIVITY
#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
/*
* I2C bus
*/
#define CONFIG_HARD_I2C 1
#define CFG_I2C_SPEED 50000
#define CFG_I2C_SLAVE 0xfe
#define CONFIG_RTC_PCF8563 1
#define CFG_I2C_RTC_ADDR 0x51
#define CFG_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* length of address */
#define CFG_EEPROM_SIZE 2048 /* size in bytes */
#undef CFG_I2C_INIT_BOARD /* board has no own init */
/*
* select serial console configuration
*/
#define CONFIG_FFUART 1 /* we use FFUART */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_DATE | \
CFG_CMD_I2C )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0xa3000000 /* default load address */
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
#define CFG_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Definitions related to passing arguments to kernel.
*/
#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
#undef CONFIG_INITRD_TAG /* do not send initrd params */
#undef CONFIG_VFD /* do not send framebuffer setup */
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 4
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
#define CFG_DRAM_BASE 0xa0000000
#define CFG_DRAM_SIZE 0x04000000
#define CFG_FLASH_BASE PHYS_FLASH_1
/*
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
#define CFG_FLASH_LOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Set Lock Bit */
#define CFG_FLASH_UNLOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Clear Lock Bits */
#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */
#define CFG_ENV_SIZE 0x4000
#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
/******************************************************************************
*
* CPU specific defines
*
******************************************************************************/
/*
* GPIO settings
*
* GPIO pin assignments
* GPIO Name Dir Out AF
* 0 NC
* 1 NC
* 2 SIRQ1 I
* 3 SIRQ2 I
* 4 SIRQ3 I
* 5 DMAACK1 O 0
* 6 DMAACK2 O 0
* 7 DMAACK3 O 0
* 8 TC1 O 0
* 9 TC2 O 0
* 10 TC3 O 0
* 11 nDMAEN O 1
* 12 AENCTRL O 0
* 13 PLDTC O 0
* 14 ETHIRQ I
* 15 NC
* 16 NC
* 17 NC
* 18 RDY I
* 19 DMASIO I
* 20 ETHIRQ NC
* 21 NC
* 22 PGMEN O 1 FIXME for debug only enable flash
* 23 NC
* 24 NC
* 25 NC
* 26 NC
* 27 NC
* 28 NC
* 29 NC
* 30 NC
* 31 NC
* 32 NC
* 33 NC
* 34 FFRXD I 01
* 35 FFCTS I 01
* 36 FFDCD I 01
* 37 FFDSR I 01
* 38 FFRI I 01
* 39 FFTXD O 1 10
* 40 FFDTR O 0 10
* 41 FFRTS O 0 10
* 42 RS232FOFF O 0 00
* 43 NC
* 44 NC
* 45 IRSL0 O 0
* 46 IRRX0 I 01
* 47 IRTX0 O 0 10
* 48 NC
* 49 nIOWE O 0
* 50 NC
* 51 NC
* 52 NC
* 53 NC
* 54 NC
* 55 NC
* 56 NC
* 57 NC
* 58 DKDIRQ I
* 59 NC
* 60 NC
* 61 NC
* 62 NC
* 63 NC
* 64 COMLED O 0
* 65 COMLED O 0
* 66 COMLED O 0
* 67 COMLED O 0
* 68 COMLED O 0
* 69 COMLED O 0
* 70 COMLED O 0
* 71 COMLED O 0
* 72 NC
* 73 NC
* 74 NC
* 75 NC
* 76 NC
* 77 NC
* 78 CSIO O 1
* 79 NC
* 80 CSETH O 1
*
* NOTE: All NC's are defined to be outputs
*
*/
/* Pin direction control */
#define CFG_GPDR0_VAL 0xd3808000
#define CFG_GPDR1_VAL 0xfcffab83
#define CFG_GPDR2_VAL 0x0001ffff
/* Set and Clear registers */
#define CFG_GPSR0_VAL 0x00008000
#define CFG_GPSR1_VAL 0x00ff0002
#define CFG_GPSR2_VAL 0x0001c000
#define CFG_GPCR0_VAL 0x00000000
#define CFG_GPCR1_VAL 0x00000000
#define CFG_GPCR2_VAL 0x00000000
/* Edge detect registers (these are set by the kernel) */
#define CFG_GRER0_VAL 0x00002180
#define CFG_GRER1_VAL 0x00000000
#define CFG_GRER2_VAL 0x00000000
#define CFG_GFER0_VAL 0x000043e0
#define CFG_GFER1_VAL 0x00000000
#define CFG_GFER2_VAL 0x00000000
/* Alternate function registers */
#define CFG_GAFR0_L_VAL 0x80000004
#define CFG_GAFR0_U_VAL 0x595a8010
#define CFG_GAFR1_L_VAL 0x699a9559
#define CFG_GAFR1_U_VAL 0xaaa5aaaa
#define CFG_GAFR2_L_VAL 0xaaaaaaaa
#define CFG_GAFR2_U_VAL 0x00000002
/*
* Clocks, power control and interrupts
*/
#define CFG_PSSR_VAL 0x00000030
#define CFG_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
#define CFG_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */
#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
/* FIXME
*
* RTC settings
* Watchdog
*
*/
/*
* Memory settings
*
*/
#define CFG_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */
#define CFG_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */
#define CFG_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */
#define CFG_MDCNFG_VAL 0x000009c9
#define CFG_MDMRS_VAL 0x00220022
#define CFG_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in memsetup.S */
/*
* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
*/
#define CFG_MECR_VAL 0x00000000
#define CFG_MCMEM0_VAL 0x00010504
#define CFG_MCMEM1_VAL 0x00010504
#define CFG_MCATT0_VAL 0x00010504
#define CFG_MCATT1_VAL 0x00010504
#define CFG_MCIO0_VAL 0x00004715
#define CFG_MCIO1_VAL 0x00004715
/* Board specific defines */
#ifndef __ASSEMBLY__
/* global prototypes */
void led_code(int code, int color);
#endif
#endif /* __CONFIG_H */

4
include/flash.h
View File

@@ -168,7 +168,9 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */
#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */
#define MX_ID_LV320T 0x22A722A7 /* 29LV320T by Macronix, AMD compatible */
#define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */
#define MX_ID_LV320B 0x22A822A8 /* 29LV320B by Macronix, AMD compatible */
#define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */
#define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */
@@ -348,6 +350,8 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */
#define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */
#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */
#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */
#define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */
/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
#define FLASH_28F256L18T 0x00B0
#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */