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ColdFire: I2C fix for multiple platforms

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Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChung Liew
2008-08-19 03:01:19 +06:00
committed by John Rigby
parent d53cf6a9c7
commit eec567a67e
12 changed files with 62 additions and 14 deletions
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9
include/asm-m68k/fsl_i2c.h
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@@ -72,15 +72,6 @@ typedef struct fsl_i2c {
#define I2C_DR 0xFF
#define I2C_DR_SHIFT 0
#define I2C_DR_RES ~(I2C_DR)
u8 dfsrr; /* I2C digital filter sampling rate register */
u8 res5[3];
#define I2C_DFSRR 0x3F
#define I2C_DFSRR_SHIFT 0
#define I2C_DFSRR_RES ~(I2C_DR)
/* Fill out the reserved block */
u8 res6[0xE8];
} fsl_i2c_t;
#endif /* _ASM_I2C_H_ */

7
include/configs/M5235EVB.h
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@@ -102,12 +102,15 @@
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000300
#define CFG_IMMR CFG_MBAR
#define CFG_I2C_PINMUX_REG (gpio->par_qspi)
#define CFG_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CFG_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */

11
include/configs/M5253DEMO.h
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@@ -118,6 +118,17 @@
#define CONFIG_HOSTNAME M5253DEMO
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000280
#define CFG_IMMR CFG_MBAR
#define CFG_I2C_PINMUX_REG (*(u32 *) (CFG_MBAR+0x19C))
#define CFG_I2C_PINMUX_CLR (0xFFFFE7FF)
#define CFG_I2C_PINMUX_SET (0)
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */

3
include/configs/M5275EVB.h
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@@ -118,6 +118,9 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000300
#define CFG_IMMR CFG_MBAR
#define CFG_I2C_PINMUX_REG (gpio_reg->par_feci2c)
#define CFG_I2C_PINMUX_CLR (0xFFF0)
#define CFG_I2C_PINMUX_SET (0x000F)
#ifdef CONFIG_MCFFEC
#define CONFIG_ETHADDR 00:06:3b:01:41:55