Merge branch 'master' of git://git.denx.de/u-boot-socfpga
This commit is contained in:
Tom Rini
@@ -324,9 +324,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
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#define CONFIG_SPL_RAM_DEVICE
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#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
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#define CONFIG_SPL_MAX_SIZE (64 * 1024)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MALLOC_SIMPLE
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#endif
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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@@ -349,9 +346,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#else
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */
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#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* offset 512 sect (256k) */
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#endif
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#endif
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@@ -22,7 +22,7 @@
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/* Booting Linux */
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
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#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
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#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
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#define CONFIG_LOADADDR 0x01000000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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231
include/configs/socfpga_vining_fpga.h
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231
include/configs/socfpga_vining_fpga.h
Normal file
@@ -0,0 +1,231 @@
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/*
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* Copyright (C) 2015 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__
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#define __CONFIG_SAMTEC_VINING_FPGA_H__
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#include <asm/arch/base_addr_ac5.h>
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/* U-Boot Commands */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_DOS_PARTITION
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#define CONFIG_FAT_WRITE
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_LED
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/* Memory configurations */
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#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */
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/* Booting Linux */
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_BOOTFILE "openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb"
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#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
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#define CONFIG_BOOTCOMMAND "run selboot"
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#define CONFIG_LOADADDR 0x01000000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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/* I2C EEPROM */
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#ifdef CONFIG_CMD_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_I2C_EEPROM_BUS 0
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
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#endif
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/*
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* Status LEDs:
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* 0 ... Top Green
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* 1 ... Top Red
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* 2 ... Bottom Green
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* 3 ... Bottom Red
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*/
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#define CONFIG_STATUS_LED
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#define CONFIG_GPIO_LED
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#define CONFIG_BOARD_SPECIFIC_LED
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#define STATUS_LED_BIT 48
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#define STATUS_LED_STATE STATUS_LED_OFF
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#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
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#define STATUS_LED_BIT1 53
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#define STATUS_LED_STATE1 STATUS_LED_OFF
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#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
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#define STATUS_LED_BIT2 54
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#define STATUS_LED_STATE2 STATUS_LED_OFF
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#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
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#define STATUS_LED_BIT3 65
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#define STATUS_LED_STATE3 STATUS_LED_OFF
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#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
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/* Ethernet on SoC (EMAC) */
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_BOOTP_SEND_HOSTNAME
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/* PHY */
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#define CONFIG_PHY_MICREL
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#define CONFIG_PHY_MICREL_KSZ9021
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#endif
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/* Extra Environment */
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#define CONFIG_HOSTNAME socfpga_vining_fpga
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/*
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* Active LOW GPIO buttons:
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* A: GPIO 77 ... the button between USB B and ethernet
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* B: GPIO 78 ... the button between USB A ports
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*
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* The logic:
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* if button B is not pressed, boot normal Linux system immediatelly
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* if button B is pressed, wait $bootdelay and boot recovery system
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*/
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#define CONFIG_PREBOOT \
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"setenv hostname vining-${unit_serial} ; " \
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"setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; " \
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"if gpio input 78 ; then " \
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"setenv bootdelay 10 ; " \
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"setenv boottype rcvr ; " \
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"else " \
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"setenv bootdelay 5 ; " \
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"setenv boottype norm ; " \
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"fi"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"verify=n\0" \
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"consdev=ttyS0\0" \
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"baudrate=115200\0" \
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"bootscript=boot.scr\0" \
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"ubimtdnr=5\0" \
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"ubimtd=rootfs\0" \
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"ubipart=ubi0:rootfs\0" \
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"ubisfcs=1\0" /* Default is flash at CS#1 */ \
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"netdev=eth0\0" \
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"hostname=vining_fpga\0" \
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"kernel_addr_r=0x10000000\0" \
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"mtdparts_0=ff705000.spi.0:" \
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"1m(u-boot)," \
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"64k(env1)," \
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"64k(env2)," \
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"256k(samtec1)," \
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"256k(samtec2)," \
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"-(rcvrfs)\0" /* Recovery */ \
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"mtdparts_1=ff705000.spi.1:" \
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"32m(rootfs)," \
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"-(userfs)\0" \
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"update_filename=u-boot-with-spl-dtb.sfp\0" \
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"update_qspi_offset=0x0\0" \
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"update_qspi=" /* Update the QSPI firmware */ \
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"if sf probe ; then " \
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"if tftp ${update_filename} ; then " \
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"sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \
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"fi ; " \
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"fi\0" \
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"fpga_filename=output_file.rbf\0" \
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"load_fpga=" /* Load FPGA bitstream */ \
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"if tftp ${fpga_filename} ; then " \
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"fpga load 0 $loadaddr $filesize ; " \
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"bridge enable ; " \
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"fi\0" \
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"addcons=" \
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"setenv bootargs ${bootargs} " \
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"console=${consdev},${baudrate}\0" \
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"addip=" \
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"setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:" \
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"${netmask}:${hostname}:${netdev}:off\0" \
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"addmisc=" \
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"setenv bootargs ${bootargs} ${miscargs}\0" \
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"addmtd=" \
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"setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; " \
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"setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \
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"addargs=run addcons addmtd addmisc\0" \
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"ubiload=" \
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"ubi part ${ubimtd} ; ubifsmount ${ubipart} ; " \
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"ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
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"netload=" \
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"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
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"miscargs=nohlt panic=1\0" \
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"ubiargs=" \
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"setenv bootargs ubi.mtd=${ubimtdnr} " \
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"root=${ubipart} rootfstype=ubifs\0" \
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"nfsargs=" \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath},v3,tcp\0" \
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"ubi_sfsel=" \
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"if test \"${boottype}\" = \"rcvr\" ; then " \
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"setenv ubisfcs 0 ; " \
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"setenv ubimtd rcvrfs ; " \
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"setenv ubimtdnr 5 ; " \
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"setenv mtdparts mtdparts=${mtdparts_0} ; " \
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"setenv mtdids nor0=ff705000.spi.0 ; " \
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"setenv ubipart ubi0:rootfs ; " \
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"else " \
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"setenv ubisfcs 1 ; " \
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"setenv ubimtd rootfs ; " \
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"setenv ubimtdnr 6 ; " \
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"setenv mtdparts mtdparts=${mtdparts_1} ; " \
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"setenv mtdids nor0=ff705000.spi.1 ; " \
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"setenv ubipart ubi0:rootfs ; " \
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"fi ; " \
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"sf probe 0:${ubisfcs}\0" \
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"ubi_ubi=" \
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"run ubi_sfsel ubiload ubiargs addargs ; " \
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"bootm ${kernel_addr_r}\0" \
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"ubi_nfs=" \
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"run ubiload nfsargs addip addargs ; " \
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"bootm ${kernel_addr_r}\0" \
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"net_ubi=" \
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"run netload ubiargs addargs ; " \
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"bootm ${kernel_addr_r}\0" \
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"net_nfs=" \
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"run netload nfsargs addip addargs ; " \
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"bootm ${kernel_addr_r}\0" \
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"selboot=" /* Select from where to boot. */ \
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"if test \"${bootmode}\" = \"qspi\" ; then " \
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"led all off ; " \
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"if test \"${boottype}\" = \"rcvr\" ; then " \
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"echo \"Booting recovery system\" ; " \
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"led 3 on ; " /* Bottom RED */ \
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"fi ; " \
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"led 1 on ; " /* Top RED */ \
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"run ubi_ubi ; " \
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"else echo \"Unsupported boot mode: \"${bootmode} ; " \
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"fi\0" \
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_MTD_UBI_FASTMAP
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#define CONFIG_RBTREE
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#define CONFIG_LZO
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#define MTDPARTS_DEFAULT \
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"mtdparts=ff705000.spi.0:" \
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"1m(u-boot)," \
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"64k(env1)," \
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"64k(env2)," \
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"256k(samtec1)," \
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"256k(samtec2)," \
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"-(rcvrfs);" /* Recovery */ \
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_ENV_OFFSET 0x100000
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#define CONFIG_ENV_OFFSET_REDUND \
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(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_MISC_INIT_R
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#define CONFIG_BOARD_LATE_INIT
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/* Enable DFU to SF and RAM */
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#define CONFIG_DFU_RAM
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#define CONFIG_DFU_SF
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/* Support changing the prompt string */
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#define CONFIG_CMDLINE_PS_SUPPORT
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/* The rest of the configuration is shared */
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#include <configs/socfpga_common.h>
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#endif /* __CONFIG_SAMTEC_VINING_FPGA_H__ */
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