Merge branch 'u-boot/master' into 'u-boot-arm/master'
This commit is contained in:
Albert ARIBAUD
@@ -65,7 +65,7 @@ typedef struct global_data {
|
||||
struct global_data *new_gd; /* relocated global data */
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#ifdef CONFIG_DM
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struct device *dm_root; /* Root instance for Driver Model */
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struct udevice *dm_root;/* Root instance for Driver Model */
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struct list_head uclass_root; /* Head of core tree */
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#endif
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@@ -86,7 +86,7 @@ enum {
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GPIOF_UNKNOWN,
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};
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struct device;
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struct udevice;
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/**
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* struct struct dm_gpio_ops - Driver model GPIO operations
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@@ -116,15 +116,15 @@ struct device;
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* all devices. Be careful not to confuse offset with gpio in the parameters.
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*/
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struct dm_gpio_ops {
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int (*request)(struct device *dev, unsigned offset, const char *label);
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int (*free)(struct device *dev, unsigned offset);
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int (*direction_input)(struct device *dev, unsigned offset);
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int (*direction_output)(struct device *dev, unsigned offset,
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int (*request)(struct udevice *dev, unsigned offset, const char *label);
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int (*free)(struct udevice *dev, unsigned offset);
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int (*direction_input)(struct udevice *dev, unsigned offset);
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int (*direction_output)(struct udevice *dev, unsigned offset,
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int value);
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int (*get_value)(struct device *dev, unsigned offset);
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int (*set_value)(struct device *dev, unsigned offset, int value);
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int (*get_function)(struct device *dev, unsigned offset);
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int (*get_state)(struct device *dev, unsigned offset, char *state,
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int (*get_value)(struct udevice *dev, unsigned offset);
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int (*set_value)(struct udevice *dev, unsigned offset, int value);
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int (*get_function)(struct udevice *dev, unsigned offset);
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int (*get_state)(struct udevice *dev, unsigned offset, char *state,
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int maxlen);
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};
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@@ -166,7 +166,7 @@ struct gpio_dev_priv {
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* @offset_count: Returns number of GPIOs within this bank
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* @return bank name of this device
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*/
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const char *gpio_get_bank_info(struct device *dev, int *offset_count);
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const char *gpio_get_bank_info(struct udevice *dev, int *offset_count);
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/**
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* gpio_lookup_name - Look up a GPIO name and return its details
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@@ -179,7 +179,7 @@ const char *gpio_get_bank_info(struct device *dev, int *offset_count);
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* @offsetp: Returns the offset number within this device
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* @gpiop: Returns the absolute GPIO number, numbered from 0
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*/
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int gpio_lookup_name(const char *name, struct device **devp,
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int gpio_lookup_name(const char *name, struct udevice **devp,
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unsigned int *offsetp, unsigned int *gpiop);
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#endif /* _ASM_GENERIC_GPIO_H_ */
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47
include/autoboot.h
Normal file
47
include/autoboot.h
Normal file
@@ -0,0 +1,47 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Add to readline cmdline-editing by
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* (C) Copyright 2005
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* JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __AUTOBOOT_H
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#define __AUTOBOOT_H
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#ifdef CONFIG_BOOTDELAY
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/**
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* bootdelay_process() - process the bootd delay
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*
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* Process the boot delay, boot limit, then get the value of either
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* bootcmd, failbootcmd or altbootcmd depending on the current state.
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* Return this command so it can be executed.
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*
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* @return command to executed
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*/
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const char *bootdelay_process(void);
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|
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/**
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* autoboot_command() - run the autoboot command
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*
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* If enabled, run the autoboot command returned from bootdelay_process().
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* Also do the CONFIG_MENUKEY processing if enabled.
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*
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||||
* @cmd: Command to run
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||||
*/
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||||
void autoboot_command(const char *cmd);
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#else
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static inline const char *bootdelay_process(void)
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{
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return NULL;
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||||
}
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|
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static inline void autoboot_command(const char *s)
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||||
{
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||||
}
|
||||
#endif
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||||
|
||||
#endif
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57
include/bootm.h
Normal file
57
include/bootm.h
Normal file
@@ -0,0 +1,57 @@
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||||
/*
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||||
* (C) Copyright 2000-2009
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||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
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||||
* SPDX-License-Identifier: GPL-2.0+
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*/
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||||
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||||
#ifndef _BOOTM_H
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#define _BOOTM_H
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||||
|
||||
#include <command.h>
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#include <image.h>
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||||
#define BOOTM_ERR_RESET (-1)
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#define BOOTM_ERR_OVERLAP (-2)
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||||
#define BOOTM_ERR_UNIMPLEMENTED (-3)
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/*
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* Continue booting an OS image; caller already has:
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* - copied image header to global variable `header'
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* - checked header magic number, checksums (both header & image),
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* - verified image architecture (PPC) and type (KERNEL or MULTI),
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* - loaded (first part of) image to header load address,
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* - disabled interrupts.
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*
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* @flag: Flags indicating what to do (BOOTM_STATE_...)
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* @argc: Number of arguments. Note that the arguments are shifted down
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* so that 0 is the first argument not processed by U-Boot, and
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||||
* argc is adjusted accordingly. This avoids confusion as to how
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* many arguments are available for the OS.
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* @images: Pointers to os/initrd/fdt
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* @return 1 on error. On success the OS boots so this function does
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* not return.
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*/
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typedef int boot_os_fn(int flag, int argc, char * const argv[],
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bootm_headers_t *images);
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extern boot_os_fn do_bootm_linux;
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int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
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void lynxkdi_boot(image_header_t *hdr);
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boot_os_fn *bootm_os_get_boot_func(int os);
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||||
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int bootm_host_load_images(const void *fit, int cfg_noffset);
|
||||
|
||||
int boot_selected_os(int argc, char * const argv[], int state,
|
||||
bootm_headers_t *images, boot_os_fn *boot_fn);
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||||
|
||||
ulong bootm_disable_interrupts(void);
|
||||
|
||||
/* This is a special function used by bootz */
|
||||
int bootm_find_ramdisk_fdt(int flag, int argc, char * const argv[]);
|
||||
|
||||
int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
|
||||
int states, bootm_headers_t *images, int boot_progress);
|
||||
|
||||
#endif
|
||||
59
include/bootretry.h
Normal file
59
include/bootretry.h
Normal file
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* (C) Copyright 2000
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||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
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||||
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||||
#ifndef __BOOTRETRY_H
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||||
#define __BOOTRETRY_H
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||||
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||||
#ifdef CONFIG_BOOT_RETRY_TIME
|
||||
/**
|
||||
* bootretry_tstc_timeout() - ensure we get a keypress before timeout
|
||||
*
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||||
* Check for a keypress repeatedly, resetting the watchdog each time. If a
|
||||
* keypress is not received within the command timeout, return an error.
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||||
*
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||||
* @return 0 if a key is received in time, -ETIMEDOUT if not
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||||
*/
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||||
int bootretry_tstc_timeout(void);
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||||
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||||
/**
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||||
* bootretry_init_cmd_timeout() - set up command timeout
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||||
*
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||||
* Get the required command timeout from the environment.
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||||
*/
|
||||
void bootretry_init_cmd_timeout(void);
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||||
|
||||
/**
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||||
* bootretry_reset_cmd_timeout() - reset command timeout
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||||
*
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||||
* Reset the command timeout so that the user has a fresh start. This is
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||||
* typically used when input is received from the user.
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||||
*/
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||||
void bootretry_reset_cmd_timeout(void);
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||||
/** bootretry_dont_retry() - Indicate that we should not retry the boot */
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||||
void bootretry_dont_retry(void);
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||||
#else
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||||
static inline int bootretry_tstc_timeout(void)
|
||||
{
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||||
return 0;
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||||
}
|
||||
|
||||
static inline void bootretry_init_cmd_timeout(void)
|
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{
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||||
}
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||||
|
||||
static inline void bootretry_reset_cmd_timeout(void)
|
||||
{
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||||
}
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||||
static inline void bootretry_dont_retry(void)
|
||||
{
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||||
}
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||||
|
||||
#endif
|
||||
|
||||
#endif
|
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149
include/cli.h
Normal file
149
include/cli.h
Normal file
@@ -0,0 +1,149 @@
|
||||
/*
|
||||
* (C) Copyright 2014 Google, Inc
|
||||
* Simon Glass <sjg@chromium.org>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CLI_H
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||||
#define __CLI_H
|
||||
|
||||
/**
|
||||
* Go into the command loop
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||||
*
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||||
* This will return if we get a timeout waiting for a command. See
|
||||
* CONFIG_BOOT_RETRY_TIME.
|
||||
*/
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||||
void cli_simple_loop(void);
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||||
|
||||
/**
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||||
* cli_simple_run_command() - Execute a command with the simple CLI
|
||||
*
|
||||
* @cmd: String containing the command to execute
|
||||
* @flag Flag value - see CMD_FLAG_...
|
||||
* @return 1 - command executed, repeatable
|
||||
* 0 - command executed but not repeatable, interrupted commands are
|
||||
* always considered not repeatable
|
||||
* -1 - not executed (unrecognized, bootd recursion or too many args)
|
||||
* (If cmd is NULL or "" or longer than CONFIG_SYS_CBSIZE-1 it is
|
||||
* considered unrecognized)
|
||||
*/
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||||
int cli_simple_run_command(const char *cmd, int flag);
|
||||
|
||||
/**
|
||||
* cli_simple_run_command_list() - Execute a list of command
|
||||
*
|
||||
* The commands should be separated by ; or \n and will be executed
|
||||
* by the built-in parser.
|
||||
*
|
||||
* This function cannot take a const char * for the command, since if it
|
||||
* finds newlines in the string, it replaces them with \0.
|
||||
*
|
||||
* @param cmd String containing list of commands
|
||||
* @param flag Execution flags (CMD_FLAG_...)
|
||||
* @return 0 on success, or != 0 on error.
|
||||
*/
|
||||
int cli_simple_run_command_list(char *cmd, int flag);
|
||||
|
||||
/**
|
||||
* cli_readline() - read a line into the console_buffer
|
||||
*
|
||||
* This is a convenience function which calls cli_readline_into_buffer().
|
||||
*
|
||||
* @prompt: Prompt to display
|
||||
* @return command line length excluding terminator, or -ve on error
|
||||
*/
|
||||
int cli_readline(const char *const prompt);
|
||||
|
||||
/**
|
||||
* readline_into_buffer() - read a line into a buffer
|
||||
*
|
||||
* Display the prompt, then read a command line into @buffer. The
|
||||
* maximum line length is CONFIG_SYS_CBSIZE including a \0 terminator, which
|
||||
* will always be added.
|
||||
*
|
||||
* The command is echoed as it is typed. Command editing is supported if
|
||||
* CONFIG_CMDLINE_EDITING is defined. Tab auto-complete is supported if
|
||||
* CONFIG_AUTO_COMPLETE is defined. If CONFIG_BOOT_RETRY_TIME is defined,
|
||||
* then a timeout will be applied.
|
||||
*
|
||||
* If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0,
|
||||
* time out when time goes past endtime (timebase time in ticks).
|
||||
*
|
||||
* @prompt: Prompt to display
|
||||
* @buffer: Place to put the line that is entered
|
||||
* @timeout: Timeout in milliseconds, 0 if none
|
||||
* @return command line length excluding terminator, or -ve on error: of the
|
||||
* timeout is exceeded (either CONFIG_BOOT_RETRY_TIME or the timeout
|
||||
* parameter), then -2 is returned. If a break is detected (Ctrl-C) then
|
||||
* -1 is returned.
|
||||
*/
|
||||
int cli_readline_into_buffer(const char *const prompt, char *buffer,
|
||||
int timeout);
|
||||
|
||||
/**
|
||||
* parse_line() - split a command line down into separate arguments
|
||||
*
|
||||
* The argv[] array is filled with pointers into @line, and each argument
|
||||
* is terminated by \0 (i.e. @line is changed in the process unless there
|
||||
* is only one argument).
|
||||
*
|
||||
* #argv is terminated by a NULL after the last argument pointer.
|
||||
*
|
||||
* At most CONFIG_SYS_MAXARGS arguments are permited - if there are more
|
||||
* than that then an error is printed, and this function returns
|
||||
* CONFIG_SYS_MAXARGS, with argv[] set up to that point.
|
||||
*
|
||||
* @line: Command line to parse
|
||||
* @args: Array to hold arguments
|
||||
* @return number of arguments
|
||||
*/
|
||||
int cli_simple_parse_line(char *line, char *argv[]);
|
||||
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
/**
|
||||
* cli_process_fdt() - process the boot command from the FDT
|
||||
*
|
||||
* If bootcmmd is defined in the /config node of the FDT, we use that
|
||||
* as the boot command. Further, if bootsecure is set to 1 (in the same
|
||||
* node) then we return true, indicating that the command should be executed
|
||||
* as securely as possible, avoiding the CLI parser.
|
||||
*
|
||||
* @cmdp: On entry, the command that will be executed if the FDT does
|
||||
* not have a command. Returns the command to execute after
|
||||
* checking the FDT.
|
||||
* @return true to execute securely, else false
|
||||
*/
|
||||
bool cli_process_fdt(const char **cmdp);
|
||||
|
||||
/** cli_secure_boot_cmd() - execute a command as securely as possible
|
||||
*
|
||||
* This avoids using the parser, thus executing the command with the
|
||||
* smallest amount of code. Parameters are not supported.
|
||||
*/
|
||||
void cli_secure_boot_cmd(const char *cmd);
|
||||
#else
|
||||
static inline bool cli_process_fdt(const char **cmdp)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline void cli_secure_boot_cmd(const char *cmd)
|
||||
{
|
||||
}
|
||||
#endif /* CONFIG_OF_CONTROL */
|
||||
|
||||
/**
|
||||
* Go into the command loop
|
||||
*
|
||||
* This will return if we get a timeout waiting for a command, but only for
|
||||
* the simple parser (not hush). See CONFIG_BOOT_RETRY_TIME.
|
||||
*/
|
||||
void cli_loop(void);
|
||||
|
||||
/** Set up the command line interpreter ready for action */
|
||||
void cli_init(void);
|
||||
|
||||
#define endtick(seconds) (get_ticks() + (uint64_t)(seconds) * get_tbclk())
|
||||
|
||||
#endif
|
||||
@@ -5,8 +5,8 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _HUSH_H_
|
||||
#define _HUSH_H_
|
||||
#ifndef _CLI_HUSH_H_
|
||||
#define _CLI_HUSH_H_
|
||||
|
||||
#define FLAG_EXIT_FROM_LOOP 1
|
||||
#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */
|
||||
@@ -11,7 +11,6 @@
|
||||
#ifndef __COMMAND_H
|
||||
#define __COMMAND_H
|
||||
|
||||
#include <config.h>
|
||||
#include <linker_lists.h>
|
||||
|
||||
#ifndef NULL
|
||||
|
||||
@@ -54,8 +54,6 @@ typedef volatile unsigned char vu_char;
|
||||
#include <asm/immap_512x.h>
|
||||
#elif defined(CONFIG_MPC8260)
|
||||
#if defined(CONFIG_MPC8247) \
|
||||
|| defined(CONFIG_MPC8248) \
|
||||
|| defined(CONFIG_MPC8271) \
|
||||
|| defined(CONFIG_MPC8272)
|
||||
#define CONFIG_MPC8272_FAMILY 1
|
||||
#endif
|
||||
@@ -273,6 +271,7 @@ int print_buffer(ulong addr, const void *data, uint width, uint count,
|
||||
/* common/main.c */
|
||||
void main_loop (void);
|
||||
int run_command(const char *cmd, int flag);
|
||||
int run_command_repeatable(const char *cmd, int flag);
|
||||
|
||||
/**
|
||||
* Run a list of commands separated by ; or even \0
|
||||
@@ -286,12 +285,6 @@ int run_command(const char *cmd, int flag);
|
||||
* @return 0 on success, or != 0 on error.
|
||||
*/
|
||||
int run_command_list(const char *cmd, int len, int flag);
|
||||
int readline (const char *const prompt);
|
||||
int readline_into_buffer(const char *const prompt, char *buffer,
|
||||
int timeout);
|
||||
int parse_line (char *, char *[]);
|
||||
void init_cmd_timeout(void);
|
||||
void reset_cmd_timeout(void);
|
||||
extern char console_buffer[];
|
||||
|
||||
/* arch/$(ARCH)/lib/board.c */
|
||||
@@ -305,6 +298,7 @@ extern ulong monitor_flash_len;
|
||||
int mac_read_from_eeprom(void);
|
||||
extern u8 __dtb_dt_begin[]; /* embedded device tree blob */
|
||||
int set_cpu_clk_info(void);
|
||||
int mdm_init(void);
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO)
|
||||
int print_cpuinfo(void);
|
||||
#else
|
||||
|
||||
@@ -83,4 +83,12 @@
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_FIT_SIGNATURE
|
||||
#define CONFIG_IMAGE_FORMAT_LEGACY
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DISABLE_IMAGE_LEGACY
|
||||
#undef CONFIG_IMAGE_FORMAT_LEGACY
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_FALLBACKS_H */
|
||||
|
||||
@@ -1,193 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2005 Arabella Software Ltd.
|
||||
* Yuli Barcohen <yuli@arabellasw.com>
|
||||
*
|
||||
* Support for Analogue&Micro Adder boards family.
|
||||
* Tested on AdderII and Adder87x.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
|
||||
#define CONFIG_MPC875
|
||||
#endif
|
||||
|
||||
#define CONFIG_ADDER /* Analogue&Micro Adder board */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFE000000
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
|
||||
#define CONFIG_ETHER_ON_FEC1
|
||||
#define CONFIG_ETHER_ON_FEC2
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
|
||||
#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
|
||||
#define CONFIG_SYS_DISCOVER_PHY
|
||||
#define CONFIG_MII_INIT 1
|
||||
#define FEC_ENET
|
||||
#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
|
||||
|
||||
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
|
||||
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
|
||||
#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
|
||||
#ifdef CONFIG_MPC852T
|
||||
#define CONFIG_SYS_8xx_CPUCLK_MAX 50000000
|
||||
#else
|
||||
#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
|
||||
#endif /* CONFIG_MPC852T */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_IMMAP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
|
||||
|
||||
#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
|
||||
#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_LONGHELP /* #undef to save memory */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x400000 /* Default load address */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */
|
||||
|
||||
#define CONFIG_SYS_MAMR 0x00002114
|
||||
|
||||
/*
|
||||
* 4096 Up to 4096 SDRAM rows
|
||||
* 1000 factor s -> ms
|
||||
* 32 PTP (pre-divider from MPTPR)
|
||||
* 4 Number of refresh cycles per period
|
||||
* 64 Refresh cycle in ms per number of rows
|
||||
*/
|
||||
#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0x09900000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
|
||||
#ifdef CONFIG_BZIP2
|
||||
#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
|
||||
#else
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
|
||||
#endif /* CONFIG_BZIP2 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Flash organisation
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000
|
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
|
||||
|
||||
/* Environment is in flash */
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xFF000774
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
|
||||
|
||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Map Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xFF000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Configuration registers
|
||||
*/
|
||||
#ifdef CONFIG_WATCHDOG
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
|
||||
SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
|
||||
SYPCR_SWP)
|
||||
#else
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
|
||||
SYPCR_SWF | SYPCR_SWP)
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
|
||||
|
||||
/* TBSCR - Time Base Status and Control Register */
|
||||
#define CONFIG_SYS_TBSCR (TBSCR_TBF | TBSCR_TBE)
|
||||
|
||||
/* PISCR - Periodic Interrupt Status and Control */
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/* PLPRCR - PLL, Low-Power, and Reset Control Register */
|
||||
/* #define CONFIG_SYS_PLPRCR PLPRCR_TEXPS */
|
||||
|
||||
/* SCCR - System Clock and reset Control Register */
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#define CONFIG_SYS_SCCR SCCR_RTSEL
|
||||
|
||||
#define CONFIG_SYS_DER 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -1,371 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2004
|
||||
* Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
|
||||
*
|
||||
* (C) Copyright 2001, 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC8245 1
|
||||
#define CONFIG_HIDDEN_DRAGON 1
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
|
||||
|
||||
#if 0
|
||||
#define USE_DINK32 1
|
||||
#else
|
||||
#undef USE_DINK32
|
||||
#endif
|
||||
|
||||
#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#define CONFIG_DRAM_SPEED 100 /* MHz */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#undef CONFIG_PCI_PNP
|
||||
|
||||
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
|
||||
|
||||
#define PCI_ENET0_IOADDR 0x80000000
|
||||
#define PCI_ENET0_MEMADDR 0x80000000
|
||||
#define PCI_ENET1_IOADDR 0x81000000
|
||||
#define PCI_ENET1_MEMADDR 0x81000000
|
||||
|
||||
#define CONFIG_RTL8139
|
||||
|
||||
/* Make sure the ethaddr can be overwritten
|
||||
TODO: Remove this on final product
|
||||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_MAX_RAM_SIZE 0x02000000
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
|
||||
|
||||
#if defined (USE_DINK32)
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x00030000
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00090000
|
||||
#define CONFIG_SYS_RAMBOOT 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x00030000
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFFE00000
|
||||
#define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_EUMB_ADDR 0xFC000000
|
||||
|
||||
#define CONFIG_SYS_ISA_MEM 0xFD000000
|
||||
#define CONFIG_SYS_ISA_IO 0xFE000000
|
||||
|
||||
#define CONFIG_SYS_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */
|
||||
#define CONFIG_SYS_FLASH_RANGE_SIZE 0x00200000
|
||||
#define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */
|
||||
|
||||
/*
|
||||
* select i2c support configuration
|
||||
*
|
||||
* Supported configurations are {none, software, hardware} drivers.
|
||||
* If the software driver is chosen, there are some additional
|
||||
* configuration items that the driver uses to drive the port pins.
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
|
||||
#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_SOFT
|
||||
#error "Soft I2C is not configured properly. Please review!"
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
|
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
|
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
|
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
|
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
|
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
|
||||
else iop->pdat &= ~0x00010000
|
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
|
||||
else iop->pdat &= ~0x00020000
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
#endif /* CONFIG_SYS_I2C_SOFT */
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
|
||||
|
||||
/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */
|
||||
#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
|
||||
#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
|
||||
#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
|
||||
|
||||
/* TODO: Change this to VIA686A */
|
||||
|
||||
/*
|
||||
* NS87308 Configuration
|
||||
*/
|
||||
#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
|
||||
|
||||
#define CONFIG_SYS_NS87308_BADDR_10 1
|
||||
|
||||
#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \
|
||||
CONFIG_SYS_NS87308_UART2 | \
|
||||
CONFIG_SYS_NS87308_POWRMAN | \
|
||||
CONFIG_SYS_NS87308_RTC_APC )
|
||||
|
||||
#undef CONFIG_SYS_NS87308_PS2MOD
|
||||
|
||||
#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
|
||||
#define CONFIG_SYS_NS87308_CS0_CONF 0x30
|
||||
#define CONFIG_SYS_NS87308_CS1_BASE 0x0075
|
||||
#define CONFIG_SYS_NS87308_CS1_CONF 0x30
|
||||
#define CONFIG_SYS_NS87308_CS2_BASE 0x0074
|
||||
#define CONFIG_SYS_NS87308_CS2_CONF 0x30
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
|
||||
#if (CONFIG_CONS_INDEX > 2)
|
||||
#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000
|
||||
#else
|
||||
#define CONFIG_SYS_NS16550_CLK 1843200
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||
|
||||
#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
|
||||
#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
|
||||
|
||||
#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
|
||||
|
||||
/* the following are for SDRAM only*/
|
||||
#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
|
||||
#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
|
||||
#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
|
||||
#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
|
||||
#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
|
||||
#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
|
||||
#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
|
||||
#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
|
||||
#if 0
|
||||
#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
|
||||
#define CONFIG_SYS_EXTROM 1
|
||||
#define CONFIG_SYS_REGDIMM 0
|
||||
|
||||
|
||||
/* memory bank settings*/
|
||||
/*
|
||||
* only bits 20-29 are actually used from these vales to set the
|
||||
* start/end address the upper two bits will be 0, and the lower 20
|
||||
* bits will be set to 0x00000 for a start address, or 0xfffff for an
|
||||
* end address
|
||||
*/
|
||||
#define CONFIG_SYS_BANK0_START 0x00000000
|
||||
#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
|
||||
#define CONFIG_SYS_BANK0_ENABLE 1
|
||||
#define CONFIG_SYS_BANK1_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK1_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK1_ENABLE 0
|
||||
#define CONFIG_SYS_BANK2_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK2_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK2_ENABLE 0
|
||||
#define CONFIG_SYS_BANK3_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK3_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK3_ENABLE 0
|
||||
#define CONFIG_SYS_BANK4_START 0x00000000
|
||||
#define CONFIG_SYS_BANK4_END 0x00000000
|
||||
#define CONFIG_SYS_BANK4_ENABLE 0
|
||||
#define CONFIG_SYS_BANK5_START 0x00000000
|
||||
#define CONFIG_SYS_BANK5_END 0x00000000
|
||||
#define CONFIG_SYS_BANK5_ENABLE 0
|
||||
#define CONFIG_SYS_BANK6_START 0x00000000
|
||||
#define CONFIG_SYS_BANK6_END 0x00000000
|
||||
#define CONFIG_SYS_BANK6_ENABLE 0
|
||||
#define CONFIG_SYS_BANK7_START 0x00000000
|
||||
#define CONFIG_SYS_BANK7_END 0x00000000
|
||||
#define CONFIG_SYS_BANK7_ENABLE 0
|
||||
/*
|
||||
* Memory bank enable bitmask, specifying which of the banks defined above
|
||||
are actually present. MSB is for bank #7, LSB is for bank #0.
|
||||
*/
|
||||
#define CONFIG_SYS_BANK_ENABLE 0x01
|
||||
|
||||
#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
|
||||
/* see 8240 book for bit definitions */
|
||||
#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
|
||||
/* currently accessed page in memory */
|
||||
/* see 8240 book for details */
|
||||
|
||||
/* SDRAM 0 - 256MB */
|
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
/* stack in DCACHE @ 1GB (no backing mem) */
|
||||
#if defined(USE_DINK32)
|
||||
#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
|
||||
#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
#endif
|
||||
|
||||
/* PCI memory */
|
||||
#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
/* Flash, config addrs, etc */
|
||||
#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 36 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/* values according to the manual */
|
||||
#define CONFIG_DRAM_50MHZ 1
|
||||
#define CONFIG_SDRAM_50MHZ
|
||||
|
||||
#undef NR_8259_INTS
|
||||
#define NR_8259_INTS 1
|
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -1,330 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004 Arabella Software Ltd.
|
||||
* Yuli Barcohen <yuli@arabellasw.com>
|
||||
*
|
||||
* Support for Interphase iSPAN Communications Controllers
|
||||
* (453x and others). Tested on 4532.
|
||||
*
|
||||
* Derived from iSPAN 4539 port (iphase4539) by
|
||||
* Wolfgang Grandegger <wg@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
|
||||
#define CONFIG_CPM2 1 /* Has a CPM2 */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFE7A0000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Select serial console configuration
|
||||
*
|
||||
* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
||||
* for SCC).
|
||||
*
|
||||
* If CONFIG_CONS_NONE is defined, then the serial console routines must be
|
||||
* defined elsewhere (for example, on the cogent platform, there are serial
|
||||
* ports on the motherboard which are used for the serial console - see
|
||||
* cogent/cma101/serial.[ch]).
|
||||
*/
|
||||
#define CONFIG_CONS_ON_SMC /* Define if console on SMC */
|
||||
#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* Define if console on something else */
|
||||
#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Select Ethernet configuration
|
||||
*
|
||||
* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
|
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
|
||||
* for FCC).
|
||||
*
|
||||
* If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
|
||||
* be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
|
||||
*/
|
||||
#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */
|
||||
#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */
|
||||
|
||||
#ifdef CONFIG_ETHER_ON_FCC
|
||||
|
||||
#if CONFIG_ETHER_INDEX == 3
|
||||
|
||||
#define CONFIG_SYS_PHY_ADDR 0
|
||||
#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
|
||||
#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
|
||||
|
||||
#endif /* CONFIG_ETHER_INDEX == 3 */
|
||||
|
||||
#define CONFIG_SYS_CPMFCR_RAMTYPE 0
|
||||
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */
|
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications
|
||||
*/
|
||||
#define MDIO_PORT 3 /* Port D */
|
||||
#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
|
||||
(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
|
||||
#define MDC_DECLARE MDIO_DECLARE
|
||||
|
||||
|
||||
#define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */
|
||||
#define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */
|
||||
|
||||
#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
|
||||
#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
|
||||
#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
|
||||
|
||||
#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
|
||||
else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
|
||||
|
||||
#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
|
||||
else iop->pdat &= ~CONFIG_SYS_MDC_PIN
|
||||
|
||||
#define MIIDELAY udelay(1)
|
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC */
|
||||
|
||||
#define CONFIG_8260_CLKIN 65536000 /* in Hz */
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_IMMAP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
|
||||
#define CONFIG_BOOTARGS "root=/dev/ram rw"
|
||||
|
||||
#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
|
||||
#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_LONGHELP /* #undef to save memory */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0x09900000
|
||||
|
||||
#define CONFIG_MISC_INIT_R /* We need misc_init_r() */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||
#ifdef CONFIG_BZIP2
|
||||
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
|
||||
#else
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
|
||||
#endif /* CONFIG_BZIP2 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000
|
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
|
||||
|
||||
/* Environment is in flash, there is little space left in Serial EEPROM */
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
|
||||
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words
|
||||
*
|
||||
* If you change bits in the HRCW, you must also change the CONFIG_SYS_*
|
||||
* defines for the various registers affected by the HRCW e.g. changing
|
||||
* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
|
||||
*/
|
||||
/* 0x1686B245 */
|
||||
#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\
|
||||
HRCW_L2CPC10 | HRCW_ISB110 |\
|
||||
HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\
|
||||
HRCW_CS10PC01 | HRCW_MODCK_H0101 \
|
||||
)
|
||||
/* No slaves */
|
||||
#define CONFIG_SYS_HRCW_SLAVE1 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE2 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE3 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE4 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE5 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE6 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE7 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xF0F00000
|
||||
#ifdef CONFIG_SYS_REV_B
|
||||
#define CONFIG_SYS_DEFAULT_IMMR 0xFF000000
|
||||
#endif /* CONFIG_SYS_REV_B */
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11
|
||||
*-----------------------------------------------------------------------
|
||||
* HID0 also contains cache control.
|
||||
*
|
||||
* HID1 has only read-only information - nothing to set.
|
||||
*/
|
||||
#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
|
||||
HID0_IFEM|HID0_ABE)
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
|
||||
#define CONFIG_SYS_HID2 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5
|
||||
*-----------------------------------------------------------------------
|
||||
* turn on Checkstop Reset Enable
|
||||
*/
|
||||
#define CONFIG_SYS_RMR RMR_CSRE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_BCR 0xA01C0000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
|
||||
*/
|
||||
#if defined (CONFIG_WATCHDOG)
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
|
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
|
||||
#else
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
|
||||
SYPCR_SWRI|SYPCR_SWP)
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40
|
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
||||
* and enable Time Counter
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
||||
* Periodic timer
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8
|
||||
*-----------------------------------------------------------------------
|
||||
* Ensure DFBRG is Divide by 16
|
||||
*/
|
||||
#define CONFIG_SYS_SCCR SCCR_DFBRG01
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_RCCR 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSize Device
|
||||
* ---- --- ------- ----------------------------- ------
|
||||
* 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash
|
||||
* 1 60x SDRAM 64 bit SDRAM
|
||||
* 2 Local SDRAM 32 bit SDRAM
|
||||
*/
|
||||
#define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory
|
||||
controller, rely on initialisation
|
||||
performed by the Interphase boot firmware.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xFE000882
|
||||
#ifdef CONFIG_SYS_REV_B
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_8 | BRx_V)
|
||||
#else /* Rev. D */
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V)
|
||||
#endif /* CONFIG_SYS_REV_B */
|
||||
|
||||
#define CONFIG_SYS_MPTPR 0x7F00
|
||||
|
||||
/* Please note that 60x SDRAM MUST start at 0 */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_60x_BR 0x00000041
|
||||
#define CONFIG_SYS_60x_OR 0xF0002CD0
|
||||
#define CONFIG_SYS_PSDMR 0x0049929A
|
||||
#define CONFIG_SYS_PSRT 0x07
|
||||
|
||||
#define CONFIG_SYS_LSDRAM_BASE 0xF7000000
|
||||
#define CONFIG_SYS_LOC_BR 0x00001861
|
||||
#define CONFIG_SYS_LOC_OR 0xFF803280
|
||||
#define CONFIG_SYS_LSDMR 0x8285A552
|
||||
#define CONFIG_SYS_LSRT 0x07
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -1,549 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stuart Hughes <stuarth@lineo.com>
|
||||
* This file is based on similar values for other boards found in other
|
||||
* U-Boot config files, and some that I found in the mpc8260ads manual.
|
||||
*
|
||||
* Note: my board is a PILOT rev.
|
||||
* Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
|
||||
*
|
||||
* (C) Copyright 2003-2004 Arabella Software Ltd.
|
||||
* Yuli Barcohen <yuli@arabellasw.com>
|
||||
* Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
|
||||
* Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
|
||||
* Ported to MPC8272ADS board.
|
||||
*
|
||||
* Copyright (c) 2005 MontaVista Software, Inc.
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
* Added support for PCI bridge on MPC8272ADS
|
||||
*
|
||||
* Copyright (C) Freescale Semiconductor, Inc. 2006-2009.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
|
||||
#endif
|
||||
|
||||
#define CONFIG_CPM2 1 /* Has a CPM2 */
|
||||
|
||||
/*
|
||||
* Figure out if we are booting low via flash HRCW or high via the BCSR.
|
||||
*/
|
||||
#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
|
||||
# define CONFIG_SYS_LOWBOOT 1
|
||||
#endif
|
||||
|
||||
/* ADS flavours */
|
||||
#define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */
|
||||
#define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */
|
||||
#define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
|
||||
#define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */
|
||||
|
||||
#ifndef CONFIG_ADSTYPE
|
||||
#define CONFIG_ADSTYPE CONFIG_SYS_8260ADS
|
||||
#endif /* CONFIG_ADSTYPE */
|
||||
|
||||
#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
|
||||
#define CONFIG_MPC8272 1
|
||||
#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
|
||||
/*
|
||||
* Actually MPC8275, but the code is littered with ifdefs that
|
||||
* apply to both, or which use this ifdef to assume board-specific
|
||||
* details. :-(
|
||||
*/
|
||||
#define CONFIG_MPC8272 1
|
||||
#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
|
||||
|
||||
/* allow serial and ethaddr to be overwritten */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*
|
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
||||
* for SCC).
|
||||
*
|
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must
|
||||
* defined elsewhere (for example, on the cogent platform, there are serial
|
||||
* ports on the motherboard which are used for the serial console - see
|
||||
* cogent/cma101/serial.[ch]).
|
||||
*/
|
||||
#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
|
||||
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on something else */
|
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
|
||||
|
||||
/*
|
||||
* select ethernet configuration
|
||||
*
|
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
|
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
|
||||
* for FCC)
|
||||
*
|
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
|
||||
* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
|
||||
*/
|
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
||||
|
||||
#ifdef CONFIG_ETHER_ON_FCC
|
||||
|
||||
#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
|
||||
|
||||
#if CONFIG_ETHER_INDEX == 1
|
||||
|
||||
# define CONFIG_SYS_PHY_ADDR 0
|
||||
# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
|
||||
# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
|
||||
|
||||
#elif CONFIG_ETHER_INDEX == 2
|
||||
|
||||
#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
|
||||
# define CONFIG_SYS_PHY_ADDR 3
|
||||
# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
|
||||
#else /* RxCLK is CLK13, TxCLK is CLK14 */
|
||||
# define CONFIG_SYS_PHY_ADDR 0
|
||||
# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
|
||||
#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
|
||||
|
||||
# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
||||
|
||||
#endif /* CONFIG_ETHER_INDEX */
|
||||
|
||||
#define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
|
||||
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
|
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications
|
||||
*/
|
||||
#define MDIO_PORT 2 /* Port C */
|
||||
#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
|
||||
(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
|
||||
#define MDC_DECLARE MDIO_DECLARE
|
||||
|
||||
#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
|
||||
#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */
|
||||
#define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */
|
||||
#else
|
||||
#define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */
|
||||
#define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */
|
||||
#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
|
||||
|
||||
#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
|
||||
#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
|
||||
#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
|
||||
|
||||
#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
|
||||
else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
|
||||
|
||||
#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
|
||||
else iop->pdat &= ~CONFIG_SYS_MDC_PIN
|
||||
|
||||
#define MIIDELAY udelay(1)
|
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC */
|
||||
|
||||
#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
|
||||
#undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
|
||||
#else
|
||||
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
|
||||
#define CONFIG_SPD_ADDR 0x50
|
||||
#endif
|
||||
#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
|
||||
|
||||
/*PCI*/
|
||||
#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_PCI_BOOTDELAY 0
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SDRAM_PBI
|
||||
#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_8260_CLKIN
|
||||
#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
|
||||
#define CONFIG_8260_CLKIN 100000000 /* in Hz */
|
||||
#else
|
||||
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
#define OF_TBCLK (bd->bi_busfreq / 4)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_CDP
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IMMAP
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_PORTIO
|
||||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_SAVES
|
||||
#define CONFIG_CMD_SDRAM
|
||||
|
||||
#undef CONFIG_CMD_XIMG
|
||||
|
||||
#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
|
||||
#undef CONFIG_CMD_SDRAM
|
||||
#undef CONFIG_CMD_I2C
|
||||
|
||||
#elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
|
||||
#undef CONFIG_CMD_SDRAM
|
||||
#undef CONFIG_CMD_I2C
|
||||
|
||||
#else
|
||||
#undef CONFIG_CMD_PCI
|
||||
|
||||
#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
|
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2"
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
|
||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
|
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
|
||||
#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
|
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xff800000
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
|
||||
#define CONFIG_SYS_FLASH_SIZE 8
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
|
||||
#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
|
||||
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
|
||||
|
||||
/*
|
||||
* JFFS2 partitions
|
||||
*
|
||||
* Note: fake mtd_id used, no linux mtd map file
|
||||
*/
|
||||
#define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
|
||||
#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
|
||||
|
||||
/* this is stuff came out of the Motorola docs */
|
||||
#ifndef CONFIG_SYS_LOWBOOT
|
||||
#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_IMMR 0xF0000000
|
||||
#define CONFIG_SYS_BCSR 0xF4500000
|
||||
#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
|
||||
#define CONFIG_SYS_PCI_INT 0xF8200000
|
||||
#endif
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_LSDRAM_BASE 0xFD000000
|
||||
|
||||
#define RS232EN_1 0x02000002
|
||||
#define RS232EN_2 0x01000001
|
||||
#define FETHIEN1 0x08000008
|
||||
#define FETH1_RST 0x04000004
|
||||
#define FETHIEN2 0x10000000
|
||||
#define FETH2_RST 0x08000000
|
||||
#define BCSR_PCI_MODE 0x01000000
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#ifdef CONFIG_SYS_LOWBOOT
|
||||
/* PQ2FADS flash HRCW = 0x0EB4B645 */
|
||||
#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
|
||||
( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
|
||||
( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
|
||||
( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
|
||||
)
|
||||
#else
|
||||
/* PQ2FADS BCSR HRCW = 0x0CB23645 */
|
||||
#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
|
||||
( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
|
||||
( HRCW_BMS | HRCW_APPC10 ) |\
|
||||
( HRCW_MODCK_H0101 ) \
|
||||
)
|
||||
#endif
|
||||
/* no slaves */
|
||||
#define CONFIG_SYS_HRCW_SLAVE1 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE2 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE3 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE4 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE5 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE6 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE7 0
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
# define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#ifdef CONFIG_BZIP2
|
||||
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
|
||||
#else
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
|
||||
#endif /* CONFIG_BZIP2 */
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
# define CONFIG_ENV_IS_IN_FLASH 1
|
||||
# define CONFIG_ENV_SECT_SIZE 0x40000
|
||||
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
|
||||
#else
|
||||
# define CONFIG_ENV_IS_IN_NVRAM 1
|
||||
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
# define CONFIG_ENV_SIZE 0x200
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT 0
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
|
||||
|
||||
#define CONFIG_SYS_HID2 0
|
||||
|
||||
#define CONFIG_SYS_SYPCR 0xFFFFFFC3
|
||||
#define CONFIG_SYS_BCR 0x100C0000
|
||||
#define CONFIG_SYS_SIUMCR 0x0A200000
|
||||
#define CONFIG_SYS_SCCR SCCR_DFBRG01
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xFF800876
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801)
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
|
||||
|
||||
/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
|
||||
|
||||
#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
|
||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xFFFF8010
|
||||
#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
|
||||
#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
|
||||
#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_RMR RMR_CSRE
|
||||
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
#define CONFIG_SYS_RCCR 0
|
||||
|
||||
#if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
|
||||
#undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */
|
||||
#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
|
||||
|
||||
#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
|
||||
#define CONFIG_SYS_OR2 0xFE002EC0
|
||||
#define CONFIG_SYS_PSDMR 0x824B36A3
|
||||
#define CONFIG_SYS_PSRT 0x13
|
||||
#define CONFIG_SYS_LSDMR 0x828737A3
|
||||
#define CONFIG_SYS_LSRT 0x13
|
||||
#define CONFIG_SYS_MPTPR 0x2800
|
||||
#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
|
||||
#define CONFIG_SYS_OR2 0xFC002CC0
|
||||
#define CONFIG_SYS_PSDMR 0x834E24A3
|
||||
#define CONFIG_SYS_PSRT 0x13
|
||||
#define CONFIG_SYS_MPTPR 0x2800
|
||||
#else
|
||||
#define CONFIG_SYS_OR2 0xFF000CA0
|
||||
#define CONFIG_SYS_PSDMR 0x016EB452
|
||||
#define CONFIG_SYS_PSRT 0x21
|
||||
#define CONFIG_SYS_LSDMR 0x0086A522
|
||||
#define CONFIG_SYS_LSRT 0x21
|
||||
#define CONFIG_SYS_MPTPR 0x1900
|
||||
#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0x04400000
|
||||
|
||||
#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
|
||||
|
||||
/* PCI Memory map (if different from default map */
|
||||
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
|
||||
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
|
||||
#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
|
||||
PICMR_PREFETCH_EN)
|
||||
|
||||
/*
|
||||
* These are the windows that allow the CPU to access PCI address space.
|
||||
* All three PCI master windows, which allow the CPU to access PCI
|
||||
* prefetch, non prefetch, and IO space (see below), must all fit within
|
||||
* these windows.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Master window that allows the CPU to access PCI Memory (prefetch).
|
||||
* This window will be setup with the second set of Outbound ATU registers
|
||||
* in the bridge.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
|
||||
#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
|
||||
#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
|
||||
#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
|
||||
#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
|
||||
|
||||
/*
|
||||
* Master window that allows the CPU to access PCI Memory (non-prefetch).
|
||||
* This window will be setup with the second set of Outbound ATU registers
|
||||
* in the bridge.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
|
||||
#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
|
||||
#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
|
||||
#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
|
||||
#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
|
||||
|
||||
/*
|
||||
* Master window that allows the CPU to access PCI IO space.
|
||||
* This window will be setup with the first set of Outbound ATU registers
|
||||
* in the bridge.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
|
||||
#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
|
||||
#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
|
||||
#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
|
||||
#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
|
||||
|
||||
|
||||
/* PCIBR0 - for PCI IO*/
|
||||
#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
|
||||
#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
|
||||
/* PCIBR1 - prefetch and non-prefetch regions joined together */
|
||||
#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
|
||||
#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
|
||||
|
||||
#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
|
||||
|
||||
#define CONFIG_HAS_ETH0
|
||||
|
||||
#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
|
||||
#define CONFIG_HAS_ETH1
|
||||
#endif
|
||||
|
||||
#define CONFIG_NETDEV eth0
|
||||
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=" __stringify(CONFIG_NETDEV) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" $filesize; " \
|
||||
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" $filesize\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"console=ttyCPM0\0" \
|
||||
"setbootargs=setenv bootargs " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
||||
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv rootdev /dev/nfs;" \
|
||||
"run setipargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv rootdev /dev/ram;" \
|
||||
"run setbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -15,14 +15,6 @@
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
|
||||
|
||||
#ifdef CONFIG_NAND_U_BOOT
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
|
||||
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
#endif /* CONFIG_NAND_U_BOOT */
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFE000000
|
||||
#endif
|
||||
@@ -93,10 +85,6 @@
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xE0000000
|
||||
|
||||
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Arbiter Setup
|
||||
*/
|
||||
@@ -281,17 +269,10 @@
|
||||
| OR_FCM_EHTR)
|
||||
/* 0xFFFF8396 */
|
||||
|
||||
#ifdef CONFIG_NAND_U_BOOT
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
|
||||
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
|
||||
#else
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
|
||||
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
@@ -459,16 +440,7 @@
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#if defined(CONFIG_NAND_U_BOOT)
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_OFFSET (512 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
||||
CONFIG_ENV_RANGE)
|
||||
#elif !defined(CONFIG_SYS_RAMBOOT)
|
||||
#if !defined(CONFIG_SYS_RAMBOOT)
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR \
|
||||
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
@@ -503,7 +475,7 @@
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#undef CONFIG_CMD_SAVEENV
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#endif
|
||||
|
||||
@@ -19,18 +19,6 @@
|
||||
#define CONFIG_PHYS_64BIT 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND
|
||||
#define CONFIG_NAND_U_BOOT 1
|
||||
#define CONFIG_RAMBOOT_NAND 1
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
|
||||
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDCARD
|
||||
#define CONFIG_RAMBOOT_SDCARD 1
|
||||
#define CONFIG_SYS_TEXT_BASE 0xf8f40000
|
||||
@@ -222,8 +210,7 @@
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
|
||||
defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#else
|
||||
@@ -352,17 +339,10 @@
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_NAND
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#else
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR4_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
|
||||
@@ -625,12 +605,7 @@
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_RAMBOOT_NAND)
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
|
||||
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#if defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_BUS 0
|
||||
#define CONFIG_ENV_SPI_CS 0
|
||||
|
||||
@@ -49,18 +49,6 @@ extern unsigned long get_clock_freq(void);
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
|
||||
#ifdef CONFIG_NAND
|
||||
#define CONFIG_NAND_U_BOOT 1
|
||||
#define CONFIG_RAMBOOT_NAND 1
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
|
||||
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xfff80000
|
||||
#endif
|
||||
@@ -180,12 +168,7 @@ extern unsigned long get_clock_freq(void);
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_NAND)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
@@ -228,17 +211,10 @@ extern unsigned long get_clock_freq(void);
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_NAND
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */
|
||||
#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#else
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
|
||||
@@ -476,11 +452,6 @@ extern unsigned long get_clock_freq(void);
|
||||
* Environment
|
||||
*/
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_RAMBOOT_NAND)
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
@@ -20,18 +20,6 @@
|
||||
#define CONFIG_PHYS_64BIT
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND
|
||||
#define CONFIG_NAND_U_BOOT
|
||||
#define CONFIG_RAMBOOT_NAND
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
|
||||
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xeff40000
|
||||
#endif
|
||||
@@ -208,12 +196,7 @@
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_NAND)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
@@ -353,17 +336,10 @@
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_NAND
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#else
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
#endif
|
||||
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
@@ -600,12 +576,6 @@
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_RAMBOOT_NAND)
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_OFFSET ((512 * 1024)\
|
||||
+ CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
|
||||
@@ -14,23 +14,6 @@
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#ifdef CONFIG_NAND
|
||||
#define CONFIG_NAND_U_BOOT
|
||||
#define CONFIG_RAMBOOT_NAND
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND_U_BOOT
|
||||
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x11001000
|
||||
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xeff40000
|
||||
#endif
|
||||
@@ -162,7 +145,6 @@ extern unsigned long get_clock_freq(void);
|
||||
#define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */
|
||||
#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
|
||||
|
||||
#ifndef CONFIG_NAND
|
||||
#define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
@@ -179,11 +161,8 @@ extern unsigned long get_clock_freq(void);
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
#else
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
|
||||
#if defined(CONFIG_SYS_SPL)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
@@ -239,17 +218,6 @@ extern unsigned long get_clock_freq(void);
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_NAND
|
||||
/* NAND Base Address */
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
/* chip select 1 - BCSR */
|
||||
#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
|
||||
| BR_MS_GPCM | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD)
|
||||
#else
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
/* chip select 1 - BCSR */
|
||||
@@ -258,7 +226,6 @@ extern unsigned long get_clock_freq(void);
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD)
|
||||
#endif
|
||||
|
||||
/* Serial Port
|
||||
* open - index 2
|
||||
@@ -381,15 +348,9 @@ extern unsigned long get_clock_freq(void);
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_RAMBOOT_NAND)
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
@@ -496,15 +457,10 @@ extern unsigned long get_clock_freq(void);
|
||||
#define CONFIG_PHY_MARVELL
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_NAND
|
||||
/* Default address of microcode for the Linux Fman driver */
|
||||
/* QE microcode/firmware address */
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
|
||||
#else
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0x1f00000
|
||||
#endif
|
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
|
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
|
||||
|
||||
|
||||
@@ -1,279 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004 Arabella Software Ltd.
|
||||
* Yuli Barcohen <yuli@arabellasw.com>
|
||||
*
|
||||
* U-Boot configuration for Analogue&Micro Rattler boards.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#ifdef CONFIG_MPC8248
|
||||
#define CPU_ID_STR "MPC8248"
|
||||
#else
|
||||
#define CPU_ID_STR "MPC8250"
|
||||
#endif /* CONFIG_MPC8248 */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFE000000
|
||||
|
||||
#define CONFIG_CPM2 1 /* Has a CPM2 */
|
||||
|
||||
#define CONFIG_RATTLER /* Analogue&Micro Rattler board */
|
||||
|
||||
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* Select serial console configuration
|
||||
*
|
||||
* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
||||
* for SCC).
|
||||
*/
|
||||
#define CONFIG_CONS_ON_SMC /* Console is on SMC */
|
||||
#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
|
||||
#undef CONFIG_CONS_NONE /* It's not on external UART */
|
||||
#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
|
||||
|
||||
/*
|
||||
* Select ethernet configuration
|
||||
*
|
||||
* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
|
||||
* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
|
||||
* SCC, 1-3 for FCC)
|
||||
*
|
||||
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
|
||||
* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
|
||||
* must be unset.
|
||||
*/
|
||||
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* No external Ethernet */
|
||||
|
||||
#ifdef CONFIG_ETHER_ON_FCC
|
||||
|
||||
#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
|
||||
|
||||
#if (CONFIG_ETHER_INDEX == 1)
|
||||
|
||||
/* - Rx clock is CLK11
|
||||
* - Tx clock is CLK10
|
||||
* - BDs/buffers on 60x bus
|
||||
* - Full duplex
|
||||
*/
|
||||
#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
|
||||
#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
|
||||
#define CONFIG_SYS_CPMFCR_RAMTYPE 0
|
||||
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
|
||||
#elif (CONFIG_ETHER_INDEX == 2)
|
||||
|
||||
/* - Rx clock is CLK15
|
||||
* - Tx clock is CLK14
|
||||
* - BDs/buffers on 60x bus
|
||||
* - Full duplex
|
||||
*/
|
||||
#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
||||
#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
|
||||
#define CONFIG_SYS_CPMFCR_RAMTYPE 0
|
||||
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
|
||||
#endif /* CONFIG_ETHER_INDEX */
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
|
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications
|
||||
*/
|
||||
#define MDIO_PORT 2 /* Port C */
|
||||
#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
|
||||
(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
|
||||
#define MDC_DECLARE MDIO_DECLARE
|
||||
|
||||
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
|
||||
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
|
||||
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
|
||||
|
||||
#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
|
||||
else iop->pdat &= ~0x00400000
|
||||
|
||||
#define MDC(bit) if(bit) iop->pdat |= 0x00800000; \
|
||||
else iop->pdat &= ~0x00800000
|
||||
|
||||
#define MIIDELAY udelay(1)
|
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC */
|
||||
|
||||
#ifndef CONFIG_8260_CLKIN
|
||||
#define CONFIG_8260_CLKIN 100000000 /* in Hz */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_IMMAP
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
|
||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
|
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
|
||||
#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
|
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
|
||||
|
||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP
|
||||
|
||||
#if defined(CONFIG_CMD_JFFS2)
|
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
|
||||
#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
|
||||
|
||||
/*
|
||||
* JFFS2 partitions
|
||||
*
|
||||
*/
|
||||
/* No command line, one static partition */
|
||||
#undef CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_JFFS2_DEV "nor0"
|
||||
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x00100000
|
||||
|
||||
/* mtdparts command line support */
|
||||
/* Note: fake mtd_id used, no linux mtd map file */
|
||||
/*
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define MTDIDS_DEFAULT "nor0=rattler-0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)"
|
||||
*/
|
||||
#endif /* CONFIG_CMD_JFFS2 */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#endif /* CONFIG_ENV_IS_IN_FLASH */
|
||||
|
||||
#define CONFIG_SYS_DEFAULT_IMMR 0xFF010000
|
||||
|
||||
#define CONFIG_SYS_IMMR 0xF0000000
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE 32
|
||||
#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
|
||||
#define CONFIG_SYS_SDRAM_OR 0xFE002EC0
|
||||
|
||||
#define CONFIG_SYS_BCSR 0xFC000000
|
||||
|
||||
/* Hard reset configuration word */
|
||||
#define CONFIG_SYS_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */
|
||||
/* No slaves */
|
||||
#define CONFIG_SYS_HRCW_SLAVE1 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE2 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE3 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE4 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE5 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE6 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE7 0
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT 0
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
|
||||
|
||||
#define CONFIG_SYS_HID2 0
|
||||
|
||||
#define CONFIG_SYS_SIUMCR 0x0E04C000
|
||||
#define CONFIG_SYS_SYPCR 0xFFFFFFC3
|
||||
#define CONFIG_SYS_BCR 0x00000000
|
||||
#define CONFIG_SYS_SCCR SCCR_DFBRG01
|
||||
|
||||
#define CONFIG_SYS_RMR RMR_CSRE
|
||||
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
#define CONFIG_SYS_RCCR 0
|
||||
|
||||
#define CONFIG_SYS_PSDMR 0x8249A452
|
||||
#define CONFIG_SYS_PSRT 0x1F
|
||||
#define CONFIG_SYS_MPTPR 0x2000
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001001)
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xFF001ED6
|
||||
#define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
|
||||
#define CONFIG_SYS_OR7_PRELIM 0xFFFF87F6
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -1,580 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) Sheldon Instruments, Inc. 2008
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
/*
|
||||
* simpc8313 board configuration file
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_NAND_U_BOOT
|
||||
|
||||
#define CONFIG_E300 1
|
||||
#define CONFIG_MPC831x 1
|
||||
#define CONFIG_MPC8313 1
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
|
||||
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
|
||||
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
#define CONFIG_FSL_ELBC 1
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
/*
|
||||
* On-board devices
|
||||
*
|
||||
* TSEC1 is Marvell PHY 88E1118
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_33MHZ
|
||||
|
||||
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
|
||||
|
||||
#define CONFIG_SYS_IMMR 0xE0000000
|
||||
|
||||
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00001000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x07f00000
|
||||
|
||||
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
|
||||
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
|
||||
|
||||
/*
|
||||
* Device configurations
|
||||
*/
|
||||
#define CONFIG_TSEC1
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
/* DDR is system memory*/
|
||||
#define CONFIG_SYS_DDR_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
||||
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_MAX_MEM_MAPPED (512 << 20)
|
||||
|
||||
#define CONFIG_SYS_DDRCDR (DDRCDR_EN \
|
||||
| DDRCDR_PZ_NOMZ \
|
||||
| DDRCDR_NZ_NOMZ \
|
||||
| DDRCDR_M_ODR)
|
||||
/* 0x73000002 TODO ODR & DRN ? */
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#if !defined(CONFIG_NAND_SPL)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
|
||||
|
||||
/*
|
||||
* Local Bus LCRR and LBCR regs
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
|
||||
#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
|
||||
| (0xFF << LBCR_BMT_SHIFT) \
|
||||
| 0xF) /* 0x0004ff0f */
|
||||
|
||||
/* LB refresh timer prescal, 266MHz/32 */
|
||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000
|
||||
|
||||
/* drivers/mtd/nand/nand.c */
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_NAND_BASE 0xFFF00000
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE 0xE2800000
|
||||
#endif
|
||||
#define CONFIG_SYS_FPGA_BASE 0xFF000000
|
||||
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
|
||||
| BR_DECC_CHK_GEN /* Use HW ECC */ \
|
||||
| BR_PS_8 /* 8 bit Port */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
|
||||
#ifdef CONFIG_NAND_SP
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
|
||||
/* NAND chip block size */
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10)
|
||||
#define NAND_CACHE_PAGES 32
|
||||
#elif defined(CONFIG_NAND_LP)
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
|
||||
| OR_FCM_PGS \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 2048 /* NAND chip page size */
|
||||
/* NAND chip block size */
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
|
||||
#define NAND_CACHE_PAGES 64
|
||||
#else
|
||||
#error Page size of NAND not defined.
|
||||
#endif /* CONFIG_NAND_SP */
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
|
||||
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA_BASE \
|
||||
| BR_PS_16 \
|
||||
| BR_MS_UPMA \
|
||||
| BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_2MB \
|
||||
| OR_UPM_BCTLD)
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_2MB)
|
||||
|
||||
/*
|
||||
* JFFS2 configuration
|
||||
*/
|
||||
#define CONFIG_JFFS2_NAND
|
||||
#define CONFIG_JFFS2_DEV "nand0"
|
||||
|
||||
/* mtdparts command line support */
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
|
||||
#define MTDIDS_DEFAULT "nand0=nand0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#define CONFIG_NS16550_MIN_FUNCTIONS
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
|
||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
|
||||
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
|
||||
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
|
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
/*
|
||||
* TSEC
|
||||
*/
|
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
|
||||
|
||||
#define CONFIG_GMII /* MII PHY management */
|
||||
|
||||
#ifdef CONFIG_TSEC1
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_TSEC1_NAME "TSEC0"
|
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
|
||||
#define TSEC1_PHY_ADDR 0x0
|
||||
#define TSEC1_FLAGS TSEC_GIGABIT
|
||||
#define TSEC1_PHYIDX 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TSEC2
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_TSEC2_NAME "TSEC1"
|
||||
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
|
||||
#define TSEC2_PHY_ADDR 4
|
||||
#define TSEC2_FLAGS TSEC_GIGABIT
|
||||
#define TSEC2_PHYIDX 0
|
||||
#endif
|
||||
|
||||
|
||||
/* Options are: TSEC[0-1] */
|
||||
#define CONFIG_ETHPRIME "TSEC1"
|
||||
|
||||
/*
|
||||
* Configure on-board RTC
|
||||
*/
|
||||
#define CONFIG_RTC_DS1337
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#if defined(CONFIG_NAND_U_BOOT)
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_OFFSET (768 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
|
||||
#define CONFIG_ENV_OFFSET_REDUND \
|
||||
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
|
||||
#elif !defined(CONFIG_SYS_RAMBOOT)
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR \
|
||||
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_FLASH
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_JFFS2
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
|
||||
#undef CONFIG_CMD_SAVEENV
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
|
||||
+ sizeof(CONFIG_SYS_PROMPT) \
|
||||
+ 16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 256 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
/* Initial Memory map for Linux*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
|
||||
|
||||
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
|
||||
|
||||
#define CONFIG_SYS_HRCW_LOW (HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
|
||||
| 0x20000000 /* reserved */ \
|
||||
| HRCWL_DDR_TO_SCB_CLK_2X1 \
|
||||
| HRCWL_CSB_TO_CLKIN_4X1 \
|
||||
| HRCWL_CORE_TO_CSB_2_5X1)
|
||||
|
||||
#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
|
||||
|
||||
#define CONFIG_SYS_HRCW_HIGH_BASE (HRCWH_PCI_HOST \
|
||||
| HRCWH_PCI1_ARBITER_ENABLE \
|
||||
| HRCWH_CORE_ENABLE \
|
||||
| HRCWH_BOOTSEQ_DISABLE \
|
||||
| HRCWH_SW_WATCHDOG_DISABLE \
|
||||
| HRCWH_TSEC1M_IN_RGMII \
|
||||
| HRCWH_TSEC2M_IN_RGMII \
|
||||
| HRCWH_BIG_ENDIAN \
|
||||
| HRCWH_LALE_NORMAL)
|
||||
|
||||
#ifdef CONFIG_NAND_LP
|
||||
#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
|
||||
| HRCWH_FROM_0XFFF00100 \
|
||||
| HRCWH_ROM_LOC_NAND_LP_8BIT \
|
||||
| HRCWH_RL_EXT_NAND)
|
||||
#else
|
||||
#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
|
||||
| HRCWH_FROM_0XFFF00100 \
|
||||
| HRCWH_ROM_LOC_NAND_SP_8BIT \
|
||||
| HRCWH_RL_EXT_NAND)
|
||||
#endif
|
||||
|
||||
/* System IO Config */
|
||||
#define CONFIG_SYS_SICRH (SICRH_ETSEC2_B \
|
||||
| SICRH_ETSEC2_C \
|
||||
| SICRH_ETSEC2_D \
|
||||
| SICRH_ETSEC2_E \
|
||||
| SICRH_ETSEC2_F \
|
||||
| SICRH_ETSEC2_G \
|
||||
| SICRH_TSOBI1 \
|
||||
| SICRH_TSOBI2)
|
||||
#define CONFIG_SYS_SICRL (SICRL_LBC \
|
||||
| SICRL_USBDR_10 \
|
||||
| SICRL_ETSEC2_A)
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT 0x000000000
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
|
||||
| HID0_ENABLE_INSTRUCTION_CACHE \
|
||||
| HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
|
||||
|
||||
#define CONFIG_SYS_HID2 HID2_HBE
|
||||
|
||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
||||
|
||||
/* DDR @ 0x00000000 */
|
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
|
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
|
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
|
||||
| BATL_PP_RW)
|
||||
#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
|
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
|
||||
/* PCI @ 0x80000000 */
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE \
|
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE \
|
||||
| BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE \
|
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
|
||||
/* PCI2 not supported on 8313 */
|
||||
#define CONFIG_SYS_IBAT4L (0)
|
||||
#define CONFIG_SYS_IBAT4U (0)
|
||||
|
||||
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
|
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
|
||||
| BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
|
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
|
||||
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
|
||||
#define CONFIG_SYS_IBAT6L (0xF0000000 \
|
||||
| BATL_PP_RW \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT6U (0xF0000000 \
|
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_IBAT7L (0)
|
||||
#define CONFIG_SYS_IBAT7U (0)
|
||||
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
||||
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
||||
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
|
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_NETDEV "eth1"
|
||||
|
||||
#define CONFIG_HOSTNAME simpc8313
|
||||
#define CONFIG_ROOTPATH "/tftpboot/"
|
||||
#define CONFIG_BOOTFILE "/tftpboot/uImage"
|
||||
/* U-Boot image on TFTP server */
|
||||
#define CONFIG_UBOOTPATH "u-boot-nand.bin"
|
||||
#define CONFIG_FDTFILE "simpc8313.dtb"
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 500000
|
||||
#define CONFIG_BOOTDELAY 5 /* 5 second delay */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=" CONFIG_NETDEV "\0" \
|
||||
"ethprime=TSEC1\0" \
|
||||
"uboot=" CONFIG_UBOOTPATH "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" $filesize; " \
|
||||
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" $filesize\0" \
|
||||
"fdtaddr=ae0000\0" \
|
||||
"fdtfile=" CONFIG_FDTFILE "\0" \
|
||||
"console=ttyS0\0" \
|
||||
"setbootargs=setenv bootargs " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
||||
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
|
||||
"$netdev:off " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
||||
"load_uboot=tftp 100000 u-boot-nand.bin\0" \
|
||||
"burn_uboot=nand erase u-boot 80000; " \
|
||||
"nand write 100000 u-boot $filesize\0" \
|
||||
"update_uboot=run load_uboot;run burn_uboot\0" \
|
||||
"mtdids=nand0=nand0\0" \
|
||||
"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
|
||||
"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
|
||||
"console=ttyS0,115200\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv rootdev /dev/nfs;" \
|
||||
"run setbootargs;" \
|
||||
"run setipargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv rootdev /dev/ram;" \
|
||||
"run setbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -201,6 +201,12 @@ unsigned long get_board_ddr_clk(void);
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V)
|
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
|
||||
|
||||
/*
|
||||
* TDM Definition
|
||||
*/
|
||||
#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
|
||||
|
||||
/* NOR Flash Timing Params */
|
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
|
||||
|
||||
@@ -230,6 +230,12 @@
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V)
|
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
|
||||
|
||||
/*
|
||||
* TDM Definition
|
||||
*/
|
||||
#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
|
||||
|
||||
/* NOR Flash Timing Params */
|
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
|
||||
|
||||
@@ -227,8 +227,9 @@ unsigned long get_board_ddr_clk(void);
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_FSL_DDR3
|
||||
#undef CONFIG_FSL_DDR_INTERACTIVE
|
||||
|
||||
@@ -1,261 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2003-2005 Arabella Software Ltd.
|
||||
* Yuli Barcohen <yuli@arabellasw.com>
|
||||
*
|
||||
* U-Boot configuration for Zephyr Engineering ZPC.1900 board.
|
||||
* This port was developed and tested on Revision C board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFE000000
|
||||
|
||||
#define CPU_ID_STR "MPC8265"
|
||||
#define CONFIG_CPM2 1 /* Has a CPM2 */
|
||||
|
||||
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* Select serial console configuration
|
||||
*
|
||||
* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
||||
* for SCC).
|
||||
*/
|
||||
#define CONFIG_CONS_ON_SMC /* Console is on SMC */
|
||||
#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
|
||||
#undef CONFIG_CONS_NONE /* It's not on external UART */
|
||||
#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
|
||||
|
||||
/*
|
||||
* Select ethernet configuration
|
||||
*
|
||||
* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
|
||||
* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
|
||||
* SCC, 1-3 for FCC)
|
||||
*
|
||||
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
|
||||
* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
|
||||
* must be unset.
|
||||
*/
|
||||
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* No external Ethernet */
|
||||
|
||||
#ifdef CONFIG_ETHER_ON_FCC
|
||||
|
||||
#define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */
|
||||
|
||||
#if (CONFIG_ETHER_INDEX == 2)
|
||||
/*
|
||||
* - Rx clock is CLK13
|
||||
* - Tx clock is CLK14
|
||||
* - Select bus for bd/buffers (see 28-13)
|
||||
* - Full duplex
|
||||
*/
|
||||
# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
||||
# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
|
||||
# define CONFIG_SYS_CPMFCR_RAMTYPE 0
|
||||
# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
|
||||
#endif /* CONFIG_ETHER_INDEX */
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
|
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications
|
||||
*/
|
||||
#define MDIO_PORT 2 /* Port C */
|
||||
#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
|
||||
(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
|
||||
#define MDC_DECLARE MDIO_DECLARE
|
||||
|
||||
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
|
||||
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
|
||||
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
|
||||
|
||||
#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
|
||||
else iop->pdat &= ~0x00400000
|
||||
|
||||
#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
|
||||
else iop->pdat &= ~0x00200000
|
||||
|
||||
#define MIIDELAY udelay(1)
|
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC */
|
||||
|
||||
#ifndef CONFIG_8260_CLKIN
|
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_IMMAP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp"
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
|
||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
|
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
|
||||
#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
|
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE 64
|
||||
|
||||
#define CONFIG_SYS_IMMR 0xF0000000
|
||||
#define CONFIG_SYS_LSDRAM_BASE 0xFC000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000
|
||||
#define CONFIG_SYS_BCSR 0xFEA00000
|
||||
#define CONFIG_SYS_EEPROM 0xFEB00000
|
||||
#define CONFIG_SYS_FLSIMM_BASE 0xFF000000
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLSIMM_BASE }
|
||||
|
||||
#define BCSR_PCI_MODE 0x01
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/* Hard reset configuration word */
|
||||
#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\
|
||||
HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
|
||||
HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\
|
||||
HRCW_MODCK_H0111 \
|
||||
) /* 0x16848207 */
|
||||
/* No slaves */
|
||||
#define CONFIG_SYS_HRCW_SLAVE1 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE2 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE3 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE4 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE5 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE6 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE7 0
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#if !defined(CONFIG_ENV_IS_IN_FLASH) && !defined(CONFIG_ENV_IS_IN_NVRAM)
|
||||
#define CONFIG_ENV_IS_IN_NVRAM 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
# define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#else
|
||||
# define CONFIG_ENV_ADDR (CONFIG_SYS_EEPROM + 0x400)
|
||||
# define CONFIG_ENV_SIZE 0x1000
|
||||
# define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT (HID0_ICFI)
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
|
||||
|
||||
#define CONFIG_SYS_HID2 0
|
||||
|
||||
#define CONFIG_SYS_SIUMCR 0x42200000
|
||||
#define CONFIG_SYS_SYPCR 0xFFFFFFC3
|
||||
#define CONFIG_SYS_BCR 0x90000000
|
||||
#define CONFIG_SYS_SCCR SCCR_DFBRG01
|
||||
|
||||
#define CONFIG_SYS_RMR RMR_CSRE
|
||||
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
#define CONFIG_SYS_RCCR 0
|
||||
|
||||
#define CONFIG_SYS_PSDMR /* 0x834DA43B */0x014DA43A
|
||||
#define CONFIG_SYS_PSRT 0x0F/* 0x0C */
|
||||
#define CONFIG_SYS_LSDMR 0x0085A562
|
||||
#define CONFIG_SYS_LSRT 0x0F
|
||||
#define CONFIG_SYS_MPTPR 0x4000
|
||||
|
||||
#define CONFIG_SYS_PSDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
|
||||
#define CONFIG_SYS_PSDRAM_OR 0xFC0028C0
|
||||
#define CONFIG_SYS_LSDRAM_BR (CONFIG_SYS_LSDRAM_BASE | 0x00001861)
|
||||
#define CONFIG_SYS_LSDRAM_OR 0xFF803480
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00000801)
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xFFE00856
|
||||
#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_EEPROM | 0x00000801)
|
||||
#define CONFIG_SYS_OR5_PRELIM 0xFFFF03F6
|
||||
#define CONFIG_SYS_BR6_PRELIM (CONFIG_SYS_FLSIMM_BASE | 0x00001801)
|
||||
#define CONFIG_SYS_OR6_PRELIM 0xFF000856
|
||||
#define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
|
||||
#define CONFIG_SYS_OR7_PRELIM 0xFFFF83F6
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -18,6 +18,21 @@
|
||||
|
||||
#include <configs/ti_am335x_common.h>
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
# define CONFIG_FIT
|
||||
# define CONFIG_TIMESTAMP
|
||||
# define CONFIG_LZO
|
||||
# ifdef CONFIG_ENABLE_VBOOT
|
||||
# define CONFIG_OF_CONTROL
|
||||
# define CONFIG_OF_SEPARATE
|
||||
# define CONFIG_DEFAULT_DEVICE_TREE am335x-boneblack
|
||||
# define CONFIG_FIT_SIGNATURE
|
||||
# define CONFIG_RSA
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
|
||||
|
||||
#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
@@ -151,6 +151,7 @@
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 135
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00000000
|
||||
|
||||
#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
|
||||
#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
|
||||
|
||||
@@ -104,8 +104,6 @@
|
||||
#define CONFIG_USB_DEVICE
|
||||
#define CONFIG_USB_TTY
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
/* This delay is really for slow-to-power-on USB sticks, not the hub */
|
||||
#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 500
|
||||
|
||||
/* commands to include */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
@@ -1,443 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2001, 2002
|
||||
* Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
|
||||
|
||||
/* Environments */
|
||||
|
||||
/* bootargs */
|
||||
#define CONFIG_BOOTARGS \
|
||||
"console=ttyS0,9600 init=/linuxrc " \
|
||||
"root=/dev/nfs rw nfsroot=192.168.0.1:" \
|
||||
"/tftpboot/target " \
|
||||
"ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
|
||||
"255.255.255.0:debris:eth0:none " \
|
||||
"mtdparts=phys:12m(root),-(kernel)"
|
||||
|
||||
/* bootcmd */
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"tftp 800000 pImage; " \
|
||||
"setenv bootargs console=ttyS0,9600 init=/linuxrc " \
|
||||
"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
|
||||
"${netmask}:${hostname}:eth0:none " \
|
||||
"mtdparts=phys:12m(root),-(kernel); " \
|
||||
"bootm 800000"
|
||||
|
||||
/* bootdelay */
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot 5s */
|
||||
|
||||
/* baudrate */
|
||||
#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
|
||||
|
||||
/* loads_echo */
|
||||
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
|
||||
|
||||
/* ethaddr */
|
||||
#undef CONFIG_ETHADDR
|
||||
|
||||
/* eth2addr */
|
||||
#undef CONFIG_ETH2ADDR
|
||||
|
||||
/* eth3addr */
|
||||
#undef CONFIG_ETH3ADDR
|
||||
|
||||
/* ipaddr */
|
||||
#define CONFIG_IPADDR 192.168.0.2
|
||||
|
||||
/* serverip */
|
||||
#define CONFIG_SERVERIP 192.168.0.1
|
||||
|
||||
/* autoload */
|
||||
#undef CONFIG_SYS_AUTOLOAD
|
||||
|
||||
/* rootpath */
|
||||
#define CONFIG_ROOTPATH "/tftpboot/target"
|
||||
|
||||
/* gatewayip */
|
||||
#define CONFIG_GATEWAYIP 192.168.0.1
|
||||
|
||||
/* netmask */
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
|
||||
/* hostname */
|
||||
#define CONFIG_HOSTNAME debris
|
||||
|
||||
/* bootfile */
|
||||
#define CONFIG_BOOTFILE "pImage"
|
||||
|
||||
/* loadaddr */
|
||||
#define CONFIG_LOADADDR 800000
|
||||
|
||||
/* preboot */
|
||||
#undef CONFIG_PREBOOT
|
||||
|
||||
/* clocks_in_mhz */
|
||||
#undef CONFIG_CLOCKS_IN_MHZ
|
||||
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC8245 1
|
||||
#define CONFIG_DEBRIS 1
|
||||
|
||||
#if 0
|
||||
#define USE_DINK32 1
|
||||
#else
|
||||
#undef USE_DINK32
|
||||
#endif
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#define CONFIG_DRAM_SPEED 100 /* MHz */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_KGDB
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SAVES
|
||||
#define CONFIG_CMD_SDRAM
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_PCI_PNP
|
||||
|
||||
#define CONFIG_EEPRO100
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
|
||||
#define CONFIG_EEPRO100_SROM_WRITE
|
||||
|
||||
#define PCI_ENET0_IOADDR 0x80000000
|
||||
#define PCI_ENET0_MEMADDR 0x80000000
|
||||
#define PCI_ENET1_IOADDR 0x81000000
|
||||
#define PCI_ENET1_MEMADDR 0x81000000
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
|
||||
|
||||
#if defined (USE_DINK32)
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x00040000
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00090000
|
||||
#define CONFIG_SYS_RAMBOOT 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x00040000
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0x7C000000
|
||||
#define CONFIG_SYS_FLASH_SIZE (16*1024*1024) /* debris has tiny eeprom */
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_EUMB_ADDR 0xFC000000
|
||||
|
||||
#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
|
||||
#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
|
||||
#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */
|
||||
|
||||
/*
|
||||
* JFFS2 partitions
|
||||
*
|
||||
*/
|
||||
/* No command line, one static partition, whole device */
|
||||
#undef CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_JFFS2_DEV "nor0"
|
||||
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
||||
|
||||
/* mtdparts command line support */
|
||||
|
||||
/* Use first bank for JFFS2, second bank contains U-Boot.
|
||||
*
|
||||
* Note: fake mtd_id's used, no linux mtd map file.
|
||||
*/
|
||||
/*
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define MTDIDS_DEFAULT "nor0=debris-0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)"
|
||||
*/
|
||||
|
||||
#define CONFIG_ENV_IS_IN_NVRAM 1
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
|
||||
#define CONFIG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */
|
||||
#define CONFIG_ENV_SIZE 0x400 /* Size of the Environment - 8K */
|
||||
#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
|
||||
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xff000000
|
||||
|
||||
/*
|
||||
* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
|
||||
* NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
|
||||
*/
|
||||
#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900
|
||||
|
||||
/*
|
||||
* select i2c support configuration
|
||||
*
|
||||
* Supported configurations are {none, software, hardware} drivers.
|
||||
* If the software driver is chosen, there are some additional
|
||||
* configuration items that the driver uses to drive the port pins.
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
|
||||
#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_SOFT
|
||||
#error "Soft I2C is not configured properly. Please review!"
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
|
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
|
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
|
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
|
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
|
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
|
||||
else iop->pdat &= ~0x00010000
|
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
|
||||
else iop->pdat &= ~0x00020000
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
#endif /* CONFIG_SYS_I2C_SOFT */
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
|
||||
#define CONFIG_SYS_NS16550_CLK 7372800
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 0xFF080000
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_NS16550_COM1 + 8)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_NS16550_COM1 + 16)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_NS16550_COM1 + 24)
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
|
||||
|
||||
#define CONFIG_SYS_DLL_EXTEND 0x00
|
||||
#define CONFIG_SYS_PCI_HOLD_DEL 0x20
|
||||
|
||||
#define CONFIG_SYS_ROMNAL 15 /* rom/flash next access time */
|
||||
#define CONFIG_SYS_ROMFAL 31 /* rom/flash access time */
|
||||
|
||||
#define CONFIG_SYS_REFINT 430 /* # of clocks between CBR refresh cycles */
|
||||
|
||||
#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
|
||||
|
||||
/* the following are for SDRAM only*/
|
||||
#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
|
||||
#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
|
||||
#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
|
||||
#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
|
||||
#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
|
||||
#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
|
||||
#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
|
||||
#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
|
||||
#if 0
|
||||
#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
|
||||
#define CONFIG_SYS_EXTROM 1
|
||||
#define CONFIG_SYS_REGDIMM 0
|
||||
|
||||
|
||||
/* memory bank settings*/
|
||||
/*
|
||||
* only bits 20-29 are actually used from these vales to set the
|
||||
* start/end address the upper two bits will be 0, and the lower 20
|
||||
* bits will be set to 0x00000 for a start address, or 0xfffff for an
|
||||
* end address
|
||||
*/
|
||||
#define CONFIG_SYS_BANK0_START 0x00000000
|
||||
#define CONFIG_SYS_BANK0_END (0x4000000 - 1)
|
||||
#define CONFIG_SYS_BANK0_ENABLE 1
|
||||
#define CONFIG_SYS_BANK1_START 0x04000000
|
||||
#define CONFIG_SYS_BANK1_END (0x8000000 - 1)
|
||||
#define CONFIG_SYS_BANK1_ENABLE 1
|
||||
#define CONFIG_SYS_BANK2_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK2_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK2_ENABLE 0
|
||||
#define CONFIG_SYS_BANK3_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK3_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK3_ENABLE 0
|
||||
#define CONFIG_SYS_BANK4_START 0x00000000
|
||||
#define CONFIG_SYS_BANK4_END 0x00000000
|
||||
#define CONFIG_SYS_BANK4_ENABLE 0
|
||||
#define CONFIG_SYS_BANK5_START 0x00000000
|
||||
#define CONFIG_SYS_BANK5_END 0x00000000
|
||||
#define CONFIG_SYS_BANK5_ENABLE 0
|
||||
#define CONFIG_SYS_BANK6_START 0x00000000
|
||||
#define CONFIG_SYS_BANK6_END 0x00000000
|
||||
#define CONFIG_SYS_BANK6_ENABLE 0
|
||||
#define CONFIG_SYS_BANK7_START 0x00000000
|
||||
#define CONFIG_SYS_BANK7_END 0x00000000
|
||||
#define CONFIG_SYS_BANK7_ENABLE 0
|
||||
/*
|
||||
* Memory bank enable bitmask, specifying which of the banks defined above
|
||||
are actually present. MSB is for bank #7, LSB is for bank #0.
|
||||
*/
|
||||
#define CONFIG_SYS_BANK_ENABLE 0x01
|
||||
|
||||
#define CONFIG_SYS_ODCR 0x75 /* configures line driver impedances, */
|
||||
/* see 8240 book for bit definitions */
|
||||
#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
|
||||
/* currently accessed page in memory */
|
||||
/* see 8240 book for details */
|
||||
|
||||
/* SDRAM 0 - 256MB */
|
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
/* stack in DCACHE @ 1GB (no backing mem) */
|
||||
#if defined(USE_DINK32)
|
||||
#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
|
||||
#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
#endif
|
||||
|
||||
/* PCI memory */
|
||||
#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
/* Flash, config addrs, etc */
|
||||
#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/* values according to the manual */
|
||||
|
||||
#define CONFIG_DRAM_50MHZ 1
|
||||
#define CONFIG_SDRAM_50MHZ
|
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -1,253 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004 Arabella Software Ltd.
|
||||
* Yuli Barcohen <yuli@arabellasw.com>
|
||||
*
|
||||
* U-Boot configuration for Embedded Planet EP8248 boards.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MPC8248
|
||||
#define CPU_ID_STR "MPC8248"
|
||||
|
||||
#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
|
||||
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* Select serial console configuration
|
||||
*
|
||||
* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
||||
* for SCC).
|
||||
*/
|
||||
#define CONFIG_CONS_ON_SMC /* Console is on SMC */
|
||||
#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
|
||||
#undef CONFIG_CONS_NONE /* It's not on external UART */
|
||||
#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
|
||||
|
||||
#define CONFIG_SYS_BCSR 0xFA000000
|
||||
|
||||
/* Pass open firmware flat device tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
#define OF_TBCLK (bd->bi_busfreq / 4)
|
||||
#define OF_STDOUT_PATH "/soc/cpm/serial <at> 11a80"
|
||||
|
||||
/* Select ethernet configuration */
|
||||
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* No external Ethernet */
|
||||
|
||||
#define CONFIG_SYS_CPMFCR_RAMTYPE 0
|
||||
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_ETHER_ON_FCC1 1
|
||||
/* - Rx clock is CLK10
|
||||
* - Tx clock is CLK11
|
||||
* - BDs/buffers on 60x bus
|
||||
* - Full duplex
|
||||
*/
|
||||
#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
|
||||
#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
|
||||
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_ETHER_ON_FCC2 1
|
||||
/* - Rx clock is CLK13
|
||||
* - Tx clock is CLK14
|
||||
* - BDs/buffers on 60x bus
|
||||
* - Full duplex
|
||||
*/
|
||||
#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
||||
#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
|
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications
|
||||
*/
|
||||
#define MDIO_PORT 0 /* Not used - implemented in BCSR */
|
||||
|
||||
#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
|
||||
#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
|
||||
#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
|
||||
|
||||
#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
|
||||
else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
|
||||
|
||||
#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
|
||||
else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
|
||||
|
||||
#define MIIDELAY udelay(1)
|
||||
|
||||
#ifndef CONFIG_8260_CLKIN
|
||||
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ECHO
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IMMAP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
|
||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
|
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
|
||||
#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
|
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFF800000
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
|
||||
|
||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP
|
||||
|
||||
#if defined(CONFIG_CMD_JFFS2)
|
||||
#define CONFIG_SYS_JFFS2_FIRST_BANK 0
|
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
|
||||
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
|
||||
#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
|
||||
#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
|
||||
#define CONFIG_SYS_JFFS_CUSTOM_PART
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_I2C)
|
||||
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#endif /* CONFIG_ENV_IS_IN_FLASH */
|
||||
|
||||
#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
|
||||
|
||||
#define CONFIG_SYS_IMMR 0xF0000000
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/* Hard reset configuration word */
|
||||
#define CONFIG_SYS_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
|
||||
/* No slaves */
|
||||
#define CONFIG_SYS_HRCW_SLAVE1 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE2 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE3 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE4 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE5 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE6 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE7 0
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT 0
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
|
||||
|
||||
#define CONFIG_SYS_HID2 0
|
||||
|
||||
#define CONFIG_SYS_SIUMCR 0x01240200
|
||||
#define CONFIG_SYS_SYPCR 0xFFFF0683
|
||||
#define CONFIG_SYS_BCR 0x00000000
|
||||
#define CONFIG_SYS_SCCR SCCR_DFBRG01
|
||||
|
||||
#define CONFIG_SYS_RMR RMR_CSRE
|
||||
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
#define CONFIG_SYS_RCCR 0
|
||||
|
||||
#define CONFIG_SYS_MPTPR 0x1300
|
||||
#define CONFIG_SYS_PSDMR 0x82672522
|
||||
#define CONFIG_SYS_PSRT 0x4B
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00001841)
|
||||
#define CONFIG_SYS_SDRAM_OR 0xFF0030C0
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xFF8008C2
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xFFF00864
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -192,7 +192,6 @@
|
||||
#define CONFIG_USB_ETH_CDC
|
||||
#define CONFIG_NETCONSOLE
|
||||
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
|
||||
#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200
|
||||
|
||||
/* Framebuffer and LCD */
|
||||
#define CONFIG_VIDEO
|
||||
|
||||
@@ -19,6 +19,8 @@
|
||||
#define CONFIG_MPC8313
|
||||
#define CONFIG_IDS8313
|
||||
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
|
||||
#define CONFIG_FSL_ELBC
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
@@ -576,11 +578,11 @@
|
||||
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_SIGNATURE
|
||||
#define CONFIG_IMAGE_FORMAT_LEGACY
|
||||
#define CONFIG_CMD_FDT
|
||||
#define CONFIG_CMD_HASH
|
||||
#define CONFIG_RSA
|
||||
#define CONFIG_SHA1
|
||||
#define CONFIG_SHA256
|
||||
#define CONFIG_OF_CONTROL
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
@@ -62,8 +62,7 @@
|
||||
* Commands additional to the ones defined in amcc-common.h
|
||||
*/
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_FPGA
|
||||
#define CONFIG_CMD_FPGA_LOADMK
|
||||
#define CONFIG_CMD_FPGAD
|
||||
#undef CONFIG_CMD_EEPROM
|
||||
|
||||
/*
|
||||
|
||||
@@ -1,251 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Sangmoon Kim, dogoil@etinsys.com.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MPC8245 1
|
||||
#define CONFIG_KVME080 1
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
#define CONFIG_IPADDR 192.168.0.2
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_SERVERIP 192.168.0.1
|
||||
|
||||
#define CONFIG_BOOTARGS \
|
||||
"console=ttyS0,115200 " \
|
||||
"root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
|
||||
"ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
|
||||
"kvme080:eth0:none " \
|
||||
"mtdparts=phys_mapped_flash:12m(root),-(kernel)"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"tftp 800000 kvme080/uImage; " \
|
||||
"bootm 800000"
|
||||
|
||||
#define CONFIG_LOADADDR 800000
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
#undef CONFIG_WATCHDOG
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_RTC_DS164x
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_SNTP
|
||||
|
||||
|
||||
#define CONFIG_NETCONSOLE
|
||||
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00400000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x07C00000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0x7C000000
|
||||
#define CONFIG_SYS_EUMB_ADDR 0xFC000000
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFF000000
|
||||
#define CONFIG_SYS_NS16550_COM1 0xFF080000
|
||||
#define CONFIG_SYS_NS16550_COM2 0xFF080010
|
||||
#define CONFIG_SYS_NS16550_COM3 0xFF080020
|
||||
#define CONFIG_SYS_NS16550_COM4 0xFF080030
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
|
||||
|
||||
#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
|
||||
#define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024)
|
||||
#define CONFIG_SYS_NVRAM_SIZE 0x7FFF8
|
||||
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x00040000
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
|
||||
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
#define CONFIG_SYS_FLASH_PROTECTION
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_PROTECT_CLEAR
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
|
||||
|
||||
#define CONFIG_SYS_JFFS2_FIRST_BANK 0
|
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
|
||||
|
||||
#define CONFIG_ENV_IS_IN_NVRAM 1
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
|
||||
#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
|
||||
#define CONFIG_ENV_SIZE 0x400
|
||||
#define CONFIG_ENV_OFFSET 0
|
||||
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK 14745600
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
#define CONFIG_PCI_PNP
|
||||
|
||||
#define CONFIG_EEPRO100
|
||||
#define CONFIG_EEPRO100_SROM_WRITE
|
||||
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 8
|
||||
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_DLL_EXTEND 0x00
|
||||
#define CONFIG_SYS_PCI_HOLD_DEL 0x20
|
||||
|
||||
#define CONFIG_SYS_ROMNAL 15
|
||||
#define CONFIG_SYS_ROMFAL 31
|
||||
|
||||
#define CONFIG_SYS_REFINT 430
|
||||
|
||||
#define CONFIG_SYS_DBUS_SIZE2 1
|
||||
|
||||
#define CONFIG_SYS_BSTOPRE 121
|
||||
#define CONFIG_SYS_REFREC 8
|
||||
#define CONFIG_SYS_RDLAT 4
|
||||
#define CONFIG_SYS_PRETOACT 3
|
||||
#define CONFIG_SYS_ACTTOPRE 5
|
||||
#define CONFIG_SYS_ACTORW 3
|
||||
#define CONFIG_SYS_SDMODE_CAS_LAT 3
|
||||
#define CONFIG_SYS_SDMODE_WRAP 0
|
||||
|
||||
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
|
||||
#define CONFIG_SYS_EXTROM 1
|
||||
#define CONFIG_SYS_REGDIMM 0
|
||||
|
||||
#define CONFIG_SYS_BANK0_START 0x00000000
|
||||
#define CONFIG_SYS_BANK0_END (0x4000000 - 1)
|
||||
#define CONFIG_SYS_BANK0_ENABLE 1
|
||||
#define CONFIG_SYS_BANK1_START 0x04000000
|
||||
#define CONFIG_SYS_BANK1_END (0x8000000 - 1)
|
||||
#define CONFIG_SYS_BANK1_ENABLE 1
|
||||
#define CONFIG_SYS_BANK2_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK2_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK2_ENABLE 0
|
||||
#define CONFIG_SYS_BANK3_START 0x3ff00000
|
||||
#define CONFIG_SYS_BANK3_END 0x3fffffff
|
||||
#define CONFIG_SYS_BANK3_ENABLE 0
|
||||
#define CONFIG_SYS_BANK4_START 0x00000000
|
||||
#define CONFIG_SYS_BANK4_END 0x00000000
|
||||
#define CONFIG_SYS_BANK4_ENABLE 0
|
||||
#define CONFIG_SYS_BANK5_START 0x00000000
|
||||
#define CONFIG_SYS_BANK5_END 0x00000000
|
||||
#define CONFIG_SYS_BANK5_ENABLE 0
|
||||
#define CONFIG_SYS_BANK6_START 0x00000000
|
||||
#define CONFIG_SYS_BANK6_END 0x00000000
|
||||
#define CONFIG_SYS_BANK6_ENABLE 0
|
||||
#define CONFIG_SYS_BANK7_START 0x00000000
|
||||
#define CONFIG_SYS_BANK7_END 0x00000000
|
||||
#define CONFIG_SYS_BANK7_ENABLE 0
|
||||
|
||||
#define CONFIG_SYS_BANK_ENABLE 0x03
|
||||
|
||||
#define CONFIG_SYS_ODCR 0x75
|
||||
#define CONFIG_SYS_PGMAX 0x32
|
||||
|
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -1,281 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2008
|
||||
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* quad100hd.h - configuration for Quad100hd board
|
||||
***********************************************************************/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */
|
||||
#define CONFIG_405EP 1 /* Specifc 405EP support*/
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
|
||||
#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */
|
||||
#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */
|
||||
|
||||
/* the environment is in the EEPROM by default */
|
||||
#define CONFIG_ENV_IS_IN_EEPROM
|
||||
#undef CONFIG_ENV_IS_IN_FLASH
|
||||
|
||||
#define CONFIG_PPC4xx_EMAC
|
||||
#define CONFIG_HAS_ETH1 1
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0x01 /* PHY address */
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
|
||||
#define CONFIG_PHY_RESET 1
|
||||
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_ASKENV
|
||||
#undef CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#undef CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#undef CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_I2C
|
||||
#undef CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#undef CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NAND
|
||||
#undef CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
/*
|
||||
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
|
||||
*/
|
||||
#define CONFIG_SDRAM_BANK0 1
|
||||
|
||||
/* FIX! SDRAM timings used in datasheet */
|
||||
#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
|
||||
#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
|
||||
#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
|
||||
#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
|
||||
#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
|
||||
|
||||
/*
|
||||
* JFFS2
|
||||
*/
|
||||
#define CONFIG_SYS_JFFS2_FIRST_BANK 0
|
||||
#ifdef CONFIG_SYS_KERNEL_IN_JFFS2
|
||||
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */
|
||||
#else /* kernel not in JFFS */
|
||||
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */
|
||||
#endif
|
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
|
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
|
||||
#define CONFIG_SYS_BASE_BAUD 691200
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* The following table includes the supported baudrates */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_PPC4XX
|
||||
#define CONFIG_SYS_I2C_PPC4XX_CH0
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */
|
||||
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
#define CONFIG_SYS_EEPROM_SIZE 0x2000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFFC00000
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
|
||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE)
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
|
||||
/* the environment is located before u-boot */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_EEPROM
|
||||
#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars */
|
||||
#define CONFIG_ENV_OFFSET 0x00000000
|
||||
#define CONFIG_SYS_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */
|
||||
#endif
|
||||
|
||||
/* partly from PPCBoot */
|
||||
/* NAND */
|
||||
#define CONFIG_NAND
|
||||
#ifdef CONFIG_NAND
|
||||
#define CONFIG_SYS_NAND_BASE 0x60000000
|
||||
#define CONFIG_SYS_NAND_CS 10 /* our CS is GPIO10 */
|
||||
#define CONFIG_SYS_NAND_RDY 23 /* our RDY is GPIO23 */
|
||||
#define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */
|
||||
#define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */
|
||||
#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache)
|
||||
*/
|
||||
/* use on chip memory (OCM) for temperary stack until sdram is tested */
|
||||
/* see ./arch/powerpc/cpu/ppc4xx/start.S */
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
|
||||
/* On Chip Memory location */
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
|
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
* Taken from PPCBoot board/icecube/icecube.h
|
||||
*/
|
||||
|
||||
/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x04002480
|
||||
/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
|
||||
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
|
||||
#define CONFIG_SYS_EBC_PB1AP 0x04005480
|
||||
#define CONFIG_SYS_EBC_PB1CR 0x60018000
|
||||
#define CONFIG_SYS_EBC_PB2AP 0x00000000
|
||||
#define CONFIG_SYS_EBC_PB2CR 0x00000000
|
||||
#define CONFIG_SYS_EBC_PB3AP 0x00000000
|
||||
#define CONFIG_SYS_EBC_PB3CR 0x00000000
|
||||
#define CONFIG_SYS_EBC_PB4AP 0x00000000
|
||||
#define CONFIG_SYS_EBC_PB4CR 0x00000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup (PPC405EP specific)
|
||||
*
|
||||
* Taken in part from PPCBoot board/icecube/icecube.h
|
||||
*/
|
||||
/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
|
||||
#define CONFIG_SYS_GPIO0_OSRL 0x55555550
|
||||
#define CONFIG_SYS_GPIO0_OSRH 0x00000110
|
||||
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
|
||||
#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
|
||||
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
|
||||
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
|
||||
#define CONFIG_SYS_GPIO0_TCR 0xFFFF8097
|
||||
#define CONFIG_SYS_GPIO0_ODR 0x00000000
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#endif
|
||||
|
||||
/* ENVIRONMENT VARS */
|
||||
|
||||
#define CONFIG_IPADDR 192.168.1.67
|
||||
#define CONFIG_SERVERIP 192.168.1.50
|
||||
#define CONFIG_GATEWAYIP 192.168.1.1
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_LOADADDR 300000
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -16,6 +16,9 @@
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_IO_TRACE
|
||||
#define CONFIG_CMD_IOTRACE
|
||||
|
||||
#define CONFIG_SYS_TIMER_RATE 1000000
|
||||
|
||||
#define CONFIG_BOOTSTAGE
|
||||
@@ -41,6 +44,7 @@
|
||||
#define CONFIG_RSA
|
||||
#define CONFIG_CMD_FDT
|
||||
#define CONFIG_DEFAULT_DEVICE_TREE sandbox
|
||||
#define CONFIG_ANDROID_BOOT_IMAGE
|
||||
|
||||
#define CONFIG_FS_FAT
|
||||
#define CONFIG_FS_EXT4
|
||||
|
||||
123
include/configs/tb100.h
Normal file
123
include/configs/tb100.h
Normal file
@@ -0,0 +1,123 @@
|
||||
/*
|
||||
* Copyright (C) 2011-2014 Pierrick Hascoet, Abilis Systems
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_TB100_H_
|
||||
#define _CONFIG_TB100_H_
|
||||
|
||||
#include <linux/sizes.h>
|
||||
|
||||
/*
|
||||
* CPU configuration
|
||||
*/
|
||||
#define CONFIG_ARC700
|
||||
#define CONFIG_ARC_MMU_VER 3
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
#define CONFIG_SYS_CLK_FREQ 500000000
|
||||
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
|
||||
|
||||
/*
|
||||
* Board configuration
|
||||
*/
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_ARCH_EARLY_INIT_R
|
||||
|
||||
/*
|
||||
* Memory configuration
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x84000000
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
#define CONFIG_SYS_SDRAM_SIZE SZ_128M
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN SZ_128K
|
||||
#define CONFIG_SYS_BOOTM_LEN SZ_32M
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x82000000
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
/*
|
||||
* UART configuration
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4
|
||||
#define CONFIG_SYS_NS16550_CLK 166666666
|
||||
#define CONFIG_SYS_NS16550_COM1 0xFF100000
|
||||
#define CONFIG_SYS_NS16550_MEM32
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/*
|
||||
* Ethernet PHY configuration
|
||||
*/
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_GIGE
|
||||
|
||||
/*
|
||||
* Even though the board houses Realtek RTL8211E PHY
|
||||
* corresponding PHY driver (drivers/net/phy/realtek.c) behaves unexpectedly.
|
||||
* In particular "parse_status" reports link is down.
|
||||
*
|
||||
* Until Realtek PHY driver is fixed fall back to generic PHY driver
|
||||
* which implements all required functionality and behaves much more stable.
|
||||
*
|
||||
* #define CONFIG_PHY_REALTEK
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_DESIGNWARE_ETH
|
||||
#define ETH0_BASE_ADDRESS 0xFE100000
|
||||
#define ETH1_BASE_ADDRESS 0xFE110000
|
||||
|
||||
/*
|
||||
* Command line configuration
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#define CONFIG_ENV_SIZE SZ_2K
|
||||
#define CONFIG_ENV_OFFSET 0
|
||||
|
||||
/*
|
||||
* Environment configuration
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200n8"
|
||||
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
|
||||
|
||||
/*
|
||||
* Console configuration
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_PROMPT "[tb100]:~# "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
#endif /* _CONFIG_TB100_H_ */
|
||||
@@ -19,6 +19,9 @@
|
||||
|
||||
#include <asm/arch/tegra.h> /* get chip and board defs */
|
||||
|
||||
#define CONFIG_DM
|
||||
#define CONFIG_CMD_DM
|
||||
|
||||
#define CONFIG_SYS_TIMER_RATE 1000000
|
||||
#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
|
||||
|
||||
|
||||
@@ -127,7 +127,7 @@
|
||||
* we are on so we do not need to rely on the command prompt. We set a
|
||||
* console baudrate of 115200 and use the default baud rate table.
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 << 20)
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT "U-Boot# "
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
|
||||
@@ -225,6 +225,7 @@
|
||||
/* FIT support */
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
|
||||
#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
|
||||
|
||||
/* FDT support */
|
||||
#define CONFIG_OF_CONTROL
|
||||
|
||||
@@ -23,14 +23,14 @@ struct dm_demo_pdata {
|
||||
};
|
||||
|
||||
struct demo_ops {
|
||||
int (*hello)(struct device *dev, int ch);
|
||||
int (*status)(struct device *dev, int *status);
|
||||
int (*hello)(struct udevice *dev, int ch);
|
||||
int (*status)(struct udevice *dev, int *status);
|
||||
};
|
||||
|
||||
int demo_hello(struct device *dev, int ch);
|
||||
int demo_status(struct device *dev, int *status);
|
||||
int demo_hello(struct udevice *dev, int ch);
|
||||
int demo_status(struct udevice *dev, int *status);
|
||||
int demo_list(void);
|
||||
|
||||
int demo_parse_dt(struct device *dev);
|
||||
int demo_parse_dt(struct udevice *dev);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
*/
|
||||
|
||||
#ifndef _DM_H_
|
||||
#define _DM_H
|
||||
#define _DM_H_
|
||||
|
||||
#include <dm/device.h>
|
||||
#include <dm/platdata.h>
|
||||
|
||||
@@ -11,7 +11,7 @@
|
||||
#ifndef _DM_DEVICE_INTERNAL_H
|
||||
#define _DM_DEVICE_INTERNAL_H
|
||||
|
||||
struct device;
|
||||
struct udevice;
|
||||
|
||||
/**
|
||||
* device_bind() - Create a device and bind it to a driver
|
||||
@@ -34,9 +34,9 @@ struct device;
|
||||
* @devp: Returns a pointer to the bound device
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int device_bind(struct device *parent, struct driver *drv,
|
||||
int device_bind(struct udevice *parent, struct driver *drv,
|
||||
const char *name, void *platdata, int of_offset,
|
||||
struct device **devp);
|
||||
struct udevice **devp);
|
||||
|
||||
/**
|
||||
* device_bind_by_name: Create a device and bind it to a driver
|
||||
@@ -49,8 +49,8 @@ int device_bind(struct device *parent, struct driver *drv,
|
||||
* @devp: Returns a pointer to the bound device
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int device_bind_by_name(struct device *parent, const struct driver_info *info,
|
||||
struct device **devp);
|
||||
int device_bind_by_name(struct udevice *parent, const struct driver_info *info,
|
||||
struct udevice **devp);
|
||||
|
||||
/**
|
||||
* device_probe() - Probe a device, activating it
|
||||
@@ -61,7 +61,7 @@ int device_bind_by_name(struct device *parent, const struct driver_info *info,
|
||||
* @dev: Pointer to device to probe
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int device_probe(struct device *dev);
|
||||
int device_probe(struct udevice *dev);
|
||||
|
||||
/**
|
||||
* device_remove() - Remove a device, de-activating it
|
||||
@@ -72,7 +72,7 @@ int device_probe(struct device *dev);
|
||||
* @dev: Pointer to device to remove
|
||||
* @return 0 if OK, -ve on error (an error here is normally a very bad thing)
|
||||
*/
|
||||
int device_remove(struct device *dev);
|
||||
int device_remove(struct udevice *dev);
|
||||
|
||||
/**
|
||||
* device_unbind() - Unbind a device, destroying it
|
||||
@@ -82,6 +82,10 @@ int device_remove(struct device *dev);
|
||||
* @dev: Pointer to device to unbind
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int device_unbind(struct device *dev);
|
||||
int device_unbind(struct udevice *dev);
|
||||
|
||||
/* Cast away any volatile pointer */
|
||||
#define DM_ROOT_NON_CONST (((gd_t *)gd)->dm_root)
|
||||
#define DM_UCLASS_ROOT_NON_CONST (((gd_t *)gd)->uclass_root)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -21,10 +21,10 @@ struct driver_info;
|
||||
#define DM_FLAG_ACTIVATED (1 << 0)
|
||||
|
||||
/* DM is responsible for allocating and freeing platdata */
|
||||
#define DM_FLAG_ALLOC_PDATA (2 << 0)
|
||||
#define DM_FLAG_ALLOC_PDATA (1 << 1)
|
||||
|
||||
/**
|
||||
* struct device - An instance of a driver
|
||||
* struct udevice - An instance of a driver
|
||||
*
|
||||
* This holds information about a device, which is a driver bound to a
|
||||
* particular port or peripheral (essentially a driver instance).
|
||||
@@ -53,12 +53,12 @@ struct driver_info;
|
||||
* @sibling_node: Next device in list of all devices
|
||||
* @flags: Flags for this device DM_FLAG_...
|
||||
*/
|
||||
struct device {
|
||||
struct udevice {
|
||||
struct driver *driver;
|
||||
const char *name;
|
||||
void *platdata;
|
||||
int of_offset;
|
||||
struct device *parent;
|
||||
struct udevice *parent;
|
||||
void *priv;
|
||||
struct uclass *uclass;
|
||||
void *uclass_priv;
|
||||
@@ -75,11 +75,11 @@ struct device {
|
||||
#define device_active(dev) ((dev)->flags & DM_FLAG_ACTIVATED)
|
||||
|
||||
/**
|
||||
* struct device_id - Lists the compatible strings supported by a driver
|
||||
* struct udevice_id - Lists the compatible strings supported by a driver
|
||||
* @compatible: Compatible string
|
||||
* @data: Data for this compatible string
|
||||
*/
|
||||
struct device_id {
|
||||
struct udevice_id {
|
||||
const char *compatible;
|
||||
ulong data;
|
||||
};
|
||||
@@ -121,12 +121,12 @@ struct device_id {
|
||||
struct driver {
|
||||
char *name;
|
||||
enum uclass_id id;
|
||||
const struct device_id *of_match;
|
||||
int (*bind)(struct device *dev);
|
||||
int (*probe)(struct device *dev);
|
||||
int (*remove)(struct device *dev);
|
||||
int (*unbind)(struct device *dev);
|
||||
int (*ofdata_to_platdata)(struct device *dev);
|
||||
const struct udevice_id *of_match;
|
||||
int (*bind)(struct udevice *dev);
|
||||
int (*probe)(struct udevice *dev);
|
||||
int (*remove)(struct udevice *dev);
|
||||
int (*unbind)(struct udevice *dev);
|
||||
int (*ofdata_to_platdata)(struct udevice *dev);
|
||||
int priv_auto_alloc_size;
|
||||
int platdata_auto_alloc_size;
|
||||
const void *ops; /* driver-specific operations */
|
||||
@@ -144,7 +144,7 @@ struct driver {
|
||||
* @dev Device to check
|
||||
* @return platform data, or NULL if none
|
||||
*/
|
||||
void *dev_get_platdata(struct device *dev);
|
||||
void *dev_get_platdata(struct udevice *dev);
|
||||
|
||||
/**
|
||||
* dev_get_priv() - Get the private data for a device
|
||||
@@ -154,6 +154,6 @@ void *dev_get_platdata(struct device *dev);
|
||||
* @dev Device to check
|
||||
* @return private data, or NULL if none
|
||||
*/
|
||||
void *dev_get_priv(struct device *dev);
|
||||
void *dev_get_priv(struct udevice *dev);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -32,8 +32,28 @@ struct driver *lists_driver_lookup_name(const char *name);
|
||||
*/
|
||||
struct uclass_driver *lists_uclass_lookup(enum uclass_id id);
|
||||
|
||||
int lists_bind_drivers(struct device *parent);
|
||||
/**
|
||||
* lists_bind_drivers() - search for and bind all drivers to parent
|
||||
*
|
||||
* This searches the U_BOOT_DEVICE() structures and creates new devices for
|
||||
* each one. The devices will have @parent as their parent.
|
||||
*
|
||||
* @parent: parent driver (root)
|
||||
* @early_only: If true, bind only drivers with the DM_INIT_F flag. If false
|
||||
* bind all drivers.
|
||||
*/
|
||||
int lists_bind_drivers(struct udevice *parent);
|
||||
|
||||
int lists_bind_fdt(struct device *parent, const void *blob, int offset);
|
||||
/**
|
||||
* lists_bind_fdt() - bind a device tree node
|
||||
*
|
||||
* This creates a new device bound to the given device tree node, with
|
||||
* @parent as its parent.
|
||||
*
|
||||
* @parent: parent driver (root)
|
||||
* @blob: device tree blob
|
||||
* @offset: offset of this device tree node
|
||||
*/
|
||||
int lists_bind_fdt(struct udevice *parent, const void *blob, int offset);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -10,7 +10,7 @@
|
||||
#ifndef _DM_ROOT_H_
|
||||
#define _DM_ROOT_H_
|
||||
|
||||
struct device;
|
||||
struct udevice;
|
||||
|
||||
/**
|
||||
* dm_root() - Return pointer to the top of the driver tree
|
||||
@@ -19,7 +19,7 @@ struct device;
|
||||
*
|
||||
* @return pointer to root device, or NULL if not inited yet
|
||||
*/
|
||||
struct device *dm_root(void);
|
||||
struct udevice *dm_root(void);
|
||||
|
||||
/**
|
||||
* dm_scan_platdata() - Scan all platform data and bind drivers
|
||||
@@ -41,7 +41,7 @@ int dm_scan_platdata(void);
|
||||
int dm_scan_fdt(const void *blob);
|
||||
|
||||
/**
|
||||
* dm_init() - Initialize Driver Model structures
|
||||
* dm_init() - Initialise Driver Model structures
|
||||
*
|
||||
* This function will initialize roots of driver tree and class tree.
|
||||
* This needs to be called before anything uses the DM
|
||||
|
||||
@@ -30,7 +30,7 @@ struct dm_test_pdata {
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
struct test_ops {
|
||||
int (*ping)(struct device *dev, int pingval, int *pingret);
|
||||
int (*ping)(struct udevice *dev, int pingval, int *pingret);
|
||||
};
|
||||
|
||||
/* Operations that our test driver supports */
|
||||
@@ -102,8 +102,8 @@ extern struct dm_test_state global_test_state;
|
||||
* @skip_post_probe: Skip uclass post-probe processing
|
||||
*/
|
||||
struct dm_test_state {
|
||||
struct device *root;
|
||||
struct device *testdev;
|
||||
struct udevice *root;
|
||||
struct udevice *testdev;
|
||||
int fail_count;
|
||||
int force_fail_alloc;
|
||||
int skip_post_probe;
|
||||
@@ -138,8 +138,8 @@ struct dm_test {
|
||||
}
|
||||
|
||||
/* Declare ping methods for the drivers */
|
||||
int test_ping(struct device *dev, int pingval, int *pingret);
|
||||
int testfdt_ping(struct device *dev, int pingval, int *pingret);
|
||||
int test_ping(struct udevice *dev, int pingval, int *pingret);
|
||||
int testfdt_ping(struct udevice *dev, int pingval, int *pingret);
|
||||
|
||||
/**
|
||||
* dm_check_operations() - Check that we can perform ping operations
|
||||
@@ -152,7 +152,7 @@ int testfdt_ping(struct device *dev, int pingval, int *pingret);
|
||||
* @priv: Pointer to private test information
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int dm_check_operations(struct dm_test_state *dms, struct device *dev,
|
||||
int dm_check_operations(struct dm_test_state *dms, struct udevice *dev,
|
||||
uint32_t base, struct dm_test_priv *priv);
|
||||
|
||||
/**
|
||||
|
||||
@@ -21,7 +21,7 @@
|
||||
* @return the uclass pointer of a child at the given index or
|
||||
* return NULL on error.
|
||||
*/
|
||||
int uclass_find_device(enum uclass_id id, int index, struct device **devp);
|
||||
int uclass_find_device(enum uclass_id id, int index, struct udevice **devp);
|
||||
|
||||
/**
|
||||
* uclass_bind_device() - Associate device with a uclass
|
||||
@@ -31,7 +31,7 @@ int uclass_find_device(enum uclass_id id, int index, struct device **devp);
|
||||
* @dev: Pointer to the device
|
||||
* #return 0 on success, -ve on error
|
||||
*/
|
||||
int uclass_bind_device(struct device *dev);
|
||||
int uclass_bind_device(struct udevice *dev);
|
||||
|
||||
/**
|
||||
* uclass_unbind_device() - Deassociate device with a uclass
|
||||
@@ -41,7 +41,7 @@ int uclass_bind_device(struct device *dev);
|
||||
* @dev: Pointer to the device
|
||||
* #return 0 on success, -ve on error
|
||||
*/
|
||||
int uclass_unbind_device(struct device *dev);
|
||||
int uclass_unbind_device(struct udevice *dev);
|
||||
|
||||
/**
|
||||
* uclass_post_probe_device() - Deal with a device that has just been probed
|
||||
@@ -52,7 +52,7 @@ int uclass_unbind_device(struct device *dev);
|
||||
* @dev: Pointer to the device
|
||||
* #return 0 on success, -ve on error
|
||||
*/
|
||||
int uclass_post_probe_device(struct device *dev);
|
||||
int uclass_post_probe_device(struct udevice *dev);
|
||||
|
||||
/**
|
||||
* uclass_pre_remove_device() - Handle a device which is about to be removed
|
||||
@@ -62,7 +62,7 @@ int uclass_post_probe_device(struct device *dev);
|
||||
* @dev: Pointer to the device
|
||||
* #return 0 on success, -ve on error
|
||||
*/
|
||||
int uclass_pre_remove_device(struct device *dev);
|
||||
int uclass_pre_remove_device(struct udevice *dev);
|
||||
|
||||
/**
|
||||
* uclass_find() - Find uclass by its id
|
||||
|
||||
@@ -26,7 +26,7 @@
|
||||
* @priv: Private data for this uclass
|
||||
* @uc_drv: The driver for the uclass itself, not to be confused with a
|
||||
* 'struct driver'
|
||||
* dev_head: List of devices in this uclass (devices are attached to their
|
||||
* @dev_head: List of devices in this uclass (devices are attached to their
|
||||
* uclass when their bind method is called)
|
||||
* @sibling_node: Next uclass in the linked list of uclasses
|
||||
*/
|
||||
@@ -37,7 +37,7 @@ struct uclass {
|
||||
struct list_head sibling_node;
|
||||
};
|
||||
|
||||
struct device;
|
||||
struct udevice;
|
||||
|
||||
/**
|
||||
* struct uclass_driver - Driver for the uclass
|
||||
@@ -65,10 +65,10 @@ struct device;
|
||||
struct uclass_driver {
|
||||
const char *name;
|
||||
enum uclass_id id;
|
||||
int (*post_bind)(struct device *dev);
|
||||
int (*pre_unbind)(struct device *dev);
|
||||
int (*post_probe)(struct device *dev);
|
||||
int (*pre_remove)(struct device *dev);
|
||||
int (*post_bind)(struct udevice *dev);
|
||||
int (*pre_unbind)(struct udevice *dev);
|
||||
int (*post_probe)(struct udevice *dev);
|
||||
int (*pre_remove)(struct udevice *dev);
|
||||
int (*init)(struct uclass *class);
|
||||
int (*destroy)(struct uclass *class);
|
||||
int priv_auto_alloc_size;
|
||||
@@ -96,12 +96,14 @@ int uclass_get(enum uclass_id key, struct uclass **ucp);
|
||||
/**
|
||||
* uclass_get_device() - Get a uclass device based on an ID and index
|
||||
*
|
||||
* The device is probed to activate it ready for use.
|
||||
*
|
||||
* id: ID to look up
|
||||
* @index: Device number within that uclass (0=first)
|
||||
* @ucp: Returns pointer to uclass (there is only one per for each ID)
|
||||
* @devp: Returns pointer to device (there is only one per for each ID)
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int uclass_get_device(enum uclass_id id, int index, struct device **ucp);
|
||||
int uclass_get_device(enum uclass_id id, int index, struct udevice **devp);
|
||||
|
||||
/**
|
||||
* uclass_first_device() - Get the first device in a uclass
|
||||
@@ -110,7 +112,7 @@ int uclass_get_device(enum uclass_id id, int index, struct device **ucp);
|
||||
* @devp: Returns pointer to the first device in that uclass, or NULL if none
|
||||
* @return 0 if OK (found or not found), -1 on error
|
||||
*/
|
||||
int uclass_first_device(enum uclass_id id, struct device **devp);
|
||||
int uclass_first_device(enum uclass_id id, struct udevice **devp);
|
||||
|
||||
/**
|
||||
* uclass_next_device() - Get the next device in a uclass
|
||||
@@ -119,7 +121,7 @@ int uclass_first_device(enum uclass_id id, struct device **devp);
|
||||
* to the next device in the same uclass, or NULL if none
|
||||
* @return 0 if OK (found or not found), -1 on error
|
||||
*/
|
||||
int uclass_next_device(struct device **devp);
|
||||
int uclass_next_device(struct udevice **devp);
|
||||
|
||||
/**
|
||||
* uclass_foreach_dev() - Helper function to iteration through devices
|
||||
@@ -127,9 +129,9 @@ int uclass_next_device(struct device **devp);
|
||||
* This creates a for() loop which works through the available devices in
|
||||
* a uclass in order from start to end.
|
||||
*
|
||||
* @pos: struct device * to hold the current device. Set to NULL when there
|
||||
* @pos: struct udevice * to hold the current device. Set to NULL when there
|
||||
* are no more devices.
|
||||
* uc: uclass to scan
|
||||
* @uc: uclass to scan
|
||||
*/
|
||||
#define uclass_foreach_dev(pos, uc) \
|
||||
for (pos = list_entry((&(uc)->dev_head)->next, typeof(*pos), \
|
||||
|
||||
15
include/dt-bindings/gpio/gpio.h
Normal file
15
include/dt-bindings/gpio/gpio.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* This header provides constants for most GPIO bindings.
|
||||
*
|
||||
* Most GPIO bindings include a flags cell as part of the GPIO specifier.
|
||||
* In most cases, the format of the flags cell uses the standard values
|
||||
* defined in this header.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_GPIO_GPIO_H
|
||||
#define _DT_BINDINGS_GPIO_GPIO_H
|
||||
|
||||
#define GPIO_ACTIVE_HIGH 0
|
||||
#define GPIO_ACTIVE_LOW 1
|
||||
|
||||
#endif
|
||||
51
include/dt-bindings/gpio/tegra-gpio.h
Normal file
51
include/dt-bindings/gpio/tegra-gpio.h
Normal file
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
* This header provides constants for binding nvidia,tegra*-gpio.
|
||||
*
|
||||
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
|
||||
* provide names for this.
|
||||
*
|
||||
* The second cell contains standard flag values specified in gpio.h.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
|
||||
#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#define TEGRA_GPIO_BANK_ID_A 0
|
||||
#define TEGRA_GPIO_BANK_ID_B 1
|
||||
#define TEGRA_GPIO_BANK_ID_C 2
|
||||
#define TEGRA_GPIO_BANK_ID_D 3
|
||||
#define TEGRA_GPIO_BANK_ID_E 4
|
||||
#define TEGRA_GPIO_BANK_ID_F 5
|
||||
#define TEGRA_GPIO_BANK_ID_G 6
|
||||
#define TEGRA_GPIO_BANK_ID_H 7
|
||||
#define TEGRA_GPIO_BANK_ID_I 8
|
||||
#define TEGRA_GPIO_BANK_ID_J 9
|
||||
#define TEGRA_GPIO_BANK_ID_K 10
|
||||
#define TEGRA_GPIO_BANK_ID_L 11
|
||||
#define TEGRA_GPIO_BANK_ID_M 12
|
||||
#define TEGRA_GPIO_BANK_ID_N 13
|
||||
#define TEGRA_GPIO_BANK_ID_O 14
|
||||
#define TEGRA_GPIO_BANK_ID_P 15
|
||||
#define TEGRA_GPIO_BANK_ID_Q 16
|
||||
#define TEGRA_GPIO_BANK_ID_R 17
|
||||
#define TEGRA_GPIO_BANK_ID_S 18
|
||||
#define TEGRA_GPIO_BANK_ID_T 19
|
||||
#define TEGRA_GPIO_BANK_ID_U 20
|
||||
#define TEGRA_GPIO_BANK_ID_V 21
|
||||
#define TEGRA_GPIO_BANK_ID_W 22
|
||||
#define TEGRA_GPIO_BANK_ID_X 23
|
||||
#define TEGRA_GPIO_BANK_ID_Y 24
|
||||
#define TEGRA_GPIO_BANK_ID_Z 25
|
||||
#define TEGRA_GPIO_BANK_ID_AA 26
|
||||
#define TEGRA_GPIO_BANK_ID_BB 27
|
||||
#define TEGRA_GPIO_BANK_ID_CC 28
|
||||
#define TEGRA_GPIO_BANK_ID_DD 29
|
||||
#define TEGRA_GPIO_BANK_ID_EE 30
|
||||
#define TEGRA_GPIO_BANK_ID_FF 31
|
||||
|
||||
#define TEGRA_GPIO(bank, offset) \
|
||||
((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
|
||||
|
||||
#endif
|
||||
22
include/dt-bindings/interrupt-controller/arm-gic.h
Normal file
22
include/dt-bindings/interrupt-controller/arm-gic.h
Normal file
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* This header provides constants for the ARM GIC.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
|
||||
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/* interrupt specific cell 0 */
|
||||
|
||||
#define GIC_SPI 0
|
||||
#define GIC_PPI 1
|
||||
|
||||
/*
|
||||
* Interrupt specifier cell 2.
|
||||
* The flaggs in irq.h are valid, plus those below.
|
||||
*/
|
||||
#define GIC_CPU_MASK_RAW(x) ((x) << 8)
|
||||
#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
|
||||
|
||||
#endif
|
||||
19
include/dt-bindings/interrupt-controller/irq.h
Normal file
19
include/dt-bindings/interrupt-controller/irq.h
Normal file
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* This header provides constants for most IRQ bindings.
|
||||
*
|
||||
* Most IRQ bindings include a flags cell as part of the IRQ specifier.
|
||||
* In most cases, the format of the flags cell uses the standard values
|
||||
* defined in this header.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
|
||||
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
|
||||
|
||||
#define IRQ_TYPE_NONE 0
|
||||
#define IRQ_TYPE_EDGE_RISING 1
|
||||
#define IRQ_TYPE_EDGE_FALLING 2
|
||||
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
|
||||
#define IRQ_TYPE_LEVEL_HIGH 4
|
||||
#define IRQ_TYPE_LEVEL_LOW 8
|
||||
|
||||
#endif
|
||||
@@ -18,7 +18,11 @@
|
||||
#define VFAT_MAXSEQ 9 /* Up to 9 of 13 2-byte UTF-16 entries */
|
||||
#define PREFETCH_BLOCKS 2
|
||||
|
||||
#define MAX_CLUSTSIZE 65536
|
||||
#ifndef CONFIG_FS_FAT_MAX_CLUSTSIZE
|
||||
#define CONFIG_FS_FAT_MAX_CLUSTSIZE 65536
|
||||
#endif
|
||||
#define MAX_CLUSTSIZE CONFIG_FS_FAT_MAX_CLUSTSIZE
|
||||
|
||||
#define DIRENTSPERBLOCK (mydata->sect_size / sizeof(dir_entry))
|
||||
#define DIRENTSPERCLUST ((mydata->clust_size * mydata->sect_size) / \
|
||||
sizeof(dir_entry))
|
||||
|
||||
@@ -16,8 +16,8 @@ u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
|
||||
const char *prop, const u32 dflt);
|
||||
u32 fdt_getprop_u32_default(const void *fdt, const char *path,
|
||||
const char *prop, const u32 dflt);
|
||||
int fdt_chosen(void *fdt, int force);
|
||||
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
|
||||
int fdt_chosen(void *fdt);
|
||||
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end);
|
||||
void do_fixup_by_path(void *fdt, const char *path, const char *prop,
|
||||
const void *val, int len, int create);
|
||||
void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
|
||||
|
||||
@@ -6,6 +6,18 @@
|
||||
#ifndef _HASH_H
|
||||
#define _HASH_H
|
||||
|
||||
/*
|
||||
* Maximum digest size for all algorithms we support. Having this value
|
||||
* avoids a malloc() or C99 local declaration in common/cmd_hash.c.
|
||||
*/
|
||||
#define HASH_MAX_DIGEST_SIZE 32
|
||||
|
||||
enum {
|
||||
HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */
|
||||
HASH_FLAG_ENV = 1 << 1, /* Allow env vars */
|
||||
};
|
||||
|
||||
#ifndef USE_HOSTCC
|
||||
#if defined(CONFIG_SHA1SUM_VERIFY) || defined(CONFIG_CRC32_VERIFY)
|
||||
#define CONFIG_HASH_VERIFY
|
||||
#endif
|
||||
@@ -65,17 +77,6 @@ struct hash_algo {
|
||||
int size);
|
||||
};
|
||||
|
||||
/*
|
||||
* Maximum digest size for all algorithms we support. Having this value
|
||||
* avoids a malloc() or C99 local declaration in common/cmd_hash.c.
|
||||
*/
|
||||
#define HASH_MAX_DIGEST_SIZE 32
|
||||
|
||||
enum {
|
||||
HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */
|
||||
HASH_FLAG_ENV = 1 << 1, /* Allow env vars */
|
||||
};
|
||||
|
||||
/**
|
||||
* hash_command: Process a hash command for a particular algorithm
|
||||
*
|
||||
@@ -125,4 +126,20 @@ int hash_block(const char *algo_name, const void *data, unsigned int len,
|
||||
* @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm.
|
||||
*/
|
||||
int hash_lookup_algo(const char *algo_name, struct hash_algo **algop);
|
||||
|
||||
/**
|
||||
* hash_show() - Print out a hash algorithm and value
|
||||
*
|
||||
* You will get a message like this (without a newline at the end):
|
||||
*
|
||||
* "sha1 for 9eb3337c ... 9eb3338f ==> 7942ef1df479fd3130f716eb9613d107dab7e257"
|
||||
*
|
||||
* @algo: Algorithm used for hash
|
||||
* @addr: Address of data that was hashed
|
||||
* @len: Length of data that was hashed
|
||||
* @output: Hash value to display
|
||||
*/
|
||||
void hash_show(struct hash_algo *algo, ulong addr, ulong len,
|
||||
uint8_t *output);
|
||||
#endif /* !USE_HOSTCC */
|
||||
#endif
|
||||
|
||||
@@ -45,6 +45,7 @@ struct lmb;
|
||||
#endif /* USE_HOSTCC */
|
||||
|
||||
#if defined(CONFIG_FIT)
|
||||
#include <hash.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
# ifdef CONFIG_SPL_BUILD
|
||||
@@ -412,7 +413,9 @@ enum fit_load_op {
|
||||
#ifndef USE_HOSTCC
|
||||
/* Image format types, returned by _get_format() routine */
|
||||
#define IMAGE_FORMAT_INVALID 0x00
|
||||
#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
|
||||
#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */
|
||||
#endif
|
||||
#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
|
||||
#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */
|
||||
|
||||
@@ -422,6 +425,7 @@ ulong genimg_get_image(ulong img_addr);
|
||||
|
||||
int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
|
||||
uint8_t arch, ulong *rd_start, ulong *rd_end);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* fit_image_load() - load an image from a FIT
|
||||
@@ -431,8 +435,9 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
|
||||
* out progress messages, checking the type/arch/os and optionally copying it
|
||||
* to the right load address.
|
||||
*
|
||||
* The property to look up is defined by image_type.
|
||||
*
|
||||
* @param images Boot images structure
|
||||
* @param prop_name Property name to look up (FIT_..._PROP)
|
||||
* @param addr Address of FIT in memory
|
||||
* @param fit_unamep On entry this is the requested image name
|
||||
* (e.g. "kernel@1") or NULL to use the default. On exit
|
||||
@@ -450,12 +455,14 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
|
||||
* @param load_op Decribes what to do with the load address
|
||||
* @param datap Returns address of loaded image
|
||||
* @param lenp Returns length of loaded image
|
||||
* @return node offset of image, or -ve error code on error
|
||||
*/
|
||||
int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr,
|
||||
int fit_image_load(bootm_headers_t *images, ulong addr,
|
||||
const char **fit_unamep, const char **fit_uname_configp,
|
||||
int arch, int image_type, int bootstage_id,
|
||||
enum fit_load_op load_op, ulong *datap, ulong *lenp);
|
||||
|
||||
#ifndef USE_HOSTCC
|
||||
/**
|
||||
* fit_get_node_from_config() - Look up an image a FIT by type
|
||||
*
|
||||
@@ -600,8 +607,8 @@ int image_check_dcrc(const image_header_t *hdr);
|
||||
ulong getenv_bootm_low(void);
|
||||
phys_size_t getenv_bootm_size(void);
|
||||
phys_size_t getenv_bootm_mapsize(void);
|
||||
void memmove_wd(void *to, void *from, size_t len, ulong chunksz);
|
||||
#endif
|
||||
void memmove_wd(void *to, void *from, size_t len, ulong chunksz);
|
||||
|
||||
static inline int image_check_magic(const image_header_t *hdr)
|
||||
{
|
||||
@@ -704,7 +711,7 @@ int bootz_setup(ulong image, ulong *start, ulong *end);
|
||||
#define FIT_FDT_PROP "fdt"
|
||||
#define FIT_DEFAULT_PROP "default"
|
||||
|
||||
#define FIT_MAX_HASH_LEN 20 /* max(crc32_len(4), sha1_len(20)) */
|
||||
#define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE
|
||||
|
||||
/* cmdline argument format parsing */
|
||||
int fit_parse_conf(const char *spec, ulong addr_curr,
|
||||
@@ -879,7 +886,7 @@ struct image_region {
|
||||
};
|
||||
|
||||
#if IMAGE_ENABLE_VERIFY
|
||||
# include <rsa-checksum.h>
|
||||
# include <u-boot/rsa-checksum.h>
|
||||
#endif
|
||||
struct checksum_algo {
|
||||
const char *name;
|
||||
|
||||
104
include/iotrace.h
Normal file
104
include/iotrace.h
Normal file
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
* Copyright (c) 2014 Google, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __IOTRACE_H
|
||||
#define __IOTRACE_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/*
|
||||
* This file is designed to be included in arch/<arch>/include/asm/io.h.
|
||||
* It redirects all IO access through a tracing/checksumming feature for
|
||||
* testing purposes.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_IO_TRACE) && !defined(IOTRACE_IMPL) && \
|
||||
!defined(CONFIG_SPL_BUILD)
|
||||
|
||||
#undef readl
|
||||
#define readl(addr) iotrace_readl((const void *)(addr))
|
||||
|
||||
#undef writel
|
||||
#define writel(val, addr) iotrace_writel(val, (const void *)(addr))
|
||||
|
||||
#undef readw
|
||||
#define readw(addr) iotrace_readw((const void *)(addr))
|
||||
|
||||
#undef writew
|
||||
#define writew(val, addr) iotrace_writew(val, (const void *)(addr))
|
||||
|
||||
#undef readb
|
||||
#define readb(addr) iotrace_readb((const void *)(addr))
|
||||
|
||||
#undef writeb
|
||||
#define writeb(val, addr) iotrace_writeb(val, (const void *)(addr))
|
||||
|
||||
#endif
|
||||
|
||||
/* Tracing functions which mirror their io.h counterparts */
|
||||
u32 iotrace_readl(const void *ptr);
|
||||
void iotrace_writel(ulong value, const void *ptr);
|
||||
u16 iotrace_readw(const void *ptr);
|
||||
void iotrace_writew(ulong value, const void *ptr);
|
||||
u8 iotrace_readb(const void *ptr);
|
||||
void iotrace_writeb(ulong value, const void *ptr);
|
||||
|
||||
/**
|
||||
* iotrace_reset_checksum() - Reset the iotrace checksum
|
||||
*/
|
||||
void iotrace_reset_checksum(void);
|
||||
|
||||
/**
|
||||
* iotrace_get_checksum() - Get the current checksum value
|
||||
*
|
||||
* @return currect checksum value
|
||||
*/
|
||||
u32 iotrace_get_checksum(void);
|
||||
|
||||
/**
|
||||
* iotrace_set_enabled() - Set whether iotracing is enabled or not
|
||||
*
|
||||
* This controls whether the checksum is updated and a trace record added
|
||||
* for each I/O access.
|
||||
*
|
||||
* @enable: true to enable iotracing, false to disable
|
||||
*/
|
||||
void iotrace_set_enabled(int enable);
|
||||
|
||||
/**
|
||||
* iotrace_get_enabled() - Get whether iotracing is enabled or not
|
||||
*
|
||||
* @return true if enabled, false if disabled
|
||||
*/
|
||||
int iotrace_get_enabled(void);
|
||||
|
||||
/**
|
||||
* iotrace_set_buffer() - Set position and size of iotrace buffer
|
||||
*
|
||||
* Defines where the iotrace buffer goes, and resets the output pointer to
|
||||
* the start of the buffer.
|
||||
*
|
||||
* The buffer can be 0 size in which case the checksum is updated but no
|
||||
* trace records are writen. If the buffer is exhausted, the offset will
|
||||
* continue to increase but not new data will be written.
|
||||
*
|
||||
* @start: Start address of buffer
|
||||
* @size: Size of buffer in bytes
|
||||
*/
|
||||
void iotrace_set_buffer(ulong start, ulong size);
|
||||
|
||||
/**
|
||||
* iotrace_get_buffer() - Get buffer information
|
||||
*
|
||||
* @start: Returns start address of buffer
|
||||
* @size: Returns size of buffer in bytes
|
||||
* @offset: Returns the byte offset where the next output trace record will
|
||||
* @count: Returns the number of trace records recorded
|
||||
* be written (or would be if the buffer was large enough)
|
||||
*/
|
||||
void iotrace_get_buffer(ulong *start, ulong *size, ulong *offset, ulong *count);
|
||||
|
||||
#endif /* __IOTRACE_H */
|
||||
@@ -21,10 +21,6 @@
|
||||
#if defined(CONFIG_MPC8272_FAMILY)
|
||||
#ifdef CONFIG_MPC8247
|
||||
#define CPU_ID_STR "MPC8247"
|
||||
#elif defined CONFIG_MPC8248
|
||||
#define CPU_ID_STR "MPC8248"
|
||||
#elif defined CONFIG_MPC8271
|
||||
#define CPU_ID_STR "MPC8271"
|
||||
#else
|
||||
#define CPU_ID_STR "MPC8272"
|
||||
#endif
|
||||
|
||||
@@ -180,6 +180,17 @@ int test_part_amiga (block_dev_desc_t *dev_desc);
|
||||
#include <part_efi.h>
|
||||
/* disk/part_efi.c */
|
||||
int get_partition_info_efi (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
|
||||
/**
|
||||
* get_partition_info_efi_by_name() - Find the specified GPT partition table entry
|
||||
*
|
||||
* @param dev_desc - block device descriptor
|
||||
* @param gpt_name - the specified table entry name
|
||||
* @param info - returns the disk partition info
|
||||
*
|
||||
* @return - '0' on match, '-1' on no match, otherwise error
|
||||
*/
|
||||
int get_partition_info_efi_by_name(block_dev_desc_t *dev_desc,
|
||||
const char *name, disk_partition_t *info);
|
||||
void print_part_efi (block_dev_desc_t *dev_desc);
|
||||
int test_part_efi (block_dev_desc_t *dev_desc);
|
||||
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __H_
|
||||
#ifndef _TPS6586X_H_
|
||||
#define _TPS6586X_H_
|
||||
|
||||
enum {
|
||||
|
||||
@@ -9,8 +9,8 @@
|
||||
|
||||
#include <errno.h>
|
||||
#include <image.h>
|
||||
#include <sha1.h>
|
||||
#include <sha256.h>
|
||||
#include <u-boot/sha1.h>
|
||||
#include <u-boot/sha256.h>
|
||||
|
||||
extern const uint8_t padding_sha256_rsa4096[];
|
||||
extern const uint8_t padding_sha256_rsa2048[];
|
||||
@@ -60,7 +60,8 @@ int rsa_sign(struct image_sign_info *info,
|
||||
*
|
||||
* @info: Specifies key and FIT information
|
||||
* @keydest: Destination FDT blob for public key data
|
||||
* @return: 0, on success, -ve on error
|
||||
* @return: 0, on success, -ENOSPC if the keydest FDT blob ran out of space,
|
||||
other -ve value on error
|
||||
*/
|
||||
int rsa_add_verify_data(struct image_sign_info *info, void *keydest);
|
||||
#else
|
||||
Reference in New Issue
Block a user