Merge git://git.denx.de/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
@@ -124,6 +124,7 @@
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"swappartitions=" \
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"setexpr partnum 3 - ${partnum}\0" \
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"failbootcmd=" \
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"bx50_backlight_enable; " \
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"msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \
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"echo $msg; " \
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"setenv stdout vga; " \
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@@ -1,155 +0,0 @@
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/*
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* (C) Copyright 2004
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Kshitij Gupta <kshitij@ti.com>
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*
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* Configuration settings for the phyCORE-i.MX31 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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/* High Level Configuration Options */
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#define CONFIG_MX31 /* This is a mx31 */
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#define CONFIG_MX31_CLK32 32000
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/***********************************************************
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* Command definition
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***********************************************************/
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.23.168
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#define CONFIG_SERVERIP 192.168.23.2
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
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"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
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"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
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"bootargs_flash=setenv bootargs $(bootargs) " \
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"root=/dev/mtdblock2 rootfstype=jffs2\0" \
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"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
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"bootcmd=run bootcmd_net\0" \
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"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \
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"tftpboot 0x80000000 $(uimage);bootm\0" \
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"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \
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"bootm 0x80000000\0" \
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"unlock=yes\0" \
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"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
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"prg_uboot=tftpboot 0x80000000 $(uboot);" \
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"protect off 0xa0000000 +0x20000;" \
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"erase 0xa0000000 +0x20000;" \
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"cp.b 0x80000000 0xa0000000 $(filesize)\0" \
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"prg_kernel=tftpboot 0x80000000 $(uimage);" \
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"erase 0xa0040000 +0x180000;" \
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"cp.b 0x80000000 0xa0040000 $(filesize)\0" \
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"prg_jffs2=tftpboot 0x80000000 $(jffs2);" \
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"erase 0xa01c0000 0xa1ffffff;" \
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"cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
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"videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \
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"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
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"sync:1241513985,vmode:0\0"
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x10000
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#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x80000000
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#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_GBL_DATA_OFFSET)
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/*
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_FLASH_BASE 0xa0000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */
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/* Monitor at beginning of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */
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#define CONFIG_ENV_SIZE 4096
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */
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/*
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* CFI FLASH driver setup
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*/
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#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
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#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
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#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
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/*
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* Timeout for Flash Erase and Flash Write
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* timeout values are in ticks
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*/
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#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ)
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/*
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* JFFS2 partitions
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*/
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#define CONFIG_JFFS2_DEV "nor0"
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/* EET platform additions */
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#ifdef CONFIG_TARGET_IMX31_PHYCORE_EET
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#define CONFIG_HARD_SPI
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#define CONFIG_S6E63D6
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#define CONFIG_VIDEO_MX3
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_BMP_16BPP
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#endif
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#endif /* __CONFIG_H */
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141
include/configs/kp_imx6q_tpc.h
Normal file
141
include/configs/kp_imx6q_tpc.h
Normal file
@@ -0,0 +1,141 @@
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/*
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* K+P iMX6Q KP_IMX6Q_TPC board configuration
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*
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* Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __KP_IMX6Q_TPC_IMX6_CONFIG_H_
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#define __KP_IMX6Q_TPC_IMX6_CONFIG_H_
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#include <asm/arch/imx-regs.h>
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#include "mx6_common.h"
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/* SPL */
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#include "imx6_spl.h" /* common IMX6 SPL configuration */
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/* Miscellaneous configurable options */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_BOUNCE_BUFFER
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
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/* FEC ethernet */
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#define CONFIG_MII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_ARP_TIMEOUT 200UL
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/* Fuses */
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#ifdef CONFIG_CMD_FUSE
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#define CONFIG_MXC_OCOTP
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#endif
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_SPEED 100000
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/* MMC Configs */
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#define CONFIG_FSL_ESDHC
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */
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/* UART */
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/* USB Configs */
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#ifdef CONFIG_CMD_USB
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
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#endif
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/* Watchdog */
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_IMX_WATCHDOG
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#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_LOADADDR 0x12000000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"console=ttymxc0,115200\0" \
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"fdt_addr=0x18000000\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"kernel_addr_r=0x10008000\0" \
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"fdt_addr_r=0x13000000\0" \
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"ramdisk_addr_r=0x18000000\0" \
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"scriptaddr=0x14000000\0" \
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"kernel_file=fitImage\0"\
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"rdinit=/sbin/init\0" \
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"addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \
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"fit_config=mx6q_tpc70_conf\0" \
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"upd_image=st.4k\0" \
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"updargs=setenv bootargs console=${console} ${smp}"\
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"rdinit=${rdinit} ${debug} ${displayargs}\0" \
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"loadusb=usb start; " \
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"fatload usb 0 ${loadaddr} ${upd_image}\0" \
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"usbupd=echo Booting update from usb ...; " \
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"setenv bootargs; " \
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"run updargs; " \
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"run loadusb; " \
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"bootm ${loadaddr}#${fit_config}\0" \
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BOOTENV
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#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd"
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(MMC, mmc, 1) \
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func(USB, usb, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#endif
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|
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/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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|
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/* Environment */
|
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#define CONFIG_ENV_SIZE (SZ_8K)
|
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#define CONFIG_ENV_OFFSET 0x100000
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
|
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#endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */
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@@ -75,9 +75,6 @@
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||||
|
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/* I2C */
|
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#define CONFIG_SYS_I2C
|
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#define CONFIG_SYS_I2C_MXC
|
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
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|
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
|
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@@ -147,11 +147,6 @@
|
||||
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/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
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#define CONFIG_SYS_I2C_MXC
|
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#define CONFIG_SYS_I2C_MXC_I2C1
|
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#define CONFIG_SYS_I2C_MXC_I2C2
|
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#define CONFIG_SYS_I2C_MXC_I2C3
|
||||
#define CONFIG_SYS_I2C_MXC_I2C4
|
||||
|
||||
/* PCIe */
|
||||
#ifndef SPL_NO_PCIE
|
||||
|
||||
@@ -125,11 +125,6 @@
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3
|
||||
#define CONFIG_SYS_I2C_MXC_I2C4
|
||||
|
||||
/* PCIe */
|
||||
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||
|
||||
@@ -67,11 +67,6 @@
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
|
||||
@@ -77,11 +77,6 @@
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
|
||||
@@ -12,9 +12,6 @@
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000
|
||||
#define CONFIG_DDR_CLK_FREQ 133333333
|
||||
|
||||
#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
|
||||
#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
|
||||
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
|
||||
#define SPD_EEPROM_ADDRESS1 0x51
|
||||
|
||||
@@ -12,9 +12,6 @@
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000
|
||||
#define CONFIG_DDR_CLK_FREQ 133333333
|
||||
|
||||
#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
|
||||
#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
|
||||
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
||||
|
||||
@@ -1,144 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
|
||||
*
|
||||
* Configuration settings for the MX31ADS Freescale board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_MX31 1 /* This is a mx31 */
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
#define CONFIG_HARD_SPI 1
|
||||
#define CONFIG_DEFAULT_SPI_BUS 1
|
||||
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
|
||||
|
||||
/* PMIC Controller */
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_SPI
|
||||
#define CONFIG_POWER_FSL
|
||||
#define CONFIG_FSL_PMIC_BUS 1
|
||||
#define CONFIG_FSL_PMIC_CS 0
|
||||
#define CONFIG_FSL_PMIC_CLK 1000000
|
||||
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
|
||||
#define CONFIG_FSL_PMIC_BITLEN 32
|
||||
#define CONFIG_RTC_MC13XXX
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"uboot_addr=0xa0000000\0" \
|
||||
"uboot=mx31ads/u-boot.bin\0" \
|
||||
"kernel=mx31ads/uImage\0" \
|
||||
"nfsroot=/opt/eldk/arm\0" \
|
||||
"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
|
||||
"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"bootcmd=run bootcmd_net\0" \
|
||||
"bootcmd_net=run bootargs_base bootargs_nfs; " \
|
||||
"tftpboot ${loadaddr} ${kernel}; bootm\0" \
|
||||
"prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
|
||||
"protect off ${uboot_addr} 0xa003ffff; " \
|
||||
"erase ${uboot_addr} 0xa003ffff; " \
|
||||
"cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
|
||||
"setenv filesize; saveenv\0"
|
||||
|
||||
#define CONFIG_CS8900
|
||||
#define CONFIG_CS8900_BASE 0xb4020300
|
||||
#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */
|
||||
|
||||
/*
|
||||
* The MX31ADS board seems to have a hardware "peculiarity" confirmed under
|
||||
* U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
|
||||
* controller inverted. The controller is capable of detecting and correcting
|
||||
* this, but it needs 4 network packets for that. Which means, at startup, you
|
||||
* will not receive answers to the first 4 packest, unless there have been some
|
||||
* broadcasts on the network, or your board is on a hub. Reducing the ARP
|
||||
* timeout from default 5 seconds to 200ms we speed up the initial TFTP
|
||||
* transfer, should the user wish one, significantly.
|
||||
*/
|
||||
#define CONFIG_ARP_TIMEOUT 200UL
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x10000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM_1 CSD0_BASE
|
||||
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_GBL_DATA_OFFSET)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE CS0_BASE
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */
|
||||
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* CFI FLASH driver setup
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
|
||||
#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
|
||||
|
||||
/*
|
||||
* JFFS2 partitions
|
||||
*/
|
||||
#define CONFIG_JFFS2_DEV "nor0"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -197,8 +197,8 @@
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
|
||||
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
|
||||
#define CONFIG_ENV_SIZE (10 * 1024)
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
|
||||
|
||||
@@ -57,6 +57,9 @@
|
||||
/* Secure boot (HAB) support */
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
#define CONFIG_CSF_SIZE 0x2000
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -50,8 +50,8 @@
|
||||
"finduuid=part uuid mmc 0:2 uuid\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=PARTUUID=${uuid} rootwait rw\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run finduuid; " \
|
||||
"run mmcargs; " \
|
||||
|
||||
@@ -24,6 +24,9 @@
|
||||
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
/* Switch on SERIAL_TAG */
|
||||
#define CONFIG_SERIAL_TAG
|
||||
|
||||
#define CONFIG_DFU_ENV_SETTINGS \
|
||||
"dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
|
||||
|
||||
|
||||
@@ -56,6 +56,7 @@
|
||||
#define DCD_CHECK_BITS_SET_PARAM 0x14
|
||||
#define DCD_CHECK_BITS_CLR_PARAM 0x04
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
enum imximage_cmd {
|
||||
CMD_INVALID,
|
||||
CMD_IMAGE_VERSION,
|
||||
@@ -197,4 +198,5 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
|
||||
typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
|
||||
uint32_t entry_point, uint32_t flash_offset);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* _IMXIMAGE_H_ */
|
||||
|
||||
@@ -1,21 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2009
|
||||
* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _S6E63D6_H_
|
||||
#define _S6E63D6_H_
|
||||
|
||||
struct s6e63d6 {
|
||||
unsigned int bus;
|
||||
unsigned int cs;
|
||||
unsigned int id;
|
||||
struct spi_slave *slave;
|
||||
};
|
||||
|
||||
extern int s6e63d6_init(struct s6e63d6 *data);
|
||||
extern int s6e63d6_index(struct s6e63d6 *data, u8 idx);
|
||||
extern int s6e63d6_param(struct s6e63d6 *data, u16 param);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user