ppc4xx: Update 440EPx lwmon5 board support

- Clear ECC status regs after ECC POST test
- Set dcbz for ECC generation with caches enabled as default
- Code cleanup

Signed-off-by: Stefan Roese <sr@denx.de>

include/configs/lwmon5.h

@@ -140,7 +140,6 @@
 
 /* POST support */
 #define CONFIG_POST		(CFG_POST_ECC)
-
 #endif
 
 /*-----------------------------------------------------------------------

include/ppc440.h

@@ -3354,6 +3354,19 @@ typedef struct {
 	unsigned long pciClkSync;             /* PCI clock is synchronous        */
 } PPC440_SYS_INFO;
 
+static inline u32 get_mcsr(void)
+{
+	u32 val;
+
+	asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+	return val;
+}
+
+static inline void set_mcsr(u32 val)
+{
+	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
 #endif	/* _ASMLANGUAGE */
 
 #define RESET_VECTOR		0xfffffffc