add a new AT91 GPIO driver

* add a real AT91 GPIO driver instead of header inline code
* resolve the mixing of port and pins
* change board config files to use new driver
* add macros to gpio to realize backward compatibility

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
This commit is contained in:
Jens Scharsig
2010-02-03 22:46:16 +01:00
committed by Tom Rix
parent 5d8e359c38
commit ea8fbba731
17 changed files with 258 additions and 152 deletions

View File

@@ -100,10 +100,20 @@ typedef union at91_pio {
at91_port_t port[AT91_PIO_PORTS];
} at91_pio_t;
#ifdef CONFIG_AT91_GPIO
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
int at91_set_pio_output(unsigned port, unsigned pin, int value);
int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
int at91_set_pio_value(unsigned port, unsigned pin, int value);
int at91_get_pio_value(unsigned port, unsigned pin);
#endif
#endif
#define AT91_PIN_TO_MASK(x) (1<<x)
#define AT91_PORTPIN(PORT, PIN) ((0x0##PORT - 9) * 32 + ((PIN) & 0x1F))
#define AT91_PIO_PORTA 0x0
#define AT91_PIO_PORTB 0x1
#define AT91_PIO_PORTC 0x2

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@@ -216,155 +216,23 @@ static inline unsigned pin_to_mask(unsigned pin)
return 1 << (pin % 32);
}
/*
* mux the pin to the "GPIO" peripheral role.
*/
static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
__raw_writel(mask, pio + PIO_PER);
return 0;
}
/*
* mux the pin to the "A" internal peripheral role.
*/
static inline int at91_set_A_periph(unsigned pin, int use_pullup)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
__raw_writel(mask, pio + PIO_ASR);
__raw_writel(mask, pio + PIO_PDR);
return 0;
}
/*
* mux the pin to the "B" internal peripheral role.
*/
static inline int at91_set_B_periph(unsigned pin, int use_pullup)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
__raw_writel(mask, pio + PIO_BSR);
__raw_writel(mask, pio + PIO_PDR);
return 0;
}
/*
* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
* configure it for an input.
*/
static inline int at91_set_gpio_input(unsigned pin, int use_pullup)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
__raw_writel(mask, pio + PIO_ODR);
__raw_writel(mask, pio + PIO_PER);
return 0;
}
/*
* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
* and configure it for an output.
*/
static inline int at91_set_gpio_output(unsigned pin, int value)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + PIO_PUDR);
__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
__raw_writel(mask, pio + PIO_OER);
__raw_writel(mask, pio + PIO_PER);
return 0;
}
/*
* enable/disable the glitch filter; mostly used with IRQ handling.
*/
static inline int at91_set_deglitch(unsigned pin, int is_on)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
return 0;
}
/*
* enable/disable the multi-driver; This is only valid for output and
* allows the output pin to run as an open collector output.
*/
static inline int at91_set_multi_drive(unsigned pin, int is_on)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
return 0;
}
static inline int gpio_direction_input(unsigned pin)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
if (!(__raw_readl(pio + PIO_PSR) & mask))
return -EINVAL;
__raw_writel(mask, pio + PIO_ODR);
return 0;
}
static inline int gpio_direction_output(unsigned pin, int value)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
if (!(__raw_readl(pio + PIO_PSR) & mask))
return -EINVAL;
__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
__raw_writel(mask, pio + PIO_OER);
return 0;
}
/*
* assuming the pin is muxed as a gpio output, set its value.
*/
static inline int at91_set_gpio_value(unsigned pin, int value)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
return 0;
}
/*
* read the pin's value (works even if it's not muxed as a gpio).
*/
static inline int at91_get_gpio_value(unsigned pin)
{
void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
u32 pdsr;
pdsr = __raw_readl(pio + PIO_PDSR);
return (pdsr & mask) != 0;
}
/* The following macros are need for backward compatibility */
#define at91_set_GPIO_periph(x, y) \
at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_A_periph(x, y) \
at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_B_periph(x, y) \
at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_gpio_output(x, y) \
at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_gpio_input(x, y) \
at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_gpio_value(x, y) \
at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y)
#define at91_get_gpio_value(x) \
at91_get_pio_value((x - PIN_BASE) / 32,(x % 32))
#else
#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y)
#define at91_get_gpio_value(x) at91_get_pio_value(x)
#endif
#endif

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@@ -47,6 +47,7 @@
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1

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@@ -49,6 +49,7 @@
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1

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@@ -54,6 +54,7 @@
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1

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@@ -52,6 +52,7 @@
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1

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@@ -51,6 +51,7 @@
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1

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@@ -52,6 +52,7 @@
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1

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@@ -49,6 +49,7 @@
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1

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@@ -244,6 +244,7 @@
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1

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@@ -59,6 +59,7 @@
*/
/* Console output */
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1

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@@ -159,6 +159,7 @@
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1

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@@ -173,6 +173,7 @@
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1

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@@ -59,6 +59,7 @@
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART
#define CONFIG_USART0
#undef CONFIG_USART1

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@@ -68,6 +68,7 @@
/*
* Hardware drivers
*/
#define CONFIG_AT91_GPIO 1
#define CONFIG_ATMEL_USART 1
#undef CONFIG_USART0
#undef CONFIG_USART1