Merge branch 'cleanups' into next
This commit is contained in:
Haavard Skinnemoen
@@ -23,11 +23,14 @@
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#define __ASM_AVR32_ARCH_CLK_H__
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#include <asm/arch/chip-features.h>
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#include <asm/arch/portmux.h>
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#ifdef CONFIG_PLL
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#define MAIN_CLK_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) * CONFIG_SYS_PLL0_MUL)
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#define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \
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* CONFIG_SYS_PLL0_MUL)
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#define MAIN_CLK_RATE PLL0_RATE
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#else
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#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
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#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
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#endif
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static inline unsigned long get_cpu_clk_rate(void)
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@@ -82,9 +85,101 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
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#endif
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extern void clk_init(void);
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extern void gclk_init(void) __attribute__((weak));
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/* Board code may need the SDRAM base clock as a compile-time constant */
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#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
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/* Generic clock control */
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enum gclk_parent {
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GCLK_PARENT_OSC0 = 0,
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GCLK_PARENT_OSC1 = 1,
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GCLK_PARENT_PLL0 = 2,
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GCLK_PARENT_PLL1 = 3,
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};
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/* Some generic clocks have specific roles */
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#define GCLK_DAC_SAMPLE_CLK 6
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#define GCLK_LCDC_PIXCLK 7
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extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
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unsigned long rate, unsigned long parent_rate);
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/**
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* gclk_set_rate - configure and enable a generic clock
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* @id: Which GCLK[id] to enable
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* @parent: Parent clock feeding the GCLK
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* @rate: Target rate of the GCLK in Hz
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*
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* Returns the actual GCLK rate in Hz, after rounding to the nearest
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* supported rate.
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*
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* All three parameters are usually constant, hence the inline.
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*/
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static inline unsigned long gclk_set_rate(unsigned int id,
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enum gclk_parent parent, unsigned long rate)
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{
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unsigned long parent_rate;
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if (id > 7)
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return 0;
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switch (parent) {
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case GCLK_PARENT_OSC0:
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parent_rate = CONFIG_SYS_OSC0_HZ;
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break;
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#ifdef CONFIG_SYS_OSC1_HZ
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case GCLK_PARENT_OSC1:
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parent_rate = CONFIG_SYS_OSC1_HZ;
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break;
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#endif
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#ifdef PLL0_RATE
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case GCLK_PARENT_PLL0:
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parent_rate = PLL0_RATE;
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break;
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#endif
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#ifdef PLL1_RATE
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case GCLK_PARENT_PLL1:
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parent_rate = PLL1_RATE;
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break;
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#endif
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default:
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parent_rate = 0;
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break;
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}
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return __gclk_set_rate(id, parent, rate, parent_rate);
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}
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/**
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* gclk_enable_output - enable output on a GCLK pin
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* @id: Which GCLK[id] pin to enable
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* @drive_strength: Drive strength of external GCLK pin, if applicable
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*/
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static inline void gclk_enable_output(unsigned int id,
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unsigned long drive_strength)
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{
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switch (id) {
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case 0:
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portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
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PORTMUX_FUNC_A, drive_strength);
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break;
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case 1:
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portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
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PORTMUX_FUNC_A, drive_strength);
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break;
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case 2:
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portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
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PORTMUX_FUNC_A, drive_strength);
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break;
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case 3:
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portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
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PORTMUX_FUNC_A, drive_strength);
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break;
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case 4:
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portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
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PORTMUX_FUNC_A, drive_strength);
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break;
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}
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}
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#endif /* __ASM_AVR32_ARCH_CLK_H__ */
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2006 Atmel Corporation
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* Copyright (C) 2006, 2008 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@@ -31,161 +31,17 @@
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* Pin numbers identifying specific GPIO pins on the chip.
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*/
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#define GPIO_PIOA_BASE (0)
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#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0)
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#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1)
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#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2)
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#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3)
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#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4)
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#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5)
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#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6)
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#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7)
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#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8)
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#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9)
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#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10)
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#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11)
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#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12)
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#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13)
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#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14)
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#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15)
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#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16)
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#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17)
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#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18)
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#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19)
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#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20)
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#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21)
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#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22)
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#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23)
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#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24)
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#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25)
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#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26)
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#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27)
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#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28)
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#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29)
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#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30)
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#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31)
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#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
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#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0)
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#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1)
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#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2)
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#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3)
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#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4)
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#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5)
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#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6)
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#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7)
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#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8)
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#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9)
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#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10)
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#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11)
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#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12)
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#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13)
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#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14)
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#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15)
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#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16)
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#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17)
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#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18)
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#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19)
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#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20)
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#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21)
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#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22)
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#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23)
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#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24)
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#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25)
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#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26)
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#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27)
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#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28)
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#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29)
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#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30)
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#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
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#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0)
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#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1)
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#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2)
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#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3)
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#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4)
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#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5)
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#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6)
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#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7)
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#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8)
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#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9)
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#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10)
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#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11)
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#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12)
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#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13)
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#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14)
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#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15)
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#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16)
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#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17)
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#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18)
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#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19)
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#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20)
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#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21)
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#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22)
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#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23)
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#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24)
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#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25)
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#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26)
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#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27)
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#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28)
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#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29)
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#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30)
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#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31)
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#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
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#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0)
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#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1)
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#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2)
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#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3)
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||||
#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4)
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||||
#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5)
|
||||
#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6)
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||||
#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7)
|
||||
#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8)
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||||
#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9)
|
||||
#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10)
|
||||
#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11)
|
||||
#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12)
|
||||
#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13)
|
||||
#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14)
|
||||
#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15)
|
||||
#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16)
|
||||
#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17)
|
||||
|
||||
#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
|
||||
#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0)
|
||||
#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1)
|
||||
#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2)
|
||||
#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3)
|
||||
#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4)
|
||||
#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5)
|
||||
#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6)
|
||||
#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7)
|
||||
#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8)
|
||||
#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9)
|
||||
#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10)
|
||||
#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11)
|
||||
#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12)
|
||||
#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13)
|
||||
#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14)
|
||||
#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15)
|
||||
#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16)
|
||||
#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17)
|
||||
#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18)
|
||||
#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19)
|
||||
#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20)
|
||||
#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21)
|
||||
#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22)
|
||||
#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23)
|
||||
#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24)
|
||||
#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25)
|
||||
#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26)
|
||||
#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x))
|
||||
#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x))
|
||||
#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x))
|
||||
#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x))
|
||||
#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x))
|
||||
|
||||
#define GPIOF_PULLUP 0x00000001 /* (not-OUT) Enable pull-up */
|
||||
#define GPIOF_OUTPUT 0x00000002 /* (OUT) Enable output driver */
|
||||
#define GPIOF_DEGLITCH 0x00000004 /* (IN) Filter glitches */
|
||||
#define GPIOF_MULTIDRV 0x00000008 /* Enable multidriver option */
|
||||
|
||||
static inline void *gpio_pin_to_addr(unsigned int pin)
|
||||
static inline void *pio_pin_to_port(unsigned int pin)
|
||||
{
|
||||
switch (pin >> 5) {
|
||||
case 0:
|
||||
@@ -203,30 +59,6 @@ static inline void *gpio_pin_to_addr(unsigned int pin)
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_select_periph_A(unsigned int pin, int use_pullup);
|
||||
void gpio_select_periph_B(unsigned int pin, int use_pullup);
|
||||
void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags);
|
||||
void gpio_set_value(unsigned int pin, int value);
|
||||
int gpio_get_value(unsigned int pin);
|
||||
|
||||
void gpio_enable_ebi(void);
|
||||
|
||||
#ifdef AT32AP700x_CHIP_HAS_USART
|
||||
void gpio_enable_usart0(void);
|
||||
void gpio_enable_usart1(void);
|
||||
void gpio_enable_usart2(void);
|
||||
void gpio_enable_usart3(void);
|
||||
#endif
|
||||
#ifdef AT32AP700x_CHIP_HAS_MACB
|
||||
void gpio_enable_macb0(void);
|
||||
void gpio_enable_macb1(void);
|
||||
#endif
|
||||
#ifdef AT32AP700x_CHIP_HAS_MMCI
|
||||
void gpio_enable_mmci(void);
|
||||
#endif
|
||||
#ifdef AT32AP700x_CHIP_HAS_SPI
|
||||
void gpio_enable_spi0(unsigned long cs_mask);
|
||||
void gpio_enable_spi1(unsigned long cs_mask);
|
||||
#endif
|
||||
#include <asm/arch-common/portmux-pio.h>
|
||||
|
||||
#endif /* __ASM_AVR32_ARCH_GPIO_H__ */
|
||||
|
||||
89
include/asm-avr32/arch-at32ap700x/portmux.h
Normal file
89
include/asm-avr32/arch-at32ap700x/portmux.h
Normal file
@@ -0,0 +1,89 @@
|
||||
/*
|
||||
* Copyright (C) 2006, 2008 Atmel Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_AVR32_ARCH_PORTMUX_H__
|
||||
#define __ASM_AVR32_ARCH_PORTMUX_H__
|
||||
|
||||
#include <asm/arch/gpio.h>
|
||||
|
||||
#define PORTMUX_PORT_A ((void *)PIOA_BASE)
|
||||
#define PORTMUX_PORT_B ((void *)PIOB_BASE)
|
||||
#define PORTMUX_PORT_C ((void *)PIOC_BASE)
|
||||
#define PORTMUX_PORT_D ((void *)PIOD_BASE)
|
||||
#define PORTMUX_PORT_E ((void *)PIOE_BASE)
|
||||
|
||||
void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width,
|
||||
unsigned long flags, unsigned long drive_strength);
|
||||
|
||||
#define PORTMUX_EBI_CS(x) (1 << (x))
|
||||
#define PORTMUX_EBI_NAND (1 << 6)
|
||||
#define PORTMUX_EBI_CF(x) (1 << ((x) + 7))
|
||||
#define PORTMUX_EBI_NWAIT (1 << 9)
|
||||
|
||||
#ifdef AT32AP700x_CHIP_HAS_USART
|
||||
static inline void portmux_enable_usart0(unsigned long drive_strength)
|
||||
{
|
||||
portmux_select_peripheral(PORTMUX_PORT_A, (1 << 8) | (1 << 9),
|
||||
PORTMUX_FUNC_B, 0);
|
||||
}
|
||||
|
||||
static inline void portmux_enable_usart1(unsigned long drive_strength)
|
||||
{
|
||||
portmux_select_peripheral(PORTMUX_PORT_A, (1 << 17) | (1 << 18),
|
||||
PORTMUX_FUNC_A, 0);
|
||||
}
|
||||
|
||||
static inline void portmux_enable_usart2(unsigned long drive_strength)
|
||||
{
|
||||
portmux_select_peripheral(PORTMUX_PORT_B, (1 << 26) | (1 << 27),
|
||||
PORTMUX_FUNC_B, 0);
|
||||
}
|
||||
|
||||
static inline void portmux_enable_usart3(unsigned long drive_strength)
|
||||
{
|
||||
portmux_select_peripheral(PORTMUX_PORT_B, (1 << 17) | (1 << 18),
|
||||
PORTMUX_FUNC_B, 0);
|
||||
}
|
||||
#endif
|
||||
#ifdef AT32AP700x_CHIP_HAS_MACB
|
||||
void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength);
|
||||
void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength);
|
||||
|
||||
#define PORTMUX_MACB_RMII (0)
|
||||
#define PORTMUX_MACB_MII (1 << 0)
|
||||
#define PORTMUX_MACB_SPEED (1 << 1)
|
||||
|
||||
#endif
|
||||
#ifdef AT32AP700x_CHIP_HAS_MMCI
|
||||
void portmux_enable_mmci(unsigned int slot, unsigned long flags,
|
||||
unsigned long drive_strength);
|
||||
|
||||
#define PORTMUX_MMCI_4BIT (1 << 0)
|
||||
#define PORTMUX_MMCI_8BIT (PORTMUX_MMCI_4BIT | (1 << 1))
|
||||
#define PORTMUX_MMCI_EXT_PULLUP (1 << 2)
|
||||
|
||||
#endif
|
||||
#ifdef AT32AP700x_CHIP_HAS_SPI
|
||||
void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength);
|
||||
void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength);
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */
|
||||
193
include/asm-avr32/arch-common/portmux-gpio.h
Normal file
193
include/asm-avr32/arch-common/portmux-gpio.h
Normal file
@@ -0,0 +1,193 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Atmel Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __AVR32_PORTMUX_GPIO_H__
|
||||
#define __AVR32_PORTMUX_GPIO_H__
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
/* Register offsets */
|
||||
struct gpio_regs {
|
||||
u32 GPER;
|
||||
u32 GPERS;
|
||||
u32 GPERC;
|
||||
u32 GPERT;
|
||||
u32 PMR0;
|
||||
u32 PMR0S;
|
||||
u32 PMR0C;
|
||||
u32 PMR0T;
|
||||
u32 PMR1;
|
||||
u32 PMR1S;
|
||||
u32 PMR1C;
|
||||
u32 PMR1T;
|
||||
u32 __reserved0[4];
|
||||
u32 ODER;
|
||||
u32 ODERS;
|
||||
u32 ODERC;
|
||||
u32 ODERT;
|
||||
u32 OVR;
|
||||
u32 OVRS;
|
||||
u32 OVRC;
|
||||
u32 OVRT;
|
||||
u32 PVR;
|
||||
u32 __reserved_PVRS;
|
||||
u32 __reserved_PVRC;
|
||||
u32 __reserved_PVRT;
|
||||
u32 PUER;
|
||||
u32 PUERS;
|
||||
u32 PUERC;
|
||||
u32 PUERT;
|
||||
u32 PDER;
|
||||
u32 PDERS;
|
||||
u32 PDERC;
|
||||
u32 PDERT;
|
||||
u32 IER;
|
||||
u32 IERS;
|
||||
u32 IERC;
|
||||
u32 IERT;
|
||||
u32 IMR0;
|
||||
u32 IMR0S;
|
||||
u32 IMR0C;
|
||||
u32 IMR0T;
|
||||
u32 IMR1;
|
||||
u32 IMR1S;
|
||||
u32 IMR1C;
|
||||
u32 IMR1T;
|
||||
u32 GFER;
|
||||
u32 GFERS;
|
||||
u32 GFERC;
|
||||
u32 GFERT;
|
||||
u32 IFR;
|
||||
u32 __reserved_IFRS;
|
||||
u32 IFRC;
|
||||
u32 __reserved_IFRT;
|
||||
u32 ODMER;
|
||||
u32 ODMERS;
|
||||
u32 ODMERC;
|
||||
u32 ODMERT;
|
||||
u32 __reserved1[4];
|
||||
u32 ODCR0;
|
||||
u32 ODCR0S;
|
||||
u32 ODCR0C;
|
||||
u32 ODCR0T;
|
||||
u32 ODCR1;
|
||||
u32 ODCR1S;
|
||||
u32 ODCR1C;
|
||||
u32 ODCR1T;
|
||||
u32 __reserved2[4];
|
||||
u32 OSRR0;
|
||||
u32 OSRR0S;
|
||||
u32 OSRR0C;
|
||||
u32 OSRR0T;
|
||||
u32 __reserved3[8];
|
||||
u32 STER;
|
||||
u32 STERS;
|
||||
u32 STERC;
|
||||
u32 STERT;
|
||||
u32 __reserved4[35];
|
||||
u32 VERSION;
|
||||
};
|
||||
|
||||
/* Register access macros */
|
||||
#define gpio_readl(port, reg) \
|
||||
__raw_readl(&((struct gpio_regs *)port)->reg)
|
||||
#define gpio_writel(gpio, reg, value) \
|
||||
__raw_writel(value, &((struct gpio_regs *)port)->reg)
|
||||
|
||||
/* Portmux API starts here. See doc/README.AVR32-port-muxing */
|
||||
|
||||
enum portmux_function {
|
||||
PORTMUX_FUNC_A,
|
||||
PORTMUX_FUNC_B,
|
||||
PORTMUX_FUNC_C,
|
||||
PORTMUX_FUNC_D,
|
||||
};
|
||||
|
||||
#define PORTMUX_DIR_INPUT (0 << 0)
|
||||
#define PORTMUX_DIR_OUTPUT (1 << 0)
|
||||
#define PORTMUX_INIT_LOW (0 << 1)
|
||||
#define PORTMUX_INIT_HIGH (1 << 1)
|
||||
#define PORTMUX_PULL_UP (1 << 2)
|
||||
#define PORTMUX_PULL_DOWN (2 << 2)
|
||||
#define PORTMUX_BUSKEEPER (3 << 2)
|
||||
#define PORTMUX_DRIVE_MIN (0 << 4)
|
||||
#define PORTMUX_DRIVE_LOW (1 << 4)
|
||||
#define PORTMUX_DRIVE_HIGH (2 << 4)
|
||||
#define PORTMUX_DRIVE_MAX (3 << 4)
|
||||
#define PORTMUX_OPEN_DRAIN (1 << 6)
|
||||
|
||||
void portmux_select_peripheral(void *port, unsigned long pin_mask,
|
||||
enum portmux_function func, unsigned long flags);
|
||||
void portmux_select_gpio(void *port, unsigned long pin_mask,
|
||||
unsigned long flags);
|
||||
|
||||
/* Internal helper functions */
|
||||
|
||||
static inline void *gpio_pin_to_port(unsigned int pin)
|
||||
{
|
||||
return (void *)GPIO_BASE + (pin >> 5) * 0x200;
|
||||
}
|
||||
|
||||
static inline void __gpio_set_output_value(void *port, unsigned int pin,
|
||||
int value)
|
||||
{
|
||||
if (value)
|
||||
gpio_writel(port, OVRS, 1 << pin);
|
||||
else
|
||||
gpio_writel(port, OVRC, 1 << pin);
|
||||
}
|
||||
|
||||
static inline int __gpio_get_input_value(void *port, unsigned int pin)
|
||||
{
|
||||
return (gpio_readl(port, PVR) >> pin) & 1;
|
||||
}
|
||||
|
||||
void gpio_set_output_value(unsigned int pin, int value);
|
||||
int gpio_get_input_value(unsigned int pin);
|
||||
|
||||
/* GPIO API starts here */
|
||||
|
||||
/*
|
||||
* GCC doesn't realize that the constant case is extremely trivial,
|
||||
* so we need to help it make the right decision by using
|
||||
* always_inline.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void gpio_set_value(unsigned int pin, int value)
|
||||
{
|
||||
if (__builtin_constant_p(pin))
|
||||
__gpio_set_output_value(gpio_pin_to_port(pin),
|
||||
pin & 0x1f, value);
|
||||
else
|
||||
gpio_set_output_value(pin, value);
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline int gpio_get_value(unsigned int pin)
|
||||
{
|
||||
if (__builtin_constant_p(pin))
|
||||
return __gpio_get_input_value(gpio_pin_to_port(pin),
|
||||
pin & 0x1f);
|
||||
else
|
||||
return gpio_get_input_value(pin);
|
||||
}
|
||||
|
||||
#endif /* __AVR32_PORTMUX_GPIO_H__ */
|
||||
138
include/asm-avr32/arch-common/portmux-pio.h
Normal file
138
include/asm-avr32/arch-common/portmux-pio.h
Normal file
@@ -0,0 +1,138 @@
|
||||
/*
|
||||
* Copyright (C) 2006, 2008 Atmel Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __AVR32_PORTMUX_PIO_H__
|
||||
#define __AVR32_PORTMUX_PIO_H__
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
/* PIO register offsets */
|
||||
#define PIO_PER 0x0000
|
||||
#define PIO_PDR 0x0004
|
||||
#define PIO_PSR 0x0008
|
||||
#define PIO_OER 0x0010
|
||||
#define PIO_ODR 0x0014
|
||||
#define PIO_OSR 0x0018
|
||||
#define PIO_IFER 0x0020
|
||||
#define PIO_IFDR 0x0024
|
||||
#define PIO_ISFR 0x0028
|
||||
#define PIO_SODR 0x0030
|
||||
#define PIO_CODR 0x0034
|
||||
#define PIO_ODSR 0x0038
|
||||
#define PIO_PDSR 0x003c
|
||||
#define PIO_IER 0x0040
|
||||
#define PIO_IDR 0x0044
|
||||
#define PIO_IMR 0x0048
|
||||
#define PIO_ISR 0x004c
|
||||
#define PIO_MDER 0x0050
|
||||
#define PIO_MDDR 0x0054
|
||||
#define PIO_MDSR 0x0058
|
||||
#define PIO_PUDR 0x0060
|
||||
#define PIO_PUER 0x0064
|
||||
#define PIO_PUSR 0x0068
|
||||
#define PIO_ASR 0x0070
|
||||
#define PIO_BSR 0x0074
|
||||
#define PIO_ABSR 0x0078
|
||||
#define PIO_OWER 0x00a0
|
||||
#define PIO_OWDR 0x00a4
|
||||
#define PIO_OWSR 0x00a8
|
||||
|
||||
/* Hardware register access */
|
||||
#define pio_readl(base, reg) \
|
||||
__raw_readl((void *)base + PIO_##reg)
|
||||
#define pio_writel(base, reg, value) \
|
||||
__raw_writel((value), (void *)base + PIO_##reg)
|
||||
|
||||
/* Portmux API starts here. See doc/README.AVR32-port-muxing */
|
||||
|
||||
enum portmux_function {
|
||||
PORTMUX_FUNC_A,
|
||||
PORTMUX_FUNC_B,
|
||||
};
|
||||
|
||||
/* Pull-down, buskeeper and drive strength are not supported */
|
||||
#define PORTMUX_DIR_INPUT (0 << 0)
|
||||
#define PORTMUX_DIR_OUTPUT (1 << 0)
|
||||
#define PORTMUX_INIT_LOW (0 << 1)
|
||||
#define PORTMUX_INIT_HIGH (1 << 1)
|
||||
#define PORTMUX_PULL_UP (1 << 2)
|
||||
#define PORTMUX_PULL_DOWN (0)
|
||||
#define PORTMUX_BUSKEEPER PORTMUX_PULL_UP
|
||||
#define PORTMUX_DRIVE_MIN (0)
|
||||
#define PORTMUX_DRIVE_LOW (0)
|
||||
#define PORTMUX_DRIVE_HIGH (0)
|
||||
#define PORTMUX_DRIVE_MAX (0)
|
||||
#define PORTMUX_OPEN_DRAIN (1 << 3)
|
||||
|
||||
void portmux_select_peripheral(void *port, unsigned long pin_mask,
|
||||
enum portmux_function func, unsigned long flags);
|
||||
void portmux_select_gpio(void *port, unsigned long pin_mask,
|
||||
unsigned long flags);
|
||||
|
||||
/* Internal helper functions */
|
||||
|
||||
static inline void __pio_set_output_value(void *port, unsigned int pin,
|
||||
int value)
|
||||
{
|
||||
/*
|
||||
* value will usually be constant, but it's pretty cheap
|
||||
* either way.
|
||||
*/
|
||||
if (value)
|
||||
pio_writel(port, SODR, 1 << pin);
|
||||
else
|
||||
pio_writel(port, CODR, 1 << pin);
|
||||
}
|
||||
|
||||
static inline int __pio_get_input_value(void *port, unsigned int pin)
|
||||
{
|
||||
return (pio_readl(port, PDSR) >> pin) & 1;
|
||||
}
|
||||
|
||||
void pio_set_output_value(unsigned int pin, int value);
|
||||
int pio_get_input_value(unsigned int pin);
|
||||
|
||||
/* GPIO API starts here */
|
||||
|
||||
/*
|
||||
* GCC doesn't realize that the constant case is extremely trivial,
|
||||
* so we need to help it make the right decision by using
|
||||
* always_inline.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void gpio_set_value(unsigned int pin, int value)
|
||||
{
|
||||
if (__builtin_constant_p(pin))
|
||||
__pio_set_output_value(pio_pin_to_port(pin), pin & 0x1f, value);
|
||||
else
|
||||
pio_set_output_value(pin, value);
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline int gpio_get_value(unsigned int pin)
|
||||
{
|
||||
if (__builtin_constant_p(pin))
|
||||
return __pio_get_input_value(pio_pin_to_port(pin), pin & 0x1f);
|
||||
else
|
||||
return pio_get_input_value(pin);
|
||||
}
|
||||
|
||||
#endif /* __AVR32_PORTMUX_PIO_H__ */
|
||||
@@ -26,6 +26,5 @@
|
||||
|
||||
extern int cpu_init(void);
|
||||
extern int timer_init(void);
|
||||
extern void board_init_info(void);
|
||||
|
||||
#endif /* __ASM_AVR32_INITCALLS_H__ */
|
||||
|
||||
@@ -25,8 +25,8 @@
|
||||
struct sdram_config {
|
||||
/* Number of data bits. */
|
||||
enum {
|
||||
SDRAM_DATA_16BIT,
|
||||
SDRAM_DATA_32BIT,
|
||||
SDRAM_DATA_16BIT = 16,
|
||||
SDRAM_DATA_32BIT = 32,
|
||||
} data_bits;
|
||||
|
||||
/* Number of address bits */
|
||||
|
||||
@@ -124,7 +124,7 @@
|
||||
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#define CONFIG_MACB 1
|
||||
#define CONFIG_PIO2 1
|
||||
#define CONFIG_PORTMUX_PIO 1
|
||||
#define CONFIG_SYS_NR_PIOS 5
|
||||
#define CONFIG_SYS_HSDRAMC 1
|
||||
#define CONFIG_MMC 1
|
||||
|
||||
@@ -149,7 +149,7 @@
|
||||
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#define CONFIG_MACB 1
|
||||
#define CONFIG_PIO2 1
|
||||
#define CONFIG_PORTMUX_PIO 1
|
||||
#define CONFIG_SYS_NR_PIOS 5
|
||||
#define CONFIG_SYS_HSDRAMC 1
|
||||
#define CONFIG_MMC 1
|
||||
|
||||
@@ -133,7 +133,7 @@
|
||||
#undef CONFIG_CMD_XIMG
|
||||
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#define CONFIG_PIO2 1
|
||||
#define CONFIG_PORTMUX_PIO 1
|
||||
#define CONFIG_SYS_HSDRAMC 1
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_ATMEL_MCI 1
|
||||
|
||||
@@ -133,7 +133,7 @@
|
||||
#undef CONFIG_CMD_XIMG
|
||||
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#define CONFIG_PIO2 1
|
||||
#define CONFIG_PORTMUX_PIO 1
|
||||
#define CONFIG_SYS_HSDRAMC 1
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_ATMEL_MCI 1
|
||||
|
||||
@@ -149,7 +149,7 @@
|
||||
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#define CONFIG_MACB 1
|
||||
#define CONFIG_PIO2 1
|
||||
#define CONFIG_PORTMUX_PIO 1
|
||||
#define CONFIG_SYS_NR_PIOS 5
|
||||
#define CONFIG_SYS_HSDRAMC 1
|
||||
#define CONFIG_MMC 1
|
||||
|
||||
@@ -146,7 +146,7 @@
|
||||
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#define CONFIG_MACB 1
|
||||
#define CONFIG_PIO2 1
|
||||
#define CONFIG_PORTMUX_PIO 1
|
||||
#define CONFIG_SYS_NR_PIOS 5
|
||||
#define CONFIG_SYS_HSDRAMC 1
|
||||
#define CONFIG_MMC 1
|
||||
|
||||
@@ -117,7 +117,7 @@
|
||||
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#define CONFIG_MACB 1
|
||||
#define CONFIG_PIO2 1
|
||||
#define CONFIG_PORTMUX_PIO 1
|
||||
#define CONFIG_SYS_NR_PIOS 5
|
||||
#define CONFIG_SYS_HSDRAMC 1
|
||||
#define CONFIG_MMC 1
|
||||
|
||||
@@ -121,7 +121,7 @@
|
||||
|
||||
#define CONFIG_ATMEL_USART 1
|
||||
#define CONFIG_MACB 1
|
||||
#define CONFIG_PIO2 1
|
||||
#define CONFIG_PORTMUX_PIO 1
|
||||
#define CONFIG_SYS_NR_PIOS 5
|
||||
#define CONFIG_SYS_HSDRAMC 1
|
||||
#define CONFIG_MMC 1
|
||||
|
||||
Reference in New Issue
Block a user