Merge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Initial support for AM64 EVM and SK - K3 DDR driver unification for J7 and AM64 platforms. - Minor fixes for TI clock driver
This commit is contained in:
Tom Rini
@@ -1060,6 +1060,10 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
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k3-j721e-r5-common-proc-board.dtb \
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k3-j7200-common-proc-board.dtb \
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k3-j7200-r5-common-proc-board.dtb
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dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
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k3-am642-r5-evm.dtb \
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k3-am642-sk.dtb \
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k3-am642-r5-sk.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7622-rfb.dtb \
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2205
arch/arm/dts/k3-am64-ddr.dtsi
Normal file
2205
arch/arm/dts/k3-am64-ddr.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
2187
arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
Normal file
2187
arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
567
arch/arm/dts/k3-am64-main.dtsi
Normal file
567
arch/arm/dts/k3-am64-main.dtsi
Normal file
@@ -0,0 +1,567 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM642 SoC Family Main Domain peripherals
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*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_main {
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oc_sram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x00 0x70000000 0x00 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x70000000 0x200000>;
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atf-sram@0 {
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reg = <0x0 0x1a000>;
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};
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01840000 0x00 0xC0000>; /* GICR */
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/*
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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dmss: dmss {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-ranges;
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ranges;
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ti,sci-dev-id = <25>;
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secure_proxy_main: mailbox@4d000000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x4d000000 0x00 0x80000>,
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<0x00 0x4a600000 0x00 0x80000>,
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<0x00 0x4a400000 0x00 0x80000>;
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interrupt-names = "rx_012";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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};
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inta_main_dmss: interrupt-controller@48000000 {
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compatible = "ti,sci-inta";
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reg = <0x00 0x48000000 0x00 0x100000>;
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#interrupt-cells = <0>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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msi-controller;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <28>;
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ti,interrupt-ranges = <4 68 36>;
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ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
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};
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main_bcdma: dma-controller@485c0100 {
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compatible = "ti,am64-dmss-bcdma";
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reg = <0x00 0x485c0100 0x00 0x100>,
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<0x00 0x4c000000 0x00 0x20000>,
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<0x00 0x4a820000 0x00 0x20000>,
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<0x00 0x4aa40000 0x00 0x20000>,
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<0x00 0x4bc00000 0x00 0x100000>;
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reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
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msi-parent = <&inta_main_dmss>;
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#dma-cells = <3>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <26>;
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ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
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ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
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ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
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};
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main_pktdma: dma-controller@485c0000 {
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compatible = "ti,am64-dmss-pktdma";
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reg = <0x00 0x485c0000 0x00 0x100>,
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<0x00 0x4a800000 0x00 0x20000>,
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<0x00 0x4aa00000 0x00 0x40000>,
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<0x00 0x4b800000 0x00 0x400000>;
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reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
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msi-parent = <&inta_main_dmss>;
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#dma-cells = <2>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <30>;
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ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
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<0x24>, /* CPSW_TX_CHAN */
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<0x25>, /* SAUL_TX_0_CHAN */
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<0x26>, /* SAUL_TX_1_CHAN */
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<0x27>, /* ICSSG_0_TX_CHAN */
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<0x28>; /* ICSSG_1_TX_CHAN */
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ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
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<0x11>, /* RING_CPSW_TX_CHAN */
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<0x12>, /* RING_SAUL_TX_0_CHAN */
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<0x13>, /* RING_SAUL_TX_1_CHAN */
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<0x14>, /* RING_ICSSG_0_TX_CHAN */
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<0x15>; /* RING_ICSSG_1_TX_CHAN */
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ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
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<0x2b>, /* CPSW_RX_CHAN */
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<0x2d>, /* SAUL_RX_0_CHAN */
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<0x2f>, /* SAUL_RX_1_CHAN */
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<0x31>, /* SAUL_RX_2_CHAN */
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<0x33>, /* SAUL_RX_3_CHAN */
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<0x35>, /* ICSSG_0_RX_CHAN */
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<0x37>; /* ICSSG_1_RX_CHAN */
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ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
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<0x2c>, /* FLOW_CPSW_RX_CHAN */
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<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
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<0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
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<0x36>, /* FLOW_ICSSG_0_RX_CHAN */
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<0x38>; /* FLOW_ICSSG_1_RX_CHAN */
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};
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};
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dmsc: dmsc@44043000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 12>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44043000 0x00 0xfe0>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clocks {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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main_pmx0: pinctrl@f4000 {
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compatible = "pinctrl-single";
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reg = <0x00 0xf4000 0x00 0x2d0>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_conf: syscon@43000000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x00 0x43000000 0x00 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x43000000 0x20000>;
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chipid@14 {
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compatible = "ti,am654-chipid";
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reg = <0x00000014 0x4>;
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};
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phy_gmii_sel: phy@4044 {
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compatible = "ti,am654-phy-gmii-sel";
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reg = <0x4044 0x8>;
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#phy-cells = <1>;
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};
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};
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main_uart0: serial@2800000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 146 0>;
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clock-names = "fclk";
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};
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main_uart1: serial@2810000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 152 0>;
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clock-names = "fclk";
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};
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main_uart2: serial@2820000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02820000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 153 0>;
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clock-names = "fclk";
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};
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main_uart3: serial@2830000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02830000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 154 0>;
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clock-names = "fclk";
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};
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main_uart4: serial@2840000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02840000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 155 0>;
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clock-names = "fclk";
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};
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main_uart5: serial@2850000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02850000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 156 0>;
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clock-names = "fclk";
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};
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main_uart6: serial@2860000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02860000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 158 0>;
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clock-names = "fclk";
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};
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main_i2c0: i2c@20000000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20000000 0x00 0x100>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 102 2>;
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clock-names = "fck";
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};
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main_i2c1: i2c@20010000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20010000 0x00 0x100>;
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interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 103 2>;
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clock-names = "fck";
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};
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main_i2c2: i2c@20020000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20020000 0x00 0x100>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 104 2>;
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clock-names = "fck";
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};
|
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|
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main_i2c3: i2c@20030000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20030000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 105 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_spi0: spi@20100000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x20100000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 141 0>;
|
||||
dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
|
||||
dma-names = "tx0", "rx0";
|
||||
};
|
||||
|
||||
main_spi1: spi@20110000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20110000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 142 0>;
|
||||
};
|
||||
|
||||
main_spi2: spi@20120000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20120000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 143 0>;
|
||||
};
|
||||
|
||||
main_spi3: spi@20130000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20130000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 144 0>;
|
||||
};
|
||||
|
||||
main_spi4: spi@20140000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20140000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 145 0>;
|
||||
};
|
||||
|
||||
sdhci0: mmc@fa10000 {
|
||||
compatible = "ti,am64-sdhci-8bit";
|
||||
reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
ti,trm-icp = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-mmc-hs = <0x0>;
|
||||
ti,otap-del-sel-ddr52 = <0x6>;
|
||||
ti,otap-del-sel-hs200 = <0x7>;
|
||||
ti,otap-del-sel-hs400 = <0x4>;
|
||||
};
|
||||
|
||||
sdhci1: mmc@fa00000 {
|
||||
compatible = "ti,am64-sdhci-4bit";
|
||||
reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
ti,trm-icp = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0xf>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-sdr104 = <0x6>;
|
||||
ti,otap-del-sel-ddr50 = <0x9>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
};
|
||||
|
||||
cpsw3g: ethernet@8000000 {
|
||||
compatible = "ti,am642-cpsw-nuss";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x0 0x8000000 0x0 0x200000>;
|
||||
reg-names = "cpsw_nuss";
|
||||
ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
|
||||
clocks = <&k3_clks 13 0>;
|
||||
assigned-clocks = <&k3_clks 13 1>;
|
||||
assigned-clock-parents = <&k3_clks 13 9>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
dmas = <&main_pktdma 0xC500 15>,
|
||||
<&main_pktdma 0xC501 15>,
|
||||
<&main_pktdma 0xC502 15>,
|
||||
<&main_pktdma 0xC503 15>,
|
||||
<&main_pktdma 0xC504 15>,
|
||||
<&main_pktdma 0xC505 15>,
|
||||
<&main_pktdma 0xC506 15>,
|
||||
<&main_pktdma 0xC507 15>,
|
||||
<&main_pktdma 0x4500 15>;
|
||||
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
|
||||
"tx7", "rx";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpsw_port1: port@1 {
|
||||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
mac-address = [00 00 de ad be ef];
|
||||
};
|
||||
|
||||
cpsw_port2: port@2 {
|
||||
reg = <2>;
|
||||
ti,mac-only;
|
||||
label = "port2";
|
||||
phys = <&phy_gmii_sel 2>;
|
||||
mac-address = [00 01 de ad be ef];
|
||||
};
|
||||
};
|
||||
|
||||
cpsw3g_mdio: mdio@f00 {
|
||||
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
||||
reg = <0x0 0xf00 0x0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 13 0>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
|
||||
cpts@3d000 {
|
||||
compatible = "ti,j721e-cpts";
|
||||
reg = <0x0 0x3d000 0x0 0x400>;
|
||||
clocks = <&k3_clks 13 1>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-ext-ts-inputs = <4>;
|
||||
ti,cpts-periodic-outputs = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
main_gpio0: gpio@600000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00600000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <77 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 3 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 4 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 5 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 6 IRQ_TYPE_EDGE_RISING>,
|
||||
<77 7 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 77 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_gpio1: gpio@601000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00601000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <78 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 3 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 4 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 5 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 6 IRQ_TYPE_EDGE_RISING>,
|
||||
<78 7 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 78 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_i2c0: i2c@20000000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x20000000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 102 2>;
|
||||
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_i2c1: i2c@20010000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x20010000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 103 2>;
|
||||
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_i2c2: i2c@20020000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20020000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 104 2>;
|
||||
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_i2c3: i2c@20030000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20030000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 105 2>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
};
|
||||
76
arch/arm/dts/k3-am64-mcu.dtsi
Normal file
76
arch/arm/dts/k3-am64-mcu.dtsi
Normal file
@@ -0,0 +1,76 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM64 SoC Family MCU Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu {
|
||||
mcu_uart0: serial@4a00000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 149 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
mcu_uart1: serial@4a10000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a10000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 160 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
mcu_i2c0: i2c@4900000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x04900000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 106 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
mcu_i2c1: i2c@4910000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x04910000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 107 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
mcu_spi0: spi@4b00000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x04b00000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 147 0>;
|
||||
};
|
||||
|
||||
mcu_spi1: spi@4b10000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x04b10000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 148 0>;
|
||||
};
|
||||
};
|
||||
2190
arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi
Normal file
2190
arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
107
arch/arm/dts/k3-am64.dtsi
Normal file
107
arch/arm/dts/k3-am64.dtsi
Normal file
@@ -0,0 +1,107 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM642 SoC Family
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 AM642 SoC";
|
||||
compatible = "ti,am642";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &mcu_uart0;
|
||||
serial1 = &mcu_uart1;
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart1;
|
||||
serial4 = &main_uart2;
|
||||
serial5 = &main_uart3;
|
||||
serial6 = &main_uart4;
|
||||
serial7 = &main_uart5;
|
||||
serial8 = &main_uart6;
|
||||
i2c0 = &main_i2c0;
|
||||
i2c1 = &main_i2c1;
|
||||
ethernet0 = &cpsw_port1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
};
|
||||
|
||||
chosen { };
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a53_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@f4000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
|
||||
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
|
||||
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
|
||||
<0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
|
||||
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
|
||||
<0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
|
||||
<0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
|
||||
<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
|
||||
<0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
|
||||
<0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
|
||||
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
|
||||
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
|
||||
<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
|
||||
<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
|
||||
<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
|
||||
|
||||
/* MCU Domain Range */
|
||||
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
|
||||
|
||||
cbass_mcu: bus@4000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include the peripherals for each bus segments */
|
||||
#include "k3-am64-main.dtsi"
|
||||
#include "k3-am64-mcu.dtsi"
|
||||
99
arch/arm/dts/k3-am642-evm-u-boot.dtsi
Normal file
99
arch/arm/dts/k3-am642-evm-u-boot.dtsi
Normal file
@@ -0,0 +1,99 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
tick-timer = &timer1;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main{
|
||||
u-boot,dm-spl;
|
||||
timer1: timer@2400000 {
|
||||
compatible = "ti,omap5430-timer";
|
||||
reg = <0x0 0x2400000 0x0 0x80>;
|
||||
ti,timer-alwon;
|
||||
clock-frequency = <250000000>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_conf {
|
||||
u-boot,dm-spl;
|
||||
chipid@14 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
|
||||
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&dmss {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&secure_proxy_main {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_pds {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_clks {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_reset {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
reg = <0x0 0x8000000 0x0 0x200000>,
|
||||
<0x0 0x43000200 0x0 0x8>;
|
||||
reg-names = "cpsw_nuss", "mac_efuse";
|
||||
/delete-property/ ranges;
|
||||
|
||||
cpsw-phy-sel@04044 {
|
||||
compatible = "ti,am64-phy-gmii-sel";
|
||||
reg = <0x0 0x43004044 0x0 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
status = "disabled";
|
||||
};
|
||||
339
arch/arm/dts/k3-am642-evm.dts
Normal file
339
arch/arm/dts/k3-am642-evm.dts
Normal file
@@ -0,0 +1,339 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am642.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am642-evm", "ti,am642";
|
||||
model = "Texas Instruments AM642 EVM";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
evm_12v0: fixedregulator-evm12v0 {
|
||||
/* main DC jack */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_12v0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_5v0: fixedregulator-vsys5v0 {
|
||||
/* output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_3v3: fixedregulator-vsys3v3 {
|
||||
/* output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: fixed-regulator-sd {
|
||||
/* TPS2051BD */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vddb: fixedregulator-vddb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vddb_3v3_display";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
label = "am64-evm:red:heartbeat";
|
||||
gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
mdio_mux: mux-controller {
|
||||
compatible = "gpio-mux";
|
||||
#mux-control-cells = <0>;
|
||||
|
||||
mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
mdio-mux-1 {
|
||||
compatible = "mdio-mux-multiplexer";
|
||||
mux-controls = <&mdio_mux>;
|
||||
mdio-parent-bus = <&cpsw3g_mdio>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio@1 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpsw3g_phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
|
||||
AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
|
||||
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
|
||||
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
|
||||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
|
||||
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
mdio1_pins_default: mdio1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
|
||||
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii1_pins_default: rgmii1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
|
||||
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
|
||||
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
|
||||
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
|
||||
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
|
||||
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
|
||||
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
|
||||
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
|
||||
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
|
||||
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii2_pins_default: rgmii2-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
|
||||
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
|
||||
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
|
||||
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
|
||||
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
|
||||
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
|
||||
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
|
||||
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
|
||||
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
|
||||
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
|
||||
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
|
||||
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
||||
/* main_uart1 is reserved for firmware usage */
|
||||
&main_uart1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_uart1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@22 {
|
||||
compatible = "ti,tca6424";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
|
||||
"GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
|
||||
"GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
|
||||
"MMC1_SD_EN", "FSI_FET_SEL",
|
||||
"MCAN0_STB_3V3", "MCAN1_STB_3V3",
|
||||
"CPSW_FET_SEL", "CPSW_FET2_SEL",
|
||||
"PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
|
||||
"GPIO_OLED_RESETn", "VPP_LDO_EN",
|
||||
"TEST_LED1", "TP92", "TP90", "TP88",
|
||||
"TP87", "TP86", "TP89", "TP91";
|
||||
};
|
||||
|
||||
/* osd9616p0899-10 */
|
||||
display@3c {
|
||||
compatible = "solomon,ssd1306fb-i2c";
|
||||
reg = <0x3c>;
|
||||
reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
|
||||
vbat-supply = <&vddb>;
|
||||
solomon,height = <16>;
|
||||
solomon,width = <96>;
|
||||
solomon,com-seq;
|
||||
solomon,com-invdir;
|
||||
solomon,page-offset = <0>;
|
||||
solomon,prechargep1 = <2>;
|
||||
solomon,prechargep2 = <13>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_i2c1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default
|
||||
&rgmii1_pins_default
|
||||
&rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy3>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
/* emmc */
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
204
arch/arm/dts/k3-am642-r5-evm.dts
Normal file
204
arch/arm/dts/k3-am642-r5-evm.dts
Normal file
@@ -0,0 +1,204 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am642.dtsi"
|
||||
#include "k3-am64-evm-ddr4-1600MTs.dtsi"
|
||||
#include "k3-am64-ddr.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
tick-timer = &timer1;
|
||||
};
|
||||
|
||||
aliases {
|
||||
remoteproc0 = &sysctrler;
|
||||
remoteproc1 = &a53_0;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
a53_0: a53@0 {
|
||||
compatible = "ti,am654-rproc";
|
||||
reg = <0x00 0x00a90000 0x00 0x10>;
|
||||
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
|
||||
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
|
||||
resets = <&k3_reset 135 0>;
|
||||
clocks = <&k3_clks 61 0>;
|
||||
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
|
||||
assigned-clock-parents = <&k3_clks 61 2>;
|
||||
assigned-clock-rates = <200000000>, <1000000000>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-proc-id = <32>;
|
||||
ti,sci-host-id = <10>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
clk_200mhz: dummy-clock-200mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
vtt_supply: vtt-supply {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vtt";
|
||||
regulator-min-microvolt = <0>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
|
||||
states = <0 0x0 3300000 0x1>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
sysctrler: sysctrler {
|
||||
compatible = "ti,am654-system-controller";
|
||||
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
|
||||
mbox-names = "tx", "rx";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
|
||||
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
|
||||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
|
||||
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
|
||||
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
|
||||
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc0_pins_default: main-mmc0-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
|
||||
AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
|
||||
AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
|
||||
AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
|
||||
AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
|
||||
AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
|
||||
AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
|
||||
AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
|
||||
AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
|
||||
AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
|
||||
AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
|
||||
AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
|
||||
>;
|
||||
};
|
||||
|
||||
ddr_vtt_pins_default: ddr-vtt-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
mboxes= <&secure_proxy_main 0>,
|
||||
<&secure_proxy_main 1>,
|
||||
<&secure_proxy_main 0>;
|
||||
mbox-names = "rx", "tx", "notify";
|
||||
ti,host-id = <35>;
|
||||
ti,secure-host;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ clocks;
|
||||
/delete-property/ clock-names;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
};
|
||||
|
||||
&memorycontroller {
|
||||
vtt-supply = <&vtt_supply>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ddr_vtt_pins_default>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
/delete-property/ power-domains;
|
||||
clocks = <&clk_200mhz>;
|
||||
clock-names = "clk_xin";
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
pinctrl-0 = <&main_mmc0_pins_default>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/delete-property/ power-domains;
|
||||
clocks = <&clk_200mhz>;
|
||||
clock-names = "clk_xin";
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
u-boot,dm-spl;
|
||||
/delete-property/ power-domains;
|
||||
};
|
||||
|
||||
/* EEPROM might be read before SYSFW is available */
|
||||
&main_i2c0 {
|
||||
/delete-property/ power-domains;
|
||||
};
|
||||
|
||||
#include "k3-am642-evm-u-boot.dtsi"
|
||||
145
arch/arm/dts/k3-am642-r5-sk.dts
Normal file
145
arch/arm/dts/k3-am642-r5-sk.dts
Normal file
@@ -0,0 +1,145 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am642.dtsi"
|
||||
#include "k3-am64-sk-lp4-1333MTs.dtsi"
|
||||
#include "k3-am64-ddr.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
tick-timer = &timer1;
|
||||
};
|
||||
|
||||
aliases {
|
||||
remoteproc0 = &sysctrler;
|
||||
remoteproc1 = &a53_0;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
a53_0: a53@0 {
|
||||
compatible = "ti,am654-rproc";
|
||||
reg = <0x00 0x00a90000 0x00 0x10>;
|
||||
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
|
||||
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
|
||||
resets = <&k3_reset 135 0>;
|
||||
clocks = <&k3_clks 61 0>;
|
||||
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
|
||||
assigned-clock-parents = <&k3_clks 61 2>;
|
||||
assigned-clock-rates = <200000000>, <1000000000>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-proc-id = <32>;
|
||||
ti,sci-host-id = <10>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
clk_200mhz: dummy-clock-200mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
sysctrler: sysctrler {
|
||||
compatible = "ti,am654-system-controller";
|
||||
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
|
||||
mbox-names = "tx", "rx";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
|
||||
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
|
||||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
|
||||
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
|
||||
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
|
||||
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
|
||||
AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
mboxes= <&secure_proxy_main 0>,
|
||||
<&secure_proxy_main 1>,
|
||||
<&secure_proxy_main 0>;
|
||||
mbox-names = "rx", "tx", "notify";
|
||||
ti,host-id = <35>;
|
||||
ti,secure-host;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ clocks;
|
||||
/delete-property/ clock-names;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/delete-property/ power-domains;
|
||||
clocks = <&clk_200mhz>;
|
||||
clock-names = "clk_xin";
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
};
|
||||
|
||||
#include "k3-am642-sk-u-boot.dtsi"
|
||||
103
arch/arm/dts/k3-am642-sk-u-boot.dtsi
Normal file
103
arch/arm/dts/k3-am642-sk-u-boot.dtsi
Normal file
@@ -0,0 +1,103 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
tick-timer = &timer1;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main{
|
||||
u-boot,dm-spl;
|
||||
timer1: timer@2400000 {
|
||||
compatible = "ti,omap5430-timer";
|
||||
reg = <0x0 0x2400000 0x0 0x80>;
|
||||
ti,timer-alwon;
|
||||
clock-frequency = <250000000>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_conf {
|
||||
u-boot,dm-spl;
|
||||
chipid@14 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
|
||||
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&dmss {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&secure_proxy_main {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_pds {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_clks {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&k3_reset {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&main_mmc1_pins_default {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
reg = <0x0 0x8000000 0x0 0x200000>,
|
||||
<0x0 0x43000200 0x0 0x8>;
|
||||
reg-names = "cpsw_nuss", "mac_efuse";
|
||||
/delete-property/ ranges;
|
||||
|
||||
cpsw-phy-sel@04044 {
|
||||
compatible = "ti,am64-phy-gmii-sel";
|
||||
reg = <0x0 0x43004044 0x0 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
status = "disabled";
|
||||
};
|
||||
156
arch/arm/dts/k3-am642-sk.dts
Normal file
156
arch/arm/dts/k3-am642-sk.dts
Normal file
@@ -0,0 +1,156 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am642.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am642-sk", "ti,am642";
|
||||
model = "Texas Instruments AM642 SK";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
|
||||
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
mdio1_pins_default: mdio1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
|
||||
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii1_pins_default: rgmii1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
|
||||
AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
|
||||
AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
|
||||
AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
|
||||
AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
|
||||
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
|
||||
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
|
||||
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
|
||||
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
|
||||
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii2_pins_default: rgmii2-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
|
||||
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
|
||||
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
|
||||
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
|
||||
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
|
||||
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
|
||||
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
|
||||
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
|
||||
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
|
||||
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
|
||||
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
|
||||
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
/* main_uart1 is reserved for firmware usage */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default
|
||||
&rgmii1_pins_default
|
||||
&rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
65
arch/arm/dts/k3-am642.dtsi
Normal file
65
arch/arm/dts/k3-am642.dtsi
Normal file
@@ -0,0 +1,65 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM642 SoC family in Dual core configuration
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am64.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x40000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
};
|
||||
};
|
||||
@@ -10,6 +10,9 @@ config SOC_K3_AM6
|
||||
config SOC_K3_J721E
|
||||
bool "TI's K3 based J721E SoC Family Support"
|
||||
|
||||
config SOC_K3_AM642
|
||||
bool "TI's K3 based AM642 SoC Family Support"
|
||||
|
||||
endchoice
|
||||
|
||||
config SYS_SOC
|
||||
@@ -19,16 +22,18 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
|
||||
hex
|
||||
default 0x80000 if SOC_K3_AM6
|
||||
default 0x100000 if SOC_K3_J721E
|
||||
default 0x1c0000 if SOC_K3_AM642
|
||||
help
|
||||
Describes the total size of the MCU MSRAM. This doesn't
|
||||
specify the total size of SPL as ROM can use some part
|
||||
of this RAM. Once ROM gives control to SPL then this
|
||||
complete size can be usable.
|
||||
Describes the total size of the MCU or OCMC MSRAM present on
|
||||
the SoC in use. This doesn't specify the total size of SPL as
|
||||
ROM can use some part of this RAM. Once ROM gives control to
|
||||
SPL then this complete size can be usable.
|
||||
|
||||
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
|
||||
hex
|
||||
default 0x58000 if SOC_K3_AM6
|
||||
default 0xc0000 if SOC_K3_J721E
|
||||
default 0x180000 if SOC_K3_AM642
|
||||
help
|
||||
Describes the maximum size of the image that ROM can download
|
||||
from any boot media.
|
||||
@@ -51,6 +56,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
|
||||
hex
|
||||
default 0x41c7fbfc if SOC_K3_AM6
|
||||
default 0x41cffbfc if SOC_K3_J721E
|
||||
default 0x701bebfc if SOC_K3_AM642
|
||||
help
|
||||
Address at which ROM stores the value which determines if SPL
|
||||
is booted up by primary boot media or secondary boot media.
|
||||
@@ -142,5 +148,6 @@ config SYS_K3_SPL_ATF
|
||||
after SPL from R5.
|
||||
|
||||
source "board/ti/am65x/Kconfig"
|
||||
source "board/ti/am64x/Kconfig"
|
||||
source "board/ti/j721e/Kconfig"
|
||||
endif
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
|
||||
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
|
||||
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
|
||||
obj-$(CONFIG_ARM64) += arm64-mmu.o
|
||||
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
|
||||
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
|
||||
|
||||
315
arch/arm/mach-k3/am642_init.c
Normal file
315
arch/arm/mach-k3/am642_init.c
Normal file
@@ -0,0 +1,315 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* AM642: SoC specific initialization
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Keerthy <j-keerthy@ti.com>
|
||||
* Dave Gerlach <d-gerlach@ti.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <spl.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/sysfw-loader.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include "common.h"
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <linux/soc/ti/ti_sci_protocol.h>
|
||||
#include <dm.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <dm/pinctrl.h>
|
||||
#include <mmc.h>
|
||||
#include <dm/root.h>
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
|
||||
static void ctrl_mmr_unlock(void)
|
||||
{
|
||||
/* Unlock all PADCFG_MMR1 module registers */
|
||||
mmr_unlock(PADCFG_MMR1_BASE, 1);
|
||||
|
||||
/* Unlock all CTRL_MMR0 module registers */
|
||||
mmr_unlock(CTRL_MMR0_BASE, 0);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 1);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 2);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 3);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 5);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 6);
|
||||
}
|
||||
|
||||
/*
|
||||
* This uninitialized global variable would normal end up in the .bss section,
|
||||
* but the .bss is cleared between writing and reading this variable, so move
|
||||
* it to the .data section.
|
||||
*/
|
||||
u32 bootindex __section(".data");
|
||||
static struct rom_extended_boot_data bootdata __section(.data);
|
||||
|
||||
static void store_boot_info_from_rom(void)
|
||||
{
|
||||
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
|
||||
memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
|
||||
sizeof(struct rom_extended_boot_data));
|
||||
}
|
||||
|
||||
#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
|
||||
void k3_mmc_stop_clock(void)
|
||||
{
|
||||
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
|
||||
struct mmc *mmc = find_mmc_device(0);
|
||||
|
||||
if (!mmc)
|
||||
return;
|
||||
|
||||
mmc->saved_clock = mmc->clock;
|
||||
mmc_set_clock(mmc, 0, true);
|
||||
}
|
||||
}
|
||||
|
||||
void k3_mmc_restart_clock(void)
|
||||
{
|
||||
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
|
||||
struct mmc *mmc = find_mmc_device(0);
|
||||
|
||||
if (!mmc)
|
||||
return;
|
||||
|
||||
mmc_set_clock(mmc, mmc->saved_clock, false);
|
||||
}
|
||||
}
|
||||
#else
|
||||
void k3_mmc_stop_clock(void) {}
|
||||
void k3_mmc_restart_clock(void) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_OF_LIST
|
||||
void do_dt_magic(void)
|
||||
{
|
||||
int ret, rescan;
|
||||
|
||||
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
|
||||
do_board_detect();
|
||||
|
||||
/*
|
||||
* Board detection has been done.
|
||||
* Let us see if another dtb wouldn't be a better match
|
||||
* for our board
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_CPU_V7R)) {
|
||||
ret = fdtdec_resetup(&rescan);
|
||||
if (!ret && rescan) {
|
||||
dm_uninit();
|
||||
dm_init_and_scan(true);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
#if defined(CONFIG_K3_LOAD_SYSFW)
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_V7R)
|
||||
setup_k3_mpu_regions();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Cannot delay this further as there is a chance that
|
||||
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
|
||||
*/
|
||||
store_boot_info_from_rom();
|
||||
|
||||
ctrl_mmr_unlock();
|
||||
|
||||
/* Init DM early */
|
||||
spl_early_init();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
do_dt_magic();
|
||||
|
||||
#if defined(CONFIG_K3_LOAD_SYSFW)
|
||||
/*
|
||||
* Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue
|
||||
* regardless of the result of pinctrl. Do this without probing the
|
||||
* device, but instead by searching the device that would request the
|
||||
* given sequence number if probed. The UART will be used by the system
|
||||
* firmware (SYSFW) image for various purposes and SYSFW depends on us
|
||||
* to initialize its pin settings.
|
||||
*/
|
||||
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
|
||||
if (!ret)
|
||||
pinctrl_select_state(dev, "default");
|
||||
|
||||
/*
|
||||
* Load, start up, and configure system controller firmware.
|
||||
* This will determine whether or not ROM has already loaded
|
||||
* system firmware and if so, will only perform needed config
|
||||
* and not attempt to load firmware again.
|
||||
*/
|
||||
k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), k3_mmc_stop_clock,
|
||||
k3_mmc_restart_clock);
|
||||
#endif
|
||||
|
||||
/* Output System Firmware version info */
|
||||
k3_sysfw_print_ver();
|
||||
|
||||
#if defined(CONFIG_K3_AM64_DDRSS)
|
||||
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
|
||||
if (ret)
|
||||
panic("DRAM init failed: %d\n", ret);
|
||||
#endif
|
||||
}
|
||||
|
||||
u32 spl_boot_mode(const u32 boot_device)
|
||||
{
|
||||
switch (boot_device) {
|
||||
case BOOT_DEVICE_MMC1:
|
||||
return MMCSD_MODE_EMMCBOOT;
|
||||
|
||||
case BOOT_DEVICE_MMC2:
|
||||
return MMCSD_MODE_FS;
|
||||
|
||||
default:
|
||||
return MMCSD_MODE_RAW;
|
||||
}
|
||||
}
|
||||
|
||||
static u32 __get_backup_bootmedia(u32 main_devstat)
|
||||
{
|
||||
u32 bkup_bootmode =
|
||||
(main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
|
||||
MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
|
||||
u32 bkup_bootmode_cfg =
|
||||
(main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
|
||||
MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
|
||||
|
||||
switch (bkup_bootmode) {
|
||||
case BACKUP_BOOT_DEVICE_UART:
|
||||
return BOOT_DEVICE_UART;
|
||||
|
||||
case BACKUP_BOOT_DEVICE_USB:
|
||||
return BOOT_DEVICE_USB;
|
||||
|
||||
case BACKUP_BOOT_DEVICE_ETHERNET:
|
||||
return BOOT_DEVICE_ETHERNET;
|
||||
|
||||
case BACKUP_BOOT_DEVICE_MMC:
|
||||
if (bkup_bootmode_cfg)
|
||||
return BOOT_DEVICE_MMC2;
|
||||
return BOOT_DEVICE_MMC1;
|
||||
|
||||
case BACKUP_BOOT_DEVICE_SPI:
|
||||
return BOOT_DEVICE_SPI;
|
||||
|
||||
case BACKUP_BOOT_DEVICE_I2C:
|
||||
return BOOT_DEVICE_I2C;
|
||||
};
|
||||
|
||||
return BOOT_DEVICE_RAM;
|
||||
}
|
||||
|
||||
static u32 __get_primary_bootmedia(u32 main_devstat)
|
||||
{
|
||||
u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
|
||||
MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
|
||||
u32 bootmode_cfg =
|
||||
(main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
|
||||
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
|
||||
|
||||
switch (bootmode) {
|
||||
case BOOT_DEVICE_OSPI:
|
||||
fallthrough;
|
||||
case BOOT_DEVICE_QSPI:
|
||||
fallthrough;
|
||||
case BOOT_DEVICE_XSPI:
|
||||
fallthrough;
|
||||
case BOOT_DEVICE_SPI:
|
||||
return BOOT_DEVICE_SPI;
|
||||
|
||||
case BOOT_DEVICE_ETHERNET_RGMII:
|
||||
fallthrough;
|
||||
case BOOT_DEVICE_ETHERNET_RMII:
|
||||
return BOOT_DEVICE_ETHERNET;
|
||||
|
||||
case BOOT_DEVICE_EMMC:
|
||||
return BOOT_DEVICE_MMC1;
|
||||
|
||||
case BOOT_DEVICE_MMC:
|
||||
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
|
||||
MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
|
||||
return BOOT_DEVICE_MMC2;
|
||||
return BOOT_DEVICE_MMC1;
|
||||
|
||||
case BOOT_DEVICE_NOBOOT:
|
||||
return BOOT_DEVICE_RAM;
|
||||
}
|
||||
|
||||
return bootmode;
|
||||
}
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
|
||||
|
||||
if (bootindex == K3_PRIMARY_BOOTMODE)
|
||||
return __get_primary_bootmedia(devstat);
|
||||
else
|
||||
return __get_backup_bootmedia(devstat);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_K3_SPL_ATF)
|
||||
|
||||
#define AM64X_DEV_RTI8 127
|
||||
#define AM64X_DEV_RTI9 128
|
||||
#define AM64X_DEV_R5FSS0_CORE0 121
|
||||
#define AM64X_DEV_R5FSS0_CORE1 122
|
||||
|
||||
void release_resources_for_core_shutdown(void)
|
||||
{
|
||||
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
|
||||
struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
|
||||
struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
|
||||
int ret;
|
||||
u32 i;
|
||||
|
||||
const u32 put_device_ids[] = {
|
||||
AM64X_DEV_RTI9,
|
||||
AM64X_DEV_RTI8,
|
||||
};
|
||||
|
||||
/* Iterate through list of devices to put (shutdown) */
|
||||
for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
|
||||
u32 id = put_device_ids[i];
|
||||
|
||||
ret = dev_ops->put_device(ti_sci, id);
|
||||
if (ret)
|
||||
panic("Failed to put device %u (%d)\n", id, ret);
|
||||
}
|
||||
|
||||
const u32 put_core_ids[] = {
|
||||
AM64X_DEV_R5FSS0_CORE1,
|
||||
AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
|
||||
};
|
||||
|
||||
/* Iterate through list of cores to put (shutdown) */
|
||||
for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
|
||||
u32 id = put_core_ids[i];
|
||||
|
||||
/*
|
||||
* Queue up the core shutdown request. Note that this call
|
||||
* needs to be followed up by an actual invocation of an WFE
|
||||
* or WFI CPU instruction.
|
||||
*/
|
||||
ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
|
||||
if (ret)
|
||||
panic("Failed sending core %u shutdown message (%d)\n",
|
||||
id, ret);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@@ -180,3 +180,44 @@ struct mm_region *mem_map = j7200_mem_map;
|
||||
#endif /* CONFIG_TARGET_J7200_A72_EVM */
|
||||
|
||||
#endif /* CONFIG_SOC_K3_J721E */
|
||||
|
||||
#ifdef CONFIG_SOC_K3_AM642
|
||||
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
|
||||
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
|
||||
|
||||
/* ToDo: Add 64bit IO */
|
||||
struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
|
||||
{
|
||||
.virt = 0x0UL,
|
||||
.phys = 0x0UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
.virt = 0x80000000UL,
|
||||
.phys = 0x80000000UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0x880000000UL,
|
||||
.phys = 0x880000000UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0x500000000UL,
|
||||
.phys = 0x500000000UL,
|
||||
.size = 0x400000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = am64_mem_map;
|
||||
#endif /* CONFIG_SOC_K3_AM642 */
|
||||
|
||||
55
arch/arm/mach-k3/include/mach/am64_hardware.h
Normal file
55
arch/arm/mach-k3/include/mach/am64_hardware.h
Normal file
@@ -0,0 +1,55 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* K3: AM64 SoC definitions, structures etc.
|
||||
*
|
||||
* (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
#ifndef __ASM_ARCH_AM64_HARDWARE_H
|
||||
#define __ASM_ARCH_AM64_HARDWARE_H
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#define CTRL_MMR0_BASE 0x43000000
|
||||
#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
|
||||
|
||||
#define PADCFG_MMR1_BASE 0xf0000
|
||||
|
||||
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078
|
||||
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
|
||||
|
||||
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK 0x00000380
|
||||
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
|
||||
|
||||
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK 0x00001c00
|
||||
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
|
||||
|
||||
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK 0x00002000
|
||||
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
|
||||
|
||||
/* After the cfg mask and shifts have been applied */
|
||||
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
|
||||
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04
|
||||
|
||||
/*
|
||||
* The CTRL_MMR and PADCFG_MMR memory space is divided into several
|
||||
* equally-spaced partitions, so defining the partition size allows us to
|
||||
* determine register addresses common to those partitions.
|
||||
*/
|
||||
#define CTRL_MMR0_PARTITION_SIZE 0x4000
|
||||
|
||||
/*
|
||||
* CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions.
|
||||
*/
|
||||
#define CTRLMMR_LOCK_KICK0 0x01008
|
||||
#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
|
||||
#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
|
||||
#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
|
||||
#define CTRLMMR_LOCK_KICK1 0x0100c
|
||||
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
|
||||
|
||||
#define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00
|
||||
|
||||
/* Use Last 1K as Scratch pad */
|
||||
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x701bfc00
|
||||
|
||||
#endif /* __ASM_ARCH_DRA8_HARDWARE_H */
|
||||
44
arch/arm/mach-k3/include/mach/am64_spl.h
Normal file
44
arch/arm/mach-k3/include/mach/am64_spl.h
Normal file
@@ -0,0 +1,44 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Keerthy <j-keerthy@ti.com>
|
||||
*/
|
||||
#ifndef _ASM_ARCH_AM64_SPL_H_
|
||||
#define _ASM_ARCH_AM64_SPL_H_
|
||||
|
||||
/* Primary BootMode devices */
|
||||
#define BOOT_DEVICE_RAM 0x00
|
||||
#define BOOT_DEVICE_OSPI 0x01
|
||||
#define BOOT_DEVICE_QSPI 0x02
|
||||
#define BOOT_DEVICE_SPI 0x03
|
||||
#define BOOT_DEVICE_ETHERNET 0x04
|
||||
#define BOOT_DEVICE_ETHERNET_RGMII 0x04
|
||||
#define BOOT_DEVICE_ETHERNET_RMII 0x05
|
||||
#define BOOT_DEVICE_I2C 0x06
|
||||
#define BOOT_DEVICE_UART 0x07
|
||||
#define BOOT_DEVICE_MMC 0x08
|
||||
#define BOOT_DEVICE_EMMC 0x09
|
||||
|
||||
#define BOOT_DEVICE_USB 0x0A
|
||||
#define BOOT_DEVICE_GPMC_NOR 0x0C
|
||||
#define BOOT_DEVICE_PCIE 0x0D
|
||||
#define BOOT_DEVICE_XSPI 0x0E
|
||||
|
||||
#define BOOT_DEVICE_NOBOOT 0x0F
|
||||
|
||||
#define BOOT_DEVICE_MMC2 0x08
|
||||
#define BOOT_DEVICE_MMC1 0x09
|
||||
/* INVALID */
|
||||
#define BOOT_DEVICE_MMC2_2 0x1F
|
||||
|
||||
/* Backup BootMode devices */
|
||||
#define BACKUP_BOOT_DEVICE_USB 0x01
|
||||
#define BACKUP_BOOT_DEVICE_UART 0x03
|
||||
#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
|
||||
#define BACKUP_BOOT_DEVICE_MMC 0x05
|
||||
#define BACKUP_BOOT_DEVICE_SPI 0x06
|
||||
#define BACKUP_BOOT_DEVICE_I2C 0x07
|
||||
|
||||
#define K3_PRIMARY_BOOTMODE 0x0
|
||||
|
||||
#endif
|
||||
@@ -14,6 +14,10 @@
|
||||
#include "j721e_hardware.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_K3_AM642
|
||||
#include "am64_hardware.h"
|
||||
#endif
|
||||
|
||||
/* Assuming these addresses and definitions stay common across K3 devices */
|
||||
#define CTRLMMR_WKUP_JTAG_ID 0x43000014
|
||||
#define JTAG_ID_VARIANT_SHIFT 28
|
||||
|
||||
@@ -13,4 +13,8 @@
|
||||
#ifdef CONFIG_SOC_K3_J721E
|
||||
#include "j721e_spl.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_K3_AM642
|
||||
#include "am64_spl.h"
|
||||
#endif
|
||||
#endif /* _ASM_ARCH_SPL_H_ */
|
||||
|
||||
Reference in New Issue
Block a user