Merge branch 'Makefile' of git://git.denx.de/u-boot-arm
This commit is contained in:
Wolfgang Denk
46
drivers/net/phy/Makefile
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46
drivers/net/phy/Makefile
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#
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# (C) Copyright 2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB := $(obj)libphy.a
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COBJS-$(CONFIG_BITBANGMII) += miiphybb.o
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COBJS := $(COBJS-y)
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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all: $(LIB)
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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235
drivers/net/phy/miiphybb.c
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235
drivers/net/phy/miiphybb.c
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/*
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* (C) Copyright 2001
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* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This provides a bit-banged interface to the ethernet MII management
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* channel.
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*/
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#include <common.h>
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#include <ioports.h>
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#include <ppc_asm.tmpl>
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/*****************************************************************************
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*
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* Utility to send the preamble, address, and register (common to read
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* and write).
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*/
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static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
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{
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int j; /* counter */
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#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
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volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
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#endif
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/*
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* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
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* The IEEE spec says this is a PHY optional requirement. The AMD
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* 79C874 requires one after power up and one after a MII communications
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* error. This means that we are doing more preambles than we need,
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* but it is safer and will be much more robust.
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*/
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MDIO_ACTIVE;
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MDIO (1);
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for (j = 0; j < 32; j++) {
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MDC (0);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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}
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/* send the start bit (01) and the read opcode (10) or write (10) */
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MDC (0);
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MDIO (0);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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MDC (0);
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MDIO (1);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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MDC (0);
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MDIO (read);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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MDC (0);
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MDIO (!read);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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/* send the PHY address */
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for (j = 0; j < 5; j++) {
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MDC (0);
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if ((addr & 0x10) == 0) {
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MDIO (0);
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} else {
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MDIO (1);
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}
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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addr <<= 1;
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}
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/* send the register address */
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for (j = 0; j < 5; j++) {
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MDC (0);
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if ((reg & 0x10) == 0) {
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MDIO (0);
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} else {
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MDIO (1);
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}
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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reg <<= 1;
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}
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}
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/*****************************************************************************
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*
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* Read a MII PHY register.
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*
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* Returns:
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* 0 on success
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*/
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int bb_miiphy_read (char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value)
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{
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short rdreg; /* register working value */
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int j; /* counter */
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#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
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volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
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#endif
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miiphy_pre (1, addr, reg);
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/* tri-state our MDIO I/O pin so we can read */
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MDC (0);
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MDIO_TRISTATE;
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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/* check the turnaround bit: the PHY should be driving it to zero */
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if (MDIO_READ != 0) {
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/* puts ("PHY didn't drive TA low\n"); */
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for (j = 0; j < 32; j++) {
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MDC (0);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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}
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return (-1);
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}
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MDC (0);
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MIIDELAY;
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/* read 16 bits of register data, MSB first */
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rdreg = 0;
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for (j = 0; j < 16; j++) {
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MDC (1);
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MIIDELAY;
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rdreg <<= 1;
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rdreg |= MDIO_READ;
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MDC (0);
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MIIDELAY;
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}
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MDC (1);
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MIIDELAY;
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MDC (0);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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*value = rdreg;
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#ifdef DEBUG
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printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
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#endif
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return 0;
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}
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/*****************************************************************************
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*
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* Write a MII PHY register.
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*
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* Returns:
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* 0 on success
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*/
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int bb_miiphy_write (char *devname, unsigned char addr,
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unsigned char reg, unsigned short value)
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{
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int j; /* counter */
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#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
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volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
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#endif
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miiphy_pre (0, addr, reg);
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/* send the turnaround (10) */
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MDC (0);
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MDIO (1);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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MDC (0);
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MDIO (0);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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/* write 16 bits of register data, MSB first */
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for (j = 0; j < 16; j++) {
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MDC (0);
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if ((value & 0x00008000) == 0) {
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MDIO (0);
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} else {
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MDIO (1);
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}
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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value <<= 1;
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}
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/*
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* Tri-state the MDIO line.
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*/
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MDIO_TRISTATE;
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MDC (0);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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return 0;
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}
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