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Merge branch 'Makefile' of git://git.denx.de/u-boot-arm

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This commit is contained in:
Wolfgang Denk
2008-09-01 00:16:29 +02:00
parent a13b2d9379 08ab4e1780
commit e99e9575bb
53 changed files with 692 additions and 1121 deletions
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1
drivers/i2c/Makefile
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@@ -29,6 +29,7 @@ COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
COBJS := $(COBJS-y)

423
drivers/i2c/soft_i2c.c Normal file
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@@ -0,0 +1,423 @@
/*
* (C) Copyright 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This has been changed substantially by Gerald Van Baren, Custom IDEAS,
* vanbaren@cideas.com. It was heavily influenced by LiMon, written by
* Neil Russell.
*/
#include <common.h>
#ifdef CONFIG_MPC8260 /* only valid for MPC8260 */
#include <ioports.h>
#endif
#ifdef CONFIG_AT91RM9200 /* need this for the at91rm9200 */
#include <asm/io.h>
#include <asm/arch/hardware.h>
#endif
#ifdef CONFIG_IXP425 /* only valid for IXP425 */
#include <asm/arch/ixp425.h>
#endif
#ifdef CONFIG_LPC2292
#include <asm/arch/hardware.h>
#endif
#include <i2c.h>
/* #define DEBUG_I2C */
#ifdef DEBUG_I2C
DECLARE_GLOBAL_DATA_PTR;
#endif
/*-----------------------------------------------------------------------
* Definitions
*/
#define RETRIES 0
#define I2C_ACK 0 /* PD_SDA level to ack a byte */
#define I2C_NOACK 1 /* PD_SDA level to noack a byte */
#ifdef DEBUG_I2C
#define PRINTD(fmt,args...) do { \
if (gd->have_console) \
printf (fmt ,##args); \
} while (0)
#else
#define PRINTD(fmt,args...)
#endif
/*-----------------------------------------------------------------------
* Local functions
*/
static void send_reset (void);
static void send_start (void);
static void send_stop (void);
static void send_ack (int);
static int write_byte (uchar byte);
static uchar read_byte (int);
/*-----------------------------------------------------------------------
* Send a reset sequence consisting of 9 clocks with the data signal high
* to clock any confused device back into an idle state. Also send a
* <stop> at the end of the sequence for belts & suspenders.
*/
static void send_reset(void)
{
#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
#endif
#ifdef CONFIG_8xx
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
int j;
I2C_SCL(1);
I2C_SDA(1);
#ifdef I2C_INIT
I2C_INIT;
#endif
I2C_TRISTATE;
for(j = 0; j < 9; j++) {
I2C_SCL(0);
I2C_DELAY;
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
I2C_DELAY;
}
send_stop();
I2C_TRISTATE;
}
/*-----------------------------------------------------------------------
* START: High -> Low on SDA while SCL is High
*/
static void send_start(void)
{
#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
#endif
#ifdef CONFIG_8xx
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
I2C_DELAY;
I2C_SDA(1);
I2C_ACTIVE;
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
I2C_SDA(0);
I2C_DELAY;
}
/*-----------------------------------------------------------------------
* STOP: Low -> High on SDA while SCL is High
*/
static void send_stop(void)
{
#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
#endif
#ifdef CONFIG_8xx
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
I2C_SCL(0);
I2C_DELAY;
I2C_SDA(0);
I2C_ACTIVE;
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
I2C_SDA(1);
I2C_DELAY;
I2C_TRISTATE;
}
/*-----------------------------------------------------------------------
* ack should be I2C_ACK or I2C_NOACK
*/
static void send_ack(int ack)
{
#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
#endif
#ifdef CONFIG_8xx
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
I2C_SCL(0);
I2C_DELAY;
I2C_ACTIVE;
I2C_SDA(ack);
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
I2C_DELAY;
I2C_SCL(0);
I2C_DELAY;
}
/*-----------------------------------------------------------------------
* Send 8 bits and look for an acknowledgement.
*/
static int write_byte(uchar data)
{
#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
#endif
#ifdef CONFIG_8xx
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
int j;
int nack;
I2C_ACTIVE;
for(j = 0; j < 8; j++) {
I2C_SCL(0);
I2C_DELAY;
I2C_SDA(data & 0x80);
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
I2C_DELAY;
data <<= 1;
}
/*
* Look for an <ACK>(negative logic) and return it.
*/
I2C_SCL(0);
I2C_DELAY;
I2C_SDA(1);
I2C_TRISTATE;
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
I2C_DELAY;
nack = I2C_READ;
I2C_SCL(0);
I2C_DELAY;
I2C_ACTIVE;
return(nack); /* not a nack is an ack */
}
/*-----------------------------------------------------------------------
* if ack == I2C_ACK, ACK the byte so can continue reading, else
* send I2C_NOACK to end the read.
*/
static uchar read_byte(int ack)
{
#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
#endif
#ifdef CONFIG_8xx
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
int data;
int j;
/*
* Read 8 bits, MSB first.
*/
I2C_TRISTATE;
I2C_SDA(1);
data = 0;
for(j = 0; j < 8; j++) {
I2C_SCL(0);
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
data <<= 1;
data |= I2C_READ;
I2C_DELAY;
}
send_ack(ack);
return(data);
}
/*=====================================================================*/
/* Public Functions */
/*=====================================================================*/
/*-----------------------------------------------------------------------
* Initialization
*/
void i2c_init (int speed, int slaveaddr)
{
/*
* WARNING: Do NOT save speed in a static variable: if the
* I2C routines are called before RAM is initialized (to read
* the DIMM SPD, for instance), RAM won't be usable and your
* system will crash.
*/
send_reset ();
}
/*-----------------------------------------------------------------------
* Probe to see if a chip is present. Also good for checking for the
* completion of EEPROM writes since the chip stops responding until
* the write completes (typically 10mSec).
*/
int i2c_probe(uchar addr)
{
int rc;
/*
* perform 1 byte write transaction with just address byte
* (fake write)
*/
send_start();
rc = write_byte ((addr << 1) | 0);
send_stop();
return (rc ? 1 : 0);
}
/*-----------------------------------------------------------------------
* Read bytes
*/
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
int shift;
PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
chip, addr, alen, buffer, len);
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
* address and the extra bits end up in the "chip address"
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
* four 256 byte chips.
*
* Note that we consider the length of the address field to
* still be one byte because the extra address bits are
* hidden in the chip address.
*/
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
chip, addr);
#endif
/*
* Do the addressing portion of a write cycle to set the
* chip's address pointer. If the address length is zero,
* don't do the normal write cycle to set the address pointer,
* there is no address pointer in this chip.
*/
send_start();
if(alen > 0) {
if(write_byte(chip << 1)) { /* write cycle */
send_stop();
PRINTD("i2c_read, no chip responded %02X\n", chip);
return(1);
}
shift = (alen-1) * 8;
while(alen-- > 0) {
if(write_byte(addr >> shift)) {
PRINTD("i2c_read, address not <ACK>ed\n");
return(1);
}
shift -= 8;
}
send_stop(); /* reportedly some chips need a full stop */
send_start();
}
/*
* Send the chip address again, this time for a read cycle.
* Then read the data. On the last byte, we do a NACK instead
* of an ACK(len == 0) to terminate the read.
*/
write_byte((chip << 1) | 1); /* read cycle */
while(len-- > 0) {
*buffer++ = read_byte(len == 0);
}
send_stop();
return(0);
}
/*-----------------------------------------------------------------------
* Write bytes
*/
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
int shift, failures = 0;
PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
chip, addr, alen, buffer, len);
send_start();
if(write_byte(chip << 1)) { /* write cycle */
send_stop();
PRINTD("i2c_write, no chip responded %02X\n", chip);
return(1);
}
shift = (alen-1) * 8;
while(alen-- > 0) {
if(write_byte(addr >> shift)) {
PRINTD("i2c_write, address not <ACK>ed\n");
return(1);
}
shift -= 8;
}
while(len-- > 0) {
if(write_byte(*buffer++)) {
failures++;
}
}
send_stop();
return(failures);
}
/*-----------------------------------------------------------------------
* Read a register
*/
uchar i2c_reg_read(uchar i2c_addr, uchar reg)
{
uchar buf;
i2c_read(i2c_addr, reg, 1, &buf, 1);
return(buf);
}
/*-----------------------------------------------------------------------
* Write a register
*/
void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
{
i2c_write(i2c_addr, reg, 1, &val, 1);
}

46
drivers/net/phy/Makefile Normal file
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@@ -0,0 +1,46 @@
#
# (C) Copyright 2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libphy.a
COBJS-$(CONFIG_BITBANGMII) += miiphybb.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

235
drivers/net/phy/miiphybb.c Normal file
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@@ -0,0 +1,235 @@
/*
* (C) Copyright 2001
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This provides a bit-banged interface to the ethernet MII management
* channel.
*/
#include <common.h>
#include <ioports.h>
#include <ppc_asm.tmpl>
/*****************************************************************************
*
* Utility to send the preamble, address, and register (common to read
* and write).
*/
static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
{
int j; /* counter */
#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
#endif
/*
* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
* The IEEE spec says this is a PHY optional requirement. The AMD
* 79C874 requires one after power up and one after a MII communications
* error. This means that we are doing more preambles than we need,
* but it is safer and will be much more robust.
*/
MDIO_ACTIVE;
MDIO (1);
for (j = 0; j < 32; j++) {
MDC (0);
MIIDELAY;
MDC (1);
MIIDELAY;
}
/* send the start bit (01) and the read opcode (10) or write (10) */
MDC (0);
MDIO (0);
MIIDELAY;
MDC (1);
MIIDELAY;
MDC (0);
MDIO (1);
MIIDELAY;
MDC (1);
MIIDELAY;
MDC (0);
MDIO (read);
MIIDELAY;
MDC (1);
MIIDELAY;
MDC (0);
MDIO (!read);
MIIDELAY;
MDC (1);
MIIDELAY;
/* send the PHY address */
for (j = 0; j < 5; j++) {
MDC (0);
if ((addr & 0x10) == 0) {
MDIO (0);
} else {
MDIO (1);
}
MIIDELAY;
MDC (1);
MIIDELAY;
addr <<= 1;
}
/* send the register address */
for (j = 0; j < 5; j++) {
MDC (0);
if ((reg & 0x10) == 0) {
MDIO (0);
} else {
MDIO (1);
}
MIIDELAY;
MDC (1);
MIIDELAY;
reg <<= 1;
}
}
/*****************************************************************************
*
* Read a MII PHY register.
*
* Returns:
* 0 on success
*/
int bb_miiphy_read (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
int j; /* counter */
#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
#endif
miiphy_pre (1, addr, reg);
/* tri-state our MDIO I/O pin so we can read */
MDC (0);
MDIO_TRISTATE;
MIIDELAY;
MDC (1);
MIIDELAY;
/* check the turnaround bit: the PHY should be driving it to zero */
if (MDIO_READ != 0) {
/* puts ("PHY didn't drive TA low\n"); */
for (j = 0; j < 32; j++) {
MDC (0);
MIIDELAY;
MDC (1);
MIIDELAY;
}
return (-1);
}
MDC (0);
MIIDELAY;
/* read 16 bits of register data, MSB first */
rdreg = 0;
for (j = 0; j < 16; j++) {
MDC (1);
MIIDELAY;
rdreg <<= 1;
rdreg |= MDIO_READ;
MDC (0);
MIIDELAY;
}
MDC (1);
MIIDELAY;
MDC (0);
MIIDELAY;
MDC (1);
MIIDELAY;
*value = rdreg;
#ifdef DEBUG
printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
#endif
return 0;
}
/*****************************************************************************
*
* Write a MII PHY register.
*
* Returns:
* 0 on success
*/
int bb_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
int j; /* counter */
#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
#endif
miiphy_pre (0, addr, reg);
/* send the turnaround (10) */
MDC (0);
MDIO (1);
MIIDELAY;
MDC (1);
MIIDELAY;
MDC (0);
MDIO (0);
MIIDELAY;
MDC (1);
MIIDELAY;
/* write 16 bits of register data, MSB first */
for (j = 0; j < 16; j++) {
MDC (0);
if ((value & 0x00008000) == 0) {
MDIO (0);
} else {
MDIO (1);
}
MIIDELAY;
MDC (1);
MIIDELAY;
value <<= 1;
}
/*
* Tri-state the MDIO line.
*/
MDIO_TRISTATE;
MDC (0);
MIIDELAY;
MDC (1);
MIIDELAY;
return 0;
}

3
drivers/spi/Makefile
View File

@@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libspi.a
COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)

193
drivers/spi/soft_spi.c Normal file
View File

@@ -0,0 +1,193 @@
/*
* (C) Copyright 2002
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
* Influenced by code from:
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <spi.h>
#include <malloc.h>
/*-----------------------------------------------------------------------
* Definitions
*/
#ifdef DEBUG_SPI
#define PRINTD(fmt,args...) printf (fmt ,##args)
#else
#define PRINTD(fmt,args...)
#endif
struct soft_spi_slave {
struct spi_slave slave;
unsigned int mode;
};
static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave)
{
return container_of(slave, struct soft_spi_slave, slave);
}
/*=====================================================================*/
/* Public Functions */
/*=====================================================================*/
/*-----------------------------------------------------------------------
* Initialization
*/
void spi_init (void)
{
#ifdef SPI_INIT
volatile immap_t *immr = (immap_t *)CFG_IMMR;
SPI_INIT;
#endif
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct soft_spi_slave *ss;
if (!spi_cs_is_valid(bus, cs))
return NULL;
ss = malloc(sizeof(struct soft_spi_slave));
if (!ss)
return NULL;
ss->slave.bus = bus;
ss->slave.cs = cs;
ss->mode = mode;
/* TODO: Use max_hz to limit the SCK rate */
return &ss->slave;
}
void spi_free_slave(struct spi_slave *slave)
{
struct soft_spi_slave *ss = to_soft_spi(slave);
free(ss);
}
int spi_claim_bus(struct spi_slave *slave)
{
#ifdef CFG_IMMR
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
struct soft_spi_slave *ss = to_soft_spi(slave);
/*
* Make sure the SPI clock is in idle state as defined for
* this slave.
*/
if (ss->mode & SPI_CPOL)
SPI_SCL(1);
else
SPI_SCL(0);
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
/* Nothing to do */
}
/*-----------------------------------------------------------------------
* SPI transfer
*
* This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
* "bitlen" bits in the SPI MISO port. That's just the way SPI works.
*
* The source of the outgoing bits is the "dout" parameter and the
* destination of the input bits is the "din" parameter. Note that "dout"
* and "din" can point to the same memory location, in which case the
* input data overwrites the output data (since both are buffered by
* temporary variables, this is OK).
*/
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
#ifdef CFG_IMMR
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
struct soft_spi_slave *ss = to_soft_spi(slave);
uchar tmpdin = 0;
uchar tmpdout = 0;
const u8 *txd = dout;
u8 *rxd = din;
int cpol = ss->mode & SPI_CPOL;
int cpha = ss->mode & SPI_CPHA;
unsigned int j;
PRINTD("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
slave->bus, slave->cs, *(uint *)txd, *(uint *)rxd, bitlen);
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
for(j = 0; j < bitlen; j++) {
/*
* Check if it is time to work on a new byte.
*/
if((j % 8) == 0) {
tmpdout = *txd++;
if(j != 0) {
*rxd++ = tmpdin;
}
tmpdin = 0;
}
if (!cpha)
SPI_SCL(!cpol);
SPI_SDA(tmpdout & 0x80);
SPI_DELAY;
if (cpha)
SPI_SCL(!cpol);
else
SPI_SCL(cpol);
tmpdin <<= 1;
tmpdin |= SPI_READ;
tmpdout <<= 1;
SPI_DELAY;
if (cpha)
SPI_SCL(cpol);
}
/*
* If the number of bits isn't a multiple of 8, shift the last
* bits over to left-justify them. Then store the last byte
* read in.
*/
if((bitlen % 8) != 0)
tmpdin <<= 8 - (bitlen % 8);
*rxd++ = tmpdin;
if (flags & SPI_XFER_END)
spi_cs_deactivate(slave);
return(0);
}