From 33041972727e84d3f95e26c83322521f61827584 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Mon, 12 Apr 2021 15:38:51 +0200 Subject: [PATCH 01/51] arm: dts: bcm283x: Add minimal smbios information At present SMBIOS tables are empty, which breaks some use-cases that rely on that. Add some minimal information to fulfill this. Signed-off-by: Matthias Brugger --- arch/arm/dts/bcm283x-u-boot.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/dts/bcm283x-u-boot.dtsi b/arch/arm/dts/bcm283x-u-boot.dtsi index 68d03627f4..22c67c4218 100644 --- a/arch/arm/dts/bcm283x-u-boot.dtsi +++ b/arch/arm/dts/bcm283x-u-boot.dtsi @@ -6,6 +6,25 @@ * (C) Copyright 2016 Fabian Vogt */ +/ { + smbios { + compatible = "u-boot,sysinfo-smbios"; + smbios { + system { + manufacturer = "raspberrypi"; + product = "rpi"; + }; + baseboard { + manufacturer = "raspberrypi"; + product = "rpi"; + }; + chassis { + manufacturer = "raspberrypi"; + }; + }; + }; +}; + &uart0 { skip-init; u-boot,dm-pre-reloc; From 1bc00bc74b91efc96ccdafc5921812f1be3e1659 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Mon, 12 Apr 2021 15:38:52 +0200 Subject: [PATCH 02/51] configs: rpi: Enable SMBIOS sysinfo driver Enable this driver to allow U-Boot to get SMBIOS table information from a device tree node. Signed-off-by: Matthias Brugger Acked-by: Fabian Vogt --- configs/rpi_0_w_defconfig | 2 ++ configs/rpi_2_defconfig | 2 ++ configs/rpi_3_32b_defconfig | 2 ++ configs/rpi_3_b_plus_defconfig | 2 ++ configs/rpi_3_defconfig | 2 ++ configs/rpi_4_32b_defconfig | 2 ++ configs/rpi_4_defconfig | 2 ++ configs/rpi_arm64_defconfig | 2 ++ configs/rpi_defconfig | 2 ++ 9 files changed, 18 insertions(+) diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index dfa72532ce..d17e102052 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -28,6 +28,8 @@ CONFIG_DM_ETH=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_KEYBOARD=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 9001e2b20b..8b8affb777 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -28,6 +28,8 @@ CONFIG_DM_ETH=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_KEYBOARD=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index a2a44aa63e..b867b7fa7b 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -30,6 +30,8 @@ CONFIG_DM_ETH=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_KEYBOARD=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index e34302ddf8..043665c3d1 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -30,6 +30,8 @@ CONFIG_DM_ETH=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_KEYBOARD=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index c48ec9c3ef..3cebd657da 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -30,6 +30,8 @@ CONFIG_DM_ETH=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_KEYBOARD=y diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index b1503e91fb..b813d04639 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -40,6 +40,8 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_IPROC200=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 9375885622..de2658ae88 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -40,6 +40,8 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_IPROC200=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index 6b18a8cada..f90107e548 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -35,6 +35,8 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_IPROC200=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 48ed929afa..af2189b8fe 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -28,6 +28,8 @@ CONFIG_DM_ETH=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_KEYBOARD=y From d28e127171768c618fb4d03ec4d3249527d7dccd Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 17 Jun 2021 11:22:03 +0200 Subject: [PATCH 03/51] ARM: bcm283x: change the virtual address of the XHCI PCI device base Move the XHCI PCI device base up in the virtual address space. This fixes initialization failure observed with newer Raspberry Pi firmware, later than 63b1922311 ("firmware: arm_loader: Update armstubs with those from PR 117). It looks that chosing 0xff800000 as the XHCI PCI device base conflicts with the updated ARM/VideoCore firmware. This also requires to reduce the size of the mapped PCI device region from 8MiB to 4MiB to fit into 32bit address space. This is still enough for the XHCI PCI device. Signed-off-by: Marek Szyprowski Reviewed-by: Jaehoon Chung Reviewed-by: Nicolas Saenz Julienne Tested-by: Stefan Agner Signed-off-by: Matthias Brugger --- arch/arm/mach-bcm283x/init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 49027ce0a2..9803499985 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -14,7 +14,7 @@ #include #define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL -#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL +#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x400000UL #ifdef CONFIG_ARM64 #include @@ -148,7 +148,7 @@ int mach_cpu_init(void) #ifdef CONFIG_ARMV7_LPAE #ifdef CONFIG_TARGET_RPI_4_32B -#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xffc00000UL #include #include From acc6987e59137485dbac0ee4a07cc349210954f3 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Tue, 10 Aug 2021 16:31:14 +0200 Subject: [PATCH 04/51] rpi: Conditionally add simple-framebuffer node It appears that RPi firmware has already added framebuffer node under /chosen, at least on RPi 2 versions. So check for this and don't add duplicate node. Signed-off-by: Ivan T. Ivanov Signed-off-by: Matthias Brugger --- board/raspberrypi/rpi/rpi.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index df52a4689f..372b26b6f2 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -497,12 +497,11 @@ void *board_fdt_blob_setup(void) int ft_board_setup(void *blob, struct bd_info *bd) { - /* - * For now, we simply always add the simplefb DT node. Later, we - * should be more intelligent, and e.g. only do this if no enabled DT - * node exists for the "real" graphics driver. - */ - lcd_dt_simplefb_add_node(blob); + int node; + + node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer"); + if (node < 0) + lcd_dt_simplefb_add_node(blob); #ifdef CONFIG_EFI_LOADER /* Reserve the spin table */ From 12ff1a8d23f96bed35dab548e31fd4ead5adca2b Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Wed, 13 May 2020 05:30:03 +0000 Subject: [PATCH 05/51] MAINTAINERS: POWERPC MPC8XX: Update email address Our email addresses have changed from @c-s.fr to @csgroup.eu Update entry in MAINTAINERS Signed-off-by: Christophe Leroy --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 40a0e7ac72..67c96a6045 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -980,7 +980,7 @@ S: Maintained F: arch/powerpc/ POWERPC MPC8XX -M: Christophe Leroy +M: Christophe Leroy S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-mpc8xx.git F: arch/powerpc/cpu/mpc8xx/ From 04662755000c7fb7d5716953a7899560863648e6 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 27 Jul 2021 18:24:39 -0500 Subject: [PATCH 06/51] firmware: ti_sci: Include linux/err.h in ti_sci_protocol.h The common TI SCI header file uses some macros from err.h and these get exercised when CONFIG_TI_SCI_PROTOCOL is not defined. Include the linux/err.h header file in this header file directly rather than relying on source files to include it to eliminate any potential build errors. While at this, reorder the existing header file include to the beginning of the file. Signed-off-by: Suman Anna Reviewed-by: Nishanth Menon --- include/linux/soc/ti/ti_sci_protocol.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index 794737923c..7f9941894c 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -11,6 +11,9 @@ #ifndef __TISCI_PROTOCOL_H #define __TISCI_PROTOCOL_H +#include +#include + /** * struct ti_sci_version_info - version information structure * @abi_major: Major ABI version. Change here implies risk of backward @@ -20,7 +23,6 @@ * @firmware_revision: Firmware revision (not usually used). * @firmware_description: Firmware description (not usually used). */ -#include struct ti_sci_version_info { u8 abi_major; u8 abi_minor; From d86a089d2946519dd7e0a840762f35e477368c85 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 27 Jul 2021 18:24:40 -0500 Subject: [PATCH 07/51] arm: mach-k3: common: Add a release_resources_for_core_shutdown() stub Add a weak release_resources_for_core_shutdown() stub implementation that can be overridden by actual implementation if a SoC supports that function. Signed-off-by: Suman Anna Reviewed-by: Nishanth Menon --- arch/arm/mach-k3/common.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index bb0f64194f..08b7344df7 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -193,6 +193,11 @@ int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr) } #endif +__weak void release_resources_for_core_shutdown(void) +{ + debug("%s not implemented...\n", __func__); +} + void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); From f1a815d068125cc5221a7294342131f0e9ede4a6 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 7 Sep 2021 17:16:54 -0500 Subject: [PATCH 08/51] arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2 divisors to generate the final FOUTPOSTDIV clock. These are in sequence with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is opposite of the actual implementation. Fix the data by simply adjusting the register bit-shifts. The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0 register values, fix these as well. Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200") Signed-off-by: Suman Anna Signed-off-by: Dave Gerlach --- arch/arm/mach-k3/j721e/clk-data.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c index 953ac45713..ff9262d7bc 100644 --- a/arch/arm/mach-k3/j721e/clk-data.c +++ b/arch/arm/mach-k3/j721e/clk-data.c @@ -463,8 +463,8 @@ static const struct clk_data clk_list[] = { CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), - CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0), - CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0), CLK_PLL("pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), @@ -523,8 +523,8 @@ static const struct clk_data clk_list[] = { CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0), CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0), CLK_PLL("pllfrac2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), - CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0), - CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0), CLK_PLL("pllfrac2_ssmod_16fft_main_13_foutvcop_clk", "main_pll_hfosc_sel_out13", 0x68d000, 0), CLK_PLL("pllfrac2_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0), CLK_PLL("pllfrac2_ssmod_16fft_main_16_foutvcop_clk", "main_pll_hfosc_sel_out16", 0x690000, 0), From 326c03b5482037d3c5b697dd588dfebb701d33b2 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 7 Sep 2021 17:16:55 -0500 Subject: [PATCH 09/51] arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2 divisors to generate the final FOUTPOSTDIV clock. These are in sequence with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is opposite of the actual implementation. Fix the data by simply adjusting the register bit-shifts. The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0 register values, fix these as well. Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200") Signed-off-by: Suman Anna Signed-off-by: Dave Gerlach --- arch/arm/mach-k3/j7200/clk-data.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c index 93c067079a..49145bbfc8 100644 --- a/arch/arm/mach-k3/j7200/clk-data.c +++ b/arch/arm/mach-k3/j7200/clk-data.c @@ -319,8 +319,8 @@ static const struct clk_data clk_list[] = { CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), - CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0), CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), @@ -360,8 +360,8 @@ static const struct clk_data clk_list[] = { CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0), CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0), CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0), CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), CLK_PLL("pllfracf_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0), CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), From ae8d3d236a3426dff4c1dfe1e8d61b54cd3a29af Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 7 Sep 2021 17:16:56 -0500 Subject: [PATCH 10/51] arm: mach-k3: Add note to auto-generated files Add a note to the automatically generated clk-data and dev-data files for j721e and j7200 to indicate that they are in fact auto-generated and should not be hand edited. Also adjust TI URL to use https instead of http and also add an empty line before first header inclusion. Signed-off-by: Dave Gerlach --- arch/arm/mach-k3/j7200/clk-data.c | 6 +++++- arch/arm/mach-k3/j7200/dev-data.c | 6 +++++- arch/arm/mach-k3/j721e/clk-data.c | 6 +++++- arch/arm/mach-k3/j721e/dev-data.c | 6 +++++- 4 files changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c index 49145bbfc8..7e55e48b92 100644 --- a/arch/arm/mach-k3/j7200/clk-data.c +++ b/arch/arm/mach-k3/j7200/clk-data.c @@ -2,8 +2,12 @@ /* * J7200 specific clock platform data * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ + #include "k3-clk.h" static const char * const gluelogic_hfosc0_clkout_parents[] = { diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c index c68bcc58e9..d3194ae51a 100644 --- a/arch/arm/mach-k3/j7200/dev-data.c +++ b/arch/arm/mach-k3/j7200/dev-data.c @@ -2,8 +2,12 @@ /* * J7200 specific device platform data * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ + #include "k3-dev.h" static struct ti_psc soc_psc_list[] = { diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c index ff9262d7bc..878b27a49a 100644 --- a/arch/arm/mach-k3/j721e/clk-data.c +++ b/arch/arm/mach-k3/j721e/clk-data.c @@ -2,8 +2,12 @@ /* * J721E specific clock platform data * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ + #include "k3-clk.h" static const char * const gluelogic_hfosc0_clkout_parents[] = { diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c index 96393c7132..300d998c62 100644 --- a/arch/arm/mach-k3/j721e/dev-data.c +++ b/arch/arm/mach-k3/j721e/dev-data.c @@ -2,8 +2,12 @@ /* * J721E specific device platform data * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ + #include "k3-dev.h" static struct ti_psc soc_psc_list[] = { From d3c56e2a823caa1e2d09daccd1b0d8a529d8df69 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 7 Sep 2021 17:16:57 -0500 Subject: [PATCH 11/51] clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write There are three different divider values in the DIV_CTRL register controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate function writes the entire register when programming plld, even though plld only resides in the lower 6 bits. Change the plld programming to read-modify-write to only affect the relevant bits for plld and to preserve the other two divider values present in the upper 16 bits, otherwise they will always get set to zero when programming plld. Fixes: 0aa2930ca192 ("clk: add support for TI K3 SoC PLL") Signed-off-by: Dave Gerlach --- drivers/clk/ti/clk-k3-pll.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c index bf2407a020..bf762c558e 100644 --- a/drivers/clk/ti/clk-k3-pll.c +++ b/drivers/clk/ti/clk-k3-pll.c @@ -2,7 +2,7 @@ /* * Texas Instruments K3 SoC PLL clock driver * - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ * Tero Kristo */ @@ -122,6 +122,7 @@ static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate) unsigned long pllm; u32 pllfm = 0; unsigned long plld; + u32 div_ctrl; u32 rem; int shift; @@ -175,7 +176,15 @@ static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate) writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0); writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1); - writel(plld, pll->reg + PLL_16FFT_DIV_CTRL); + + /* + * div_ctrl register contains other divider values, so rmw + * only plld and leave existing values alone + */ + div_ctrl = readl(pll->reg + PLL_16FFT_DIV_CTRL); + div_ctrl &= ~PLL_16FFT_DIV_CTRL_REF_DIV_MASK; + div_ctrl |= plld; + writel(div_ctrl, pll->reg + PLL_16FFT_DIV_CTRL); ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN; ctrl |= PLL_16FFT_CTRL_PLL_EN; From cfd50dfb729ab2268a5a44eaeea00ffa557919cd Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 7 Sep 2021 17:16:58 -0500 Subject: [PATCH 12/51] clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna Signed-off-by: Dave Gerlach --- arch/arm/mach-k3/j7200/clk-data.c | 85 ++++++++++++----------- arch/arm/mach-k3/j721e/clk-data.c | 111 +++++++++++++++--------------- drivers/clk/ti/clk-k3.c | 4 +- include/k3-clk.h | 30 ++++---- 4 files changed, 118 insertions(+), 112 deletions(-) diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c index 7e55e48b92..0437e30abb 100644 --- a/arch/arm/mach-k3/j7200/clk-data.c +++ b/arch/arm/mach-k3/j7200/clk-data.c @@ -8,6 +8,7 @@ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include #include "k3-clk.h" static const char * const gluelogic_hfosc0_clkout_parents[] = { @@ -323,18 +324,18 @@ static const struct clk_data clk_list[] = { CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), - CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), - CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0), - CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0), - CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 166666666), + CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666), CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), - CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), @@ -355,46 +356,46 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mcu_i2c0_scl_out", 0, 0), CLK_FIXED_RATE("board_0_wkup_lf_clkin_out", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), - CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000), - CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0, 0), CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), CLK_PLL("pllfracf_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0), CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), CLK_PLL("pllfracf_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), CLK_PLL("pllfracf_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), - CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0), - CLK_DIV("postdiv2_16fft_main_1_hsdivout7_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0), + CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv2_16fft_main_1_hsdivout7_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0), CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0), CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), - CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000), - CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0), - CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0), - CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0), - CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfracf_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfracf_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), - CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0), - CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0, 0), CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0), CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0), CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0), @@ -403,14 +404,14 @@ static const struct clk_data clk_list[] = { CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0), CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0), - CLK_DIV("hsdiv2_16fft_main_4_hsdivout0_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0), - CLK_DIV("hsdiv2_16fft_main_4_hsdivout2_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0), + CLK_DIV("hsdiv2_16fft_main_4_hsdivout0_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0, 0), + CLK_DIV("hsdiv2_16fft_main_4_hsdivout2_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0, 0), CLK_MUX("audio_refclko_mux_out0", audio_refclko_mux_out0_parents, 32, 0x1082e0, 0, 5, 0), CLK_MUX("audio_refclko_mux_out1", audio_refclko_mux_out1_parents, 32, 0x1082e4, 0, 5, 0), CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0), - CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0), - CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0), - CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0), + CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0), }; static const struct dev_clk soc_dev_clk_data[] = { diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c index 878b27a49a..5ab795139e 100644 --- a/arch/arm/mach-k3/j721e/clk-data.c +++ b/arch/arm/mach-k3/j721e/clk-data.c @@ -8,6 +8,7 @@ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include #include "k3-clk.h" static const char * const gluelogic_hfosc0_clkout_parents[] = { @@ -467,18 +468,18 @@ static const struct clk_data clk_list[] = { CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), - CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0), - CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), CLK_PLL("pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), - CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0), - CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0), - CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 166666666), + CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666), CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), - CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), @@ -517,18 +518,18 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n", 0, 0), CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), - CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000), - CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0, 0), CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0), CLK_PLL("pllfrac2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), - CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0), - CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), CLK_PLL("pllfrac2_ssmod_16fft_main_13_foutvcop_clk", "main_pll_hfosc_sel_out13", 0x68d000, 0), CLK_PLL("pllfrac2_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0), CLK_PLL("pllfrac2_ssmod_16fft_main_16_foutvcop_clk", "main_pll_hfosc_sel_out16", 0x690000, 0), @@ -544,41 +545,41 @@ static const struct clk_data clk_list[] = { CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), CLK_PLL("pllfrac2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), - CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0), - CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0), + CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0), CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0), CLK_MUX("main_pll15_xref_sel_out0", main_pll15_xref_sel_out0_parents, 2, 0x430080bc, 4, 1, 0), CLK_MUX("main_pll24_hfosc_sel_out0", main_pll24_hfosc_sel_out0_parents, 2, 0x430080e0, 0, 1, 0), CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), - CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000), - CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0), - CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0), - CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0), - CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0), - CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0), - CLK_DIV("hsdiv1_16fft_main_16_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_16_foutvcop_clk", 0x690080, 0, 7, 0), - CLK_DIV("hsdiv1_16fft_main_17_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_17_foutvcop_clk", 0x691080, 0, 7, 0), - CLK_DIV("hsdiv1_16fft_main_18_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_18_foutvcop_clk", 0x692080, 0, 7, 0), - CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0), - CLK_DIV("hsdiv1_16fft_main_23_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_23_foutvcop_clk", 0x697080, 0, 7, 0), - CLK_DIV("hsdiv1_16fft_main_25_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_25_foutvcop_clk", 0x699080, 0, 7, 0), - CLK_DIV("hsdiv3_16fft_main_13_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_13_foutvcop_clk", 0x68d080, 0, 7, 0), - CLK_DIV("hsdiv3_16fft_main_5_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_5_foutvcop_clk", 0x685080, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_16_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_16_foutvcop_clk", 0x690080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_17_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_17_foutvcop_clk", 0x691080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_18_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_18_foutvcop_clk", 0x692080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_23_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_23_foutvcop_clk", 0x697080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_25_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_25_foutvcop_clk", 0x699080, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_13_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_13_foutvcop_clk", 0x68d080, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_5_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_5_foutvcop_clk", 0x685080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), - CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0), - CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0, 0), CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0), CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0), CLK_PLL("pllfrac2_ssmod_16fft_main_15_foutvcop_clk", "main_pll15_xref_sel_out0", 0x68f000, 0), @@ -588,19 +589,19 @@ static const struct clk_data clk_list[] = { CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0), - CLK_DIV("hsdiv0_16fft_main_24_hsdivout0_clk", "plldeskew_16fft_main_24_foutp_clk", 0x698080, 0, 0, 0), - CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0), - CLK_DIV("hsdiv3_16fft_main_15_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f088, 0, 7, 0), - CLK_DIV("hsdiv3_16fft_main_4_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0), - CLK_DIV("hsdiv3_16fft_main_4_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_24_hsdivout0_clk", "plldeskew_16fft_main_24_foutp_clk", 0x698080, 0, 0, 0, 0), + CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_15_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f088, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_4_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_4_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0, 0), CLK_MUX("mcasp_ahclko_mux_out0", mcasp_ahclko_mux_out0_parents, 33, 0x1082e0, 0, 5, 0), CLK_MUX("mcasp_ahclko_mux_out1", mcasp_ahclko_mux_out1_parents, 33, 0x1082e4, 0, 5, 0), CLK_MUX("mcasp_ahclko_mux_out2", mcasp_ahclko_mux_out2_parents, 33, 0x1082e8, 0, 5, 0), CLK_MUX("mcasp_ahclko_mux_out3", mcasp_ahclko_mux_out3_parents, 33, 0x1082ec, 0, 5, 0), CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0), - CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0), - CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0), - CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0), + CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0), }; static const struct dev_clk soc_dev_clk_data[] = { diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index e921894e7a..e04c57eff2 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -2,7 +2,7 @@ /* * Texas Instruments K3 clock driver * - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ * Tero Kristo */ @@ -112,7 +112,7 @@ static int ti_clk_probe(struct udevice *dev) map_physmem(ti_clk_data->clk.div.reg, 0, MAP_NOCACHE), ti_clk_data->clk.div.shift, ti_clk_data->clk.div.width, - 0); + ti_clk_data->clk.div.div_flags); break; case CLK_TYPE_MUX: name = ti_clk_data->clk.mux.name; diff --git a/include/k3-clk.h b/include/k3-clk.h index 0735228579..59c76db86e 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com + * (C) Copyright 2020-2021 Texas Instruments Incorporated - http://www.ti.com * Tero Kristo */ @@ -54,6 +54,7 @@ struct div_data { u32 flags; int shift; int width; + u32 div_flags; }; struct hfosc_data { @@ -105,20 +106,23 @@ struct clk_data { .width = _width, .flags = _flags } \ } -#define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags) \ - { \ - .type = CLK_TYPE_DIV, \ - .clk.div = {.name = _name, .parent = _parent, .reg = _reg, .shift = _shift, .width = _width, .flags = _flags } \ +#define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags, _div_flags) \ + { \ + .type = CLK_TYPE_DIV, \ + .clk.div = { \ + .name = _name, .parent = _parent, .reg = _reg, \ + .shift = _shift, .width = _width, \ + .flags = _flags, .div_flags = _div_flags } \ } -#define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _freq) \ - { \ - .type = CLK_TYPE_DIV, \ - .default_freq = _freq, \ - .clk.div = { \ - .name = _name, .parent = _parent, \ - .reg = _reg, .shift = _shift, \ - .width = _width, .flags = _flags } \ +#define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _div_flags, _freq) \ + { \ + .type = CLK_TYPE_DIV, \ + .default_freq = _freq, \ + .clk.div = { \ + .name = _name, .parent = _parent, .reg = _reg, \ + .shift = _shift, .width = _width, \ + .flags = _flags, .div_flags = _div_flags } \ } #define CLK_PLL(_name, _parent, _reg, _flags) \ From 6887f8e00b821a3af02da207c85ba61c286dcc3c Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Wed, 8 Sep 2021 15:28:59 -0500 Subject: [PATCH 13/51] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge NB0 is bridge to SRAM and NB1 is bridge to DDR. To ensure that SRAM transfers are not stalled due to delays during DDR refreshes, SRAM traffic should be higher priority (threadmap=2) than DDR traffic (threadmap=0). This fixup is critical to provide deterministic access latency to MSMC from ICSSG, it applies to all AM65 silicon revisions and is due to incorrect reset values (has no erratum id) and statically setting things up should be done independent of usecases and board. This specific style of Northbridge configuration is specific only to AM65x devices, follow-on K3 devices have different data prioritization schemes (ASEL and the like) and hence the fixup applies purely to AM65x. Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in case of SR1 devices, on SR2 devices, lockups were not observed so far but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower throughput. Signed-off-by: Roger Quadros Acked-by: Andrew F. Davis Acked-by: Tomi Valkeinen Acked-by: Benoit Parrot [Jan: rebased, dropped used define, extended commit log] Signed-off-by: Jan Kiszka [Nishanth: Provide relevant context in the commit message] Signed-off-by: Nishanth Menon --- arch/arm/mach-k3/am6_init.c | 15 +++++++++++++++ arch/arm/mach-k3/include/mach/am6_hardware.h | 6 ++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 425b3f93c8..ffb7aaded2 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -151,6 +151,19 @@ int fdtdec_board_setup(const void *fdt_blob) return fixup_usb_boot(); } #endif + +static void setup_am654_navss_northbridge(void) +{ + /* + * NB0 is bridge to SRAM and NB1 is bridge to DDR. + * To ensure that SRAM transfers are not stalled due to + * delays during DDR refreshes, SRAM traffic should be higher + * priority (threadmap=2) than DDR traffic (threadmap=0). + */ + writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP); + writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP); +} + void board_init_f(ulong dummy) { #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS) @@ -168,6 +181,8 @@ void board_init_f(ulong dummy) /* Make all control module registers accessible */ ctrl_mmr_unlock(); + setup_am654_navss_northbridge(); + #ifdef CONFIG_CPU_V7R disable_linefill_optimization(); setup_k3_mpu_regions(); diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index 1908a13f0f..f533e22e06 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -52,4 +52,10 @@ /* MCU SCRATCHPAD usage */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE +/* NAVSS Northbridge config */ +#define NAVSS0_NBSS_NB0_CFG_BASE 0x03802000 +#define NAVSS0_NBSS_NB1_CFG_BASE 0x03803000 + +#define NAVSS_NBSS_THREADMAP 0x10 + #endif /* __ASM_ARCH_AM6_HARDWARE_H */ From ee91d465573637da5c386df3770a20cfb183d210 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 31 Aug 2021 13:20:48 -0500 Subject: [PATCH 14/51] arm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 startup With Device Manager firmware in an elf file form, we cannot load the FIT image to the exact same address as any of the executable sections of the elf file itself is located. However, the device tree descriptions for the ARMV8 bootloader/OS includes DDR regions only the final sections in DDR where the Device Manager firmware is actually executing out of. As the R5 uC is usually operating at a slower rate than an ARMv8 MPU, by starting the Armv8 ahead of parsing the elf and copying the correct sections to the required memories creates a race condition where the ARMv8 could overwrite the elf image loaded from the FIT image prior to the R5 completing parsing and putting the correct sections of elf in the required memory locations. OR create rather obscure debug conditions where data in the section is being modified by ARMV8 OS while the elf copy is in progress. To prevent all these conditions, lets make sure that the elf parse and copy operations are completed ahead of ARMv8 being released to execute. We will pay a penalty of elf copy time, but that is a valid tradeoff in comparison to debug of alternate scenarios. Signed-off-by: Nishanth Menon --- arch/arm/mach-k3/common.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 08b7344df7..2666cd2d7b 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -203,7 +203,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) typedef void __noreturn (*image_entry_noargs_t)(void); struct ti_sci_handle *ti_sci = get_ti_sci_handle(); u32 loadaddr = 0; - int ret, size = 0; + int ret, size = 0, shut_cpu = 0; /* Release all the exclusive devices held by SPL before starting ATF */ ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci); @@ -231,19 +231,10 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) if (ret) panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret); - /* Add an extra newline to differentiate the ATF logs from SPL */ - printf("Starting ATF on ARM64 core...\n\n"); - - ret = rproc_start(1); - if (ret) - panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret); if (!fit_image_info[IMAGE_ID_DM_FW].image_len && !(size > 0 && valid_elf_image(loadaddr))) { - debug("Shutting down...\n"); - release_resources_for_core_shutdown(); - - while (1) - asm volatile("wfe"); + shut_cpu = 1; + goto start_arm64; } if (!fit_image_info[IMAGE_ID_DM_FW].image_start) { @@ -256,6 +247,21 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) debug("%s: jumping to address %x\n", __func__, loadaddr); +start_arm64: + /* Add an extra newline to differentiate the ATF logs from SPL */ + printf("Starting ATF on ARM64 core...\n\n"); + + ret = rproc_start(1); + if (ret) + panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret); + + if (shut_cpu) { + debug("Shutting down...\n"); + release_resources_for_core_shutdown(); + + while (1) + asm volatile("wfe"); + } image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr; image_entry(); From a7e4f905d206d5895dab4bd38a8316e4f2fe15fe Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 2 Aug 2021 08:44:29 -0600 Subject: [PATCH 15/51] Revert "doc: Update CapsuleUpdate READMEs" This reverts commit 316ab801c0d91c02b21b8be1e3db7e69555364e9. Signed-off-by: Simon Glass --- doc/develop/uefi/uefi.rst | 124 -------------------------------------- 1 file changed, 124 deletions(-) diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index f17138f5c7..4f2b8b036d 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -277,130 +277,6 @@ Enable ``CONFIG_OPTEE``, ``CONFIG_CMD_OPTEE_RPMB`` and ``CONFIG_EFI_MM_COMM_TEE` [1] https://optee.readthedocs.io/en/latest/building/efi_vars/stmm.html -Enabling UEFI Capsule Update feature -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Support has been added for the UEFI capsule update feature which -enables updating the U-Boot image using the UEFI firmware management -protocol (FMP). The capsules are not passed to the firmware through -the UpdateCapsule runtime service. Instead, capsule-on-disk -functionality is used for fetching the capsule from the EFI System -Partition (ESP) by placing the capsule file under the -\EFI\UpdateCapsule directory. - -The directory \EFI\UpdateCapsule is checked for capsules only within the -EFI system partition on the device specified in the active boot option -determined by reference to BootNext variable or BootOrder variable processing. -The active Boot Variable is the variable with highest priority BootNext or -within BootOrder that refers to a device found to be present. Boot variables -in BootOrder but referring to devices not present are ignored when determining -active boot variable. -Before starting a capsule update make sure your capsules are installed in the -correct ESP partition or set BootNext. - -Performing the update -********************* - -Since U-boot doesn't currently support SetVariable at runtime there's a Kconfig -option (CONFIG_EFI_IGNORE_OSINDICATIONS) to disable the OsIndications variable -check. If that option is enabled just copy your capsule to \EFI\UpdateCapsule. - -If that option is disabled, you'll need to set the OsIndications variable with:: - - => setenv -e -nv -bs -rt -v OsIndications =0x04 - -Finally, the capsule update can be initiated either by rebooting the board, -which is the preferred method, or by issuing the following command:: - - => efidebug capsule disk-update - -**The efidebug command is should only be used during debugging/development.** - -Enabling Capsule Authentication -******************************* - -The UEFI specification defines a way of authenticating the capsule to -be updated by verifying the capsule signature. The capsule signature -is computed and prepended to the capsule payload at the time of -capsule generation. This signature is then verified by using the -public key stored as part of the X509 certificate. This certificate is -in the form of an efi signature list (esl) file, which is embedded as -part of U-Boot. - -The capsule authentication feature can be enabled through the -following config, in addition to the configs listed above for capsule -update:: - - CONFIG_EFI_CAPSULE_AUTHENTICATE=y - CONFIG_EFI_CAPSULE_KEY_PATH= - -The public and private keys used for the signing process are generated -and used by the steps highlighted below:: - - 1. Install utility commands on your host - * OPENSSL - * efitools - - 2. Create signing keys and certificate files on your host - - $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=CRT/ \ - -keyout CRT.key -out CRT.crt -nodes -days 365 - $ cert-to-efi-sig-list CRT.crt CRT.esl - - $ openssl x509 -in CRT.crt -out CRT.cer -outform DER - $ openssl x509 -inform DER -in CRT.cer -outform PEM -out CRT.pub.pem - - $ openssl pkcs12 -export -out CRT.pfx -inkey CRT.key -in CRT.crt - $ openssl pkcs12 -in CRT.pfx -nodes -out CRT.pem - -The capsule file can be generated by using the GenerateCapsule.py -script in EDKII:: - - $ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \ - --monotonic-count --fw-version \ - --lsv --guid \ - e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose \ - --update-image-index --signer-private-cert \ - /path/to/CRT.pem --trusted-public-cert \ - /path/to/CRT.pub.pem --other-public-cert /path/to/CRT.pub.pem \ - - -Place the capsule generated in the above step on the EFI System -Partition under the EFI/UpdateCapsule directory - -Testing on QEMU -*************** - -Currently, support has been added on the QEMU ARM64 virt platform for -updating the U-Boot binary as a raw image when the platform is booted -in non-secure mode, i.e. with CONFIG_TFABOOT disabled. For this -configuration, the QEMU platform needs to be booted with -'secure=off'. The U-Boot binary placed on the first bank of the NOR -flash at offset 0x0. The U-Boot environment is placed on the second -NOR flash bank at offset 0x4000000. - -The capsule update feature is enabled with the following configuration -settings:: - - CONFIG_MTD=y - CONFIG_FLASH_CFI_MTD=y - CONFIG_CMD_MTDPARTS=y - CONFIG_CMD_DFU=y - CONFIG_DFU_MTD=y - CONFIG_PCI_INIT_R=y - CONFIG_EFI_CAPSULE_ON_DISK=y - CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y - CONFIG_EFI_CAPSULE_FIRMWARE=y - CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y - -In addition, the following config needs to be disabled(QEMU ARM specific):: - - CONFIG_TFABOOT - -The capsule file can be generated by using the tools/mkeficapsule:: - - $ mkeficapsule --raw --index 1 - Executing the boot manager ~~~~~~~~~~~~~~~~~~~~~~~~~~ From d428e81266a59974ade74c1ba019af39f23304ab Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 2 Aug 2021 08:44:30 -0600 Subject: [PATCH 16/51] Revert "mkeficapsule: Remove dtb related options" This reverts commit f86caab058ff062ce72b24cd1ab9ec1253cc1352. Signed-off-by: Simon Glass --- tools/mkeficapsule.c | 229 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 222 insertions(+), 7 deletions(-) diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c index 4995ba4e0c..de0a628988 100644 --- a/tools/mkeficapsule.c +++ b/tools/mkeficapsule.c @@ -4,17 +4,22 @@ * Author: AKASHI Takahiro */ +#include #include #include #include #include #include #include +#include #include +#include #include #include +#include "fdt_host.h" + typedef __u8 u8; typedef __u16 u16; typedef __u32 u32; @@ -24,6 +29,9 @@ typedef __s32 s32; #define aligned_u64 __aligned_u64 +#define SIGNATURE_NODENAME "signature" +#define OVERLAY_NODENAME "__overlay__" + #ifndef __packed #define __packed __attribute__((packed)) #endif @@ -44,6 +52,9 @@ static struct option options[] = { {"raw", required_argument, NULL, 'r'}, {"index", required_argument, NULL, 'i'}, {"instance", required_argument, NULL, 'I'}, + {"dtb", required_argument, NULL, 'D'}, + {"public key", required_argument, NULL, 'K'}, + {"overlay", no_argument, NULL, 'O'}, {"help", no_argument, NULL, 'h'}, {NULL, 0, NULL, 0}, }; @@ -57,10 +68,187 @@ static void print_usage(void) "\t-r, --raw new raw image file\n" "\t-i, --index update image index\n" "\t-I, --instance update hardware instance\n" + "\t-K, --public-key public key esl file\n" + "\t-D, --dtb dtb file\n" + "\t-O, --overlay the dtb file is an overlay\n" "\t-h, --help print a help message\n", tool_name); } +static int fdt_add_pub_key_data(void *sptr, void *dptr, size_t key_size, + bool overlay) +{ + int parent; + int ov_node; + int frag_node; + int ret = 0; + + if (overlay) { + /* + * The signature would be stored in the + * first fragment node of the overlay + */ + frag_node = fdt_first_subnode(dptr, 0); + if (frag_node == -FDT_ERR_NOTFOUND) { + fprintf(stderr, + "Couldn't find the fragment node: %s\n", + fdt_strerror(frag_node)); + goto done; + } + + ov_node = fdt_subnode_offset(dptr, frag_node, OVERLAY_NODENAME); + if (ov_node == -FDT_ERR_NOTFOUND) { + fprintf(stderr, + "Couldn't find the __overlay__ node: %s\n", + fdt_strerror(ov_node)); + goto done; + } + } else { + ov_node = 0; + } + + parent = fdt_subnode_offset(dptr, ov_node, SIGNATURE_NODENAME); + if (parent == -FDT_ERR_NOTFOUND) { + parent = fdt_add_subnode(dptr, ov_node, SIGNATURE_NODENAME); + if (parent < 0) { + ret = parent; + if (ret != -FDT_ERR_NOSPACE) { + fprintf(stderr, + "Couldn't create signature node: %s\n", + fdt_strerror(parent)); + } + } + } + if (ret) + goto done; + + /* Write the key to the FDT node */ + ret = fdt_setprop(dptr, parent, "capsule-key", + sptr, key_size); + +done: + if (ret) + ret = ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO; + + return ret; +} + +static int add_public_key(const char *pkey_file, const char *dtb_file, + bool overlay) +{ + int ret; + int srcfd = -1; + int destfd = -1; + void *sptr = NULL; + void *dptr = NULL; + off_t src_size; + struct stat pub_key; + struct stat dtb; + + /* Find out the size of the public key */ + srcfd = open(pkey_file, O_RDONLY); + if (srcfd == -1) { + fprintf(stderr, "%s: Can't open %s: %s\n", + __func__, pkey_file, strerror(errno)); + ret = -1; + goto err; + } + + ret = fstat(srcfd, &pub_key); + if (ret == -1) { + fprintf(stderr, "%s: Can't stat %s: %s\n", + __func__, pkey_file, strerror(errno)); + ret = -1; + goto err; + } + + src_size = pub_key.st_size; + + /* mmap the public key esl file */ + sptr = mmap(0, src_size, PROT_READ, MAP_SHARED, srcfd, 0); + if (sptr == MAP_FAILED) { + fprintf(stderr, "%s: Failed to mmap %s:%s\n", + __func__, pkey_file, strerror(errno)); + ret = -1; + goto err; + } + + /* Open the dest FDT */ + destfd = open(dtb_file, O_RDWR); + if (destfd == -1) { + fprintf(stderr, "%s: Can't open %s: %s\n", + __func__, dtb_file, strerror(errno)); + ret = -1; + goto err; + } + + ret = fstat(destfd, &dtb); + if (ret == -1) { + fprintf(stderr, "%s: Can't stat %s: %s\n", + __func__, dtb_file, strerror(errno)); + goto err; + } + + dtb.st_size += src_size + 0x30; + if (ftruncate(destfd, dtb.st_size)) { + fprintf(stderr, "%s: Can't expand %s: %s\n", + __func__, dtb_file, strerror(errno)); + ret = -1; + goto err; + } + + errno = 0; + /* mmap the dtb file */ + dptr = mmap(0, dtb.st_size, PROT_READ | PROT_WRITE, MAP_SHARED, + destfd, 0); + if (dptr == MAP_FAILED) { + fprintf(stderr, "%s: Failed to mmap %s:%s\n", + __func__, dtb_file, strerror(errno)); + ret = -1; + goto err; + } + + if (fdt_check_header(dptr)) { + fprintf(stderr, "%s: Invalid FDT header\n", __func__); + ret = -1; + goto err; + } + + ret = fdt_open_into(dptr, dptr, dtb.st_size); + if (ret) { + fprintf(stderr, "%s: Cannot expand FDT: %s\n", + __func__, fdt_strerror(ret)); + ret = -1; + goto err; + } + + /* Copy the esl file to the expanded FDT */ + ret = fdt_add_pub_key_data(sptr, dptr, src_size, overlay); + if (ret < 0) { + fprintf(stderr, "%s: Unable to add public key to the FDT\n", + __func__); + ret = -1; + goto err; + } + + ret = 0; + +err: + if (sptr) + munmap(sptr, src_size); + + if (dptr) + munmap(dptr, dtb.st_size); + + if (srcfd != -1) + close(srcfd); + + if (destfd != -1) + close(destfd); + + return ret; +} + static int create_fwbin(char *path, char *bin, efi_guid_t *guid, unsigned long index, unsigned long instance) { @@ -178,16 +366,22 @@ err_1: int main(int argc, char **argv) { char *file; + char *pkey_file; + char *dtb_file; efi_guid_t *guid; unsigned long index, instance; int c, idx; + int ret; + bool overlay = false; file = NULL; + pkey_file = NULL; + dtb_file = NULL; guid = NULL; index = 0; instance = 0; for (;;) { - c = getopt_long(argc, argv, "f:r:i:I:v:h", options, &idx); + c = getopt_long(argc, argv, "f:r:i:I:v:D:K:Oh", options, &idx); if (c == -1) break; @@ -214,22 +408,43 @@ int main(int argc, char **argv) case 'I': instance = strtoul(optarg, NULL, 0); break; + case 'K': + if (pkey_file) { + printf("Public Key already specified\n"); + return -1; + } + pkey_file = optarg; + break; + case 'D': + if (dtb_file) { + printf("DTB file already specified\n"); + return -1; + } + dtb_file = optarg; + break; + case 'O': + overlay = true; + break; case 'h': print_usage(); return 0; } } - /* need an output file */ - if (argc != optind + 1) { + /* need a fit image file or raw image file */ + if (!file && !pkey_file && !dtb_file) { print_usage(); exit(EXIT_FAILURE); } - /* need a fit image file or raw image file */ - if (!file) { - print_usage(); - exit(EXIT_SUCCESS); + if (pkey_file && dtb_file) { + ret = add_public_key(pkey_file, dtb_file, overlay); + if (ret == -1) { + printf("Adding public key to the dtb failed\n"); + exit(EXIT_FAILURE); + } else { + exit(EXIT_SUCCESS); + } } if (create_fwbin(argv[optind], file, guid, index, instance) From 47a25e81d35c8d801cae9089de90c9ffea083409 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 2 Aug 2021 08:44:31 -0600 Subject: [PATCH 17/51] Revert "efi_capsule: Move signature from DTB to .rodata" This was unfortunately applied despite much discussion about it beiong the wrong way to implement this feature. Revert it before too many other things are built on top of it. This reverts commit ddf67daac39de76d2697d587148f4c2cb768f492. Signed-off-by: Simon Glass --- board/emulation/common/Makefile | 1 + include/asm-generic/sections.h | 2 -- lib/efi_loader/Kconfig | 7 ------- lib/efi_loader/Makefile | 8 -------- lib/efi_loader/efi_capsule.c | 18 +++--------------- lib/efi_loader/efi_capsule_key.S | 17 ----------------- 6 files changed, 4 insertions(+), 49 deletions(-) delete mode 100644 lib/efi_loader/efi_capsule_key.S diff --git a/board/emulation/common/Makefile b/board/emulation/common/Makefile index c5b452e7e3..7ed447a69d 100644 --- a/board/emulation/common/Makefile +++ b/board/emulation/common/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += qemu_mtdparts.o obj-$(CONFIG_SET_DFU_ALT_INFO) += qemu_dfu.o +obj-$(CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT) += qemu_capsule.o diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index ec992b0c2e..267f1db73f 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -27,8 +27,6 @@ extern char __efi_helloworld_begin[]; extern char __efi_helloworld_end[]; extern char __efi_var_file_begin[]; extern char __efi_var_file_end[]; -extern char __efi_capsule_sig_begin[]; -extern char __efi_capsule_sig_end[]; /* Private data used by of-platdata devices/uclasses */ extern char __priv_data_start[], __priv_data_end[]; diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 649ee57330..f48d9e8b51 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -215,13 +215,6 @@ config EFI_CAPSULE_AUTHENTICATE Select this option if you want to enable capsule authentication -config EFI_CAPSULE_KEY_PATH - string "Path to .esl cert for capsule authentication" - depends on EFI_CAPSULE_AUTHENTICATE - help - Provide the EFI signature list (esl) certificate used for capsule - authentication - config EFI_DEVICE_PATH_TO_TEXT bool "Device path to text protocol" default y diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 08469d9cd9..fd344cea29 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -20,19 +20,11 @@ always += helloworld.efi targets += helloworld.o endif -ifeq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE),y) -EFI_CAPSULE_KEY_PATH := $(subst $\",,$(CONFIG_EFI_CAPSULE_KEY_PATH)) -ifeq ("$(wildcard $(EFI_CAPSULE_KEY_PATH))","") -$(error .esl certificate not found. Configure your CONFIG_EFI_CAPSULE_KEY_PATH) -endif -endif - obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o obj-$(CONFIG_CMD_BOOTEFI_BOOTMGR) += efi_bootmgr.o obj-y += efi_boottime.o obj-y += efi_helper.o obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += efi_capsule.o -obj-$(CONFIG_EFI_CAPSULE_AUTHENTICATE) += efi_capsule_key.o obj-$(CONFIG_EFI_CAPSULE_FIRMWARE) += efi_firmware.o obj-y += efi_console.o obj-y += efi_device_path.o diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index 26990bc2df..b75e4bcba1 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include @@ -253,23 +252,12 @@ out: #if defined(CONFIG_EFI_CAPSULE_AUTHENTICATE) -static int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len) -{ - const void *blob = __efi_capsule_sig_begin; - const int len = __efi_capsule_sig_end - __efi_capsule_sig_begin; - - *pkey = (void *)blob; - *pkey_len = len; - - return 0; -} - efi_status_t efi_capsule_authenticate(const void *capsule, efi_uintn_t capsule_size, void **image, efi_uintn_t *image_size) { u8 *buf; int ret; - void *stored_pkey, *pkey; + void *fdt_pkey, *pkey; efi_uintn_t pkey_len; uint64_t monotonic_count; struct efi_signature_store *truststore; @@ -322,7 +310,7 @@ efi_status_t efi_capsule_authenticate(const void *capsule, efi_uintn_t capsule_s goto out; } - ret = efi_get_public_key_data(&stored_pkey, &pkey_len); + ret = efi_get_public_key_data(&fdt_pkey, &pkey_len); if (ret < 0) goto out; @@ -330,7 +318,7 @@ efi_status_t efi_capsule_authenticate(const void *capsule, efi_uintn_t capsule_s if (!pkey) goto out; - memcpy(pkey, stored_pkey, pkey_len); + memcpy(pkey, fdt_pkey, pkey_len); truststore = efi_build_signature_store(pkey, pkey_len); if (!truststore) goto out; diff --git a/lib/efi_loader/efi_capsule_key.S b/lib/efi_loader/efi_capsule_key.S deleted file mode 100644 index 58f00b8e4b..0000000000 --- a/lib/efi_loader/efi_capsule_key.S +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * .esl cert for capsule authentication - * - * Copyright (c) 2021, Ilias Apalodimas - */ - -#include - -.section .rodata.capsule_key.init,"a" -.balign 16 -.global __efi_capsule_sig_begin -__efi_capsule_sig_begin: -.incbin CONFIG_EFI_CAPSULE_KEY_PATH -__efi_capsule_sig_end: -.global __efi_capsule_sig_end -.balign 16 From b31077feca2276f0860706d1843f548baae68aee Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 11 Sep 2021 15:11:30 -0400 Subject: [PATCH 18/51] wdt: dw: Fix passing NULL pointer to reset functions reset_*_bulk expects a real pointer. Fixes: 4f7abafe1c ("driver: watchdog: reset watchdog in designware_wdt_stop() function") Signed-off-by: Sean Anderson Reviewed-by: Stefan Roese --- drivers/watchdog/designware_wdt.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index afed81e6c6..cfec29bd15 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -22,7 +22,7 @@ struct designware_wdt_priv { void __iomem *base; unsigned int clk_khz; - struct reset_ctl_bulk *resets; + struct reset_ctl_bulk resets; }; /* @@ -99,11 +99,11 @@ static int designware_wdt_stop(struct udevice *dev) if (CONFIG_IS_ENABLED(DM_RESET)) { int ret; - ret = reset_assert_bulk(priv->resets); + ret = reset_assert_bulk(&priv->resets); if (ret) return ret; - ret = reset_deassert_bulk(priv->resets); + ret = reset_deassert_bulk(&priv->resets); if (ret) return ret; } @@ -156,11 +156,11 @@ static int designware_wdt_probe(struct udevice *dev) #endif if (CONFIG_IS_ENABLED(DM_RESET)) { - ret = reset_get_bulk(dev, priv->resets); + ret = reset_get_bulk(dev, &priv->resets); if (ret) goto err; - ret = reset_deassert_bulk(priv->resets); + ret = reset_deassert_bulk(&priv->resets); if (ret) goto err; } From cf39d0c29dcf332d7055d0545fc95e3379d91a62 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 14 Sep 2021 14:14:52 +0200 Subject: [PATCH 19/51] arm: dts: stm32mp1: use ssbl partition name for U-Boot Continue to use the "ssbl" name for GPT partition of secondary boot stage = U-Boot for basic boot with SPL to avoid to disturb existing user. The "fip" partition name is only used for TFA_BOOT with FIP, it is a TF-A BL2 requirement; it the default configuration for STMicroelectronics boards. Fixes: b73e8bf453f8 ("arm: stm32mp: add defconfig for trusted boot with FIP") Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 4 +++- arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index 0101962ea5..15a04ae927 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -21,11 +21,13 @@ st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; -#ifdef CONFIG_STM32MP15x_STM32IMAGE +#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL) config { u-boot,mmc-env-partition = "ssbl"; }; +#endif +#ifdef CONFIG_STM32MP15x_STM32IMAGE /* only needed for boot with TF-A, witout FIP support */ firmware { optee { diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 32777384c6..408abaf52f 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -20,11 +20,13 @@ st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; -#ifdef CONFIG_STM32MP15x_STM32IMAGE +#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL) config { u-boot,mmc-env-partition = "ssbl"; }; +#endif +#ifdef CONFIG_STM32MP15x_STM32IMAGE /* only needed for boot with TF-A, witout FIP support */ firmware { optee { From e45066f48f07dd192cb763d9cc2ef115bc7cb814 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 10 Sep 2021 10:59:27 +0300 Subject: [PATCH 20/51] x86: edison: Mark eMMC non-removable eMMC is non-removable on Intel Edison board. Fix the DTS accordingly. Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- arch/x86/dts/edison.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts index 64b6228363..2c8cf6c071 100644 --- a/arch/x86/dts/edison.dts +++ b/arch/x86/dts/edison.dts @@ -88,6 +88,7 @@ emmc: mmc@ff3fc000 { compatible = "intel,sdhci-tangier"; reg = <0xff3fc000 0x1000>; + non-removable; }; sdcard: mmc@ff3fa000 { From 57e2c0a86fe48194c9407d36d60f9ab033b4460e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Sat, 11 Sep 2021 21:27:42 +0300 Subject: [PATCH 21/51] x86: tangier: acpi: Add GPIO card detection to SDHCI #2 On Intel Tangier the SDHCI #2 provides SD card connection. Add GPIO card detection for it. Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier") BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135 Signed-off-by: Andy Shevchenko Acked-by: Bin Meng --- .../asm/arch-tangier/acpi/southcluster.asl | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index df66625930..a8852f8202 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -97,6 +97,38 @@ Device (PCI0) } } + Device (SDHB) + { + Name (_ADR, 0x00010002) + Name (_DEP, Package () + { + GPIO + }) + + Name (RBUF, ResourceTemplate() + { + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 10000, + "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 77 } + }) + + Method (_CRS, 0, Serialized) + { + Return (RBUF) + } + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "cd-gpios", Package () { ^SDHB, 0, 0, 0 } }, + } + }) + + Method (_STA) + { + Return (STA_VISIBLE) + } + } + Device (SDHC) { Name (_ADR, 0x00010003) From 7f899da901b001a973a1971d539d77bde2b68b05 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Mon, 5 Jul 2021 13:29:01 +0100 Subject: [PATCH 22/51] phy: sun50i-usb3: Add a driver for the H6 USB3 PHY This driver is needed for XHCI to work on the Allwinner H6 SoC. The driver is copied from Linux v5.10. Reviewed-by: Andre Przywara Signed-off-by: Samuel Holland Signed-off-by: Andre Przywara --- drivers/phy/allwinner/Kconfig | 8 ++ drivers/phy/allwinner/Makefile | 1 + drivers/phy/allwinner/phy-sun50i-usb3.c | 171 ++++++++++++++++++++++++ 3 files changed, 180 insertions(+) create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig index dba3bae61c..6bfb79cbca 100644 --- a/drivers/phy/allwinner/Kconfig +++ b/drivers/phy/allwinner/Kconfig @@ -11,3 +11,11 @@ config PHY_SUN4I_USB This driver controls the entire USB PHY block, both the USB OTG parts, as well as the 2 regular USB 2 host PHYs. + +config PHY_SUN50I_USB3 + bool "Allwinner sun50i USB3 PHY driver" + depends on ARCH_SUNXI + select PHY + help + Enable this to support the USB3 transceiver that is part of + Allwinner sun50i SoCs. diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile index e709fca643..f2b60ce1a6 100644 --- a/drivers/phy/allwinner/Makefile +++ b/drivers/phy/allwinner/Makefile @@ -4,3 +4,4 @@ # obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o +obj-$(CONFIG_PHY_SUN50I_USB3) += phy-sun50i-usb3.o diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c b/drivers/phy/allwinner/phy-sun50i-usb3.c new file mode 100644 index 0000000000..e5a3d2d92e --- /dev/null +++ b/drivers/phy/allwinner/phy-sun50i-usb3.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Allwinner sun50i(H6) USB 3.0 phy driver + * + * Copyright (C) 2020 Samuel Holland + * + * Based on the Linux driver, which is: + * + * Copyright (C) 2017 Icenowy Zheng + * + * Based on phy-sun9i-usb.c, which is: + * + * Copyright (C) 2014-2015 Chen-Yu Tsai + * + * Based on code from Allwinner BSP, which is: + * + * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Interface Status and Control Registers */ +#define SUNXI_ISCR 0x00 +#define SUNXI_PIPE_CLOCK_CONTROL 0x14 +#define SUNXI_PHY_TUNE_LOW 0x18 +#define SUNXI_PHY_TUNE_HIGH 0x1c +#define SUNXI_PHY_EXTERNAL_CONTROL 0x20 + +/* USB2.0 Interface Status and Control Register */ +#define SUNXI_ISCR_FORCE_VBUS (3 << 12) + +/* PIPE Clock Control Register */ +#define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6) + +/* PHY External Control Register */ +#define SUNXI_PEC_EXTERN_VBUS (3 << 1) +#define SUNXI_PEC_SSC_EN (1 << 24) +#define SUNXI_PEC_REF_SSP_EN (1 << 26) + +/* PHY Tune High Register */ +#define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19) +#define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19) +#define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13) +#define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13) +#define SUNXI_TX_SWING_FULL(n) ((n) << 6) +#define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6) +#define SUNXI_LOS_BIAS(n) ((n) << 3) +#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3) +#define SUNXI_TXVBOOSTLVL(n) ((n) << 0) +#define SUNXI_TXVBOOSTLVL_MASK GENMASK(2, 0) + +struct sun50i_usb3_phy_priv { + void __iomem *regs; + struct reset_ctl reset; + struct clk clk; +}; + +static void sun50i_usb3_phy_open(struct sun50i_usb3_phy_priv *phy) +{ + u32 val; + + val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); + val |= SUNXI_PEC_EXTERN_VBUS; + val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN; + writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); + + val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL); + val |= SUNXI_PCC_PIPE_CLK_OPEN; + writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL); + + val = readl(phy->regs + SUNXI_ISCR); + val |= SUNXI_ISCR_FORCE_VBUS; + writel(val, phy->regs + SUNXI_ISCR); + + /* + * All the magic numbers written to the PHY_TUNE_{LOW_HIGH} + * registers are directly taken from the BSP USB3 driver from + * Allwiner. + */ + writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW); + + val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH); + val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK | + SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK | + SUNXI_TX_DEEMPH_3P5DB_MASK); + val |= SUNXI_TXVBOOSTLVL(0x7); + val |= SUNXI_LOS_BIAS(0x7); + val |= SUNXI_TX_SWING_FULL(0x55); + val |= SUNXI_TX_DEEMPH_6DB(0x20); + val |= SUNXI_TX_DEEMPH_3P5DB(0x15); + writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH); +} + +static int sun50i_usb3_phy_init(struct phy *phy) +{ + struct sun50i_usb3_phy_priv *priv = dev_get_priv(phy->dev); + int ret; + + ret = clk_prepare_enable(&priv->clk); + if (ret) + return ret; + + ret = reset_deassert(&priv->reset); + if (ret) { + clk_disable_unprepare(&priv->clk); + return ret; + } + + sun50i_usb3_phy_open(priv); + + return 0; +} + +static int sun50i_usb3_phy_exit(struct phy *phy) +{ + struct sun50i_usb3_phy_priv *priv = dev_get_priv(phy->dev); + + reset_assert(&priv->reset); + clk_disable_unprepare(&priv->clk); + + return 0; +} + +static const struct phy_ops sun50i_usb3_phy_ops = { + .init = sun50i_usb3_phy_init, + .exit = sun50i_usb3_phy_exit, +}; + +static int sun50i_usb3_phy_probe(struct udevice *dev) +{ + struct sun50i_usb3_phy_priv *priv = dev_get_priv(dev); + int ret; + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) { + dev_err(dev, "failed to get phy clock\n"); + return ret; + } + + ret = reset_get_by_index(dev, 0, &priv->reset); + if (ret) { + dev_err(dev, "failed to get reset control\n"); + return ret; + } + + priv->regs = (void __iomem *)dev_read_addr(dev); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + return 0; +} + +static const struct udevice_id sun50i_usb3_phy_ids[] = { + { .compatible = "allwinner,sun50i-h6-usb3-phy" }, + { }, +}; + +U_BOOT_DRIVER(sun50i_usb3_phy) = { + .name = "sun50i-usb3-phy", + .id = UCLASS_PHY, + .of_match = sun50i_usb3_phy_ids, + .ops = &sun50i_usb3_phy_ops, + .probe = sun50i_usb3_phy_probe, + .priv_auto = sizeof(struct sun50i_usb3_phy_priv), +}; From 70a98caf194dba204861575d207f9172549a5f35 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Mon, 5 Jul 2021 13:29:02 +0100 Subject: [PATCH 23/51] usb: xhci-pci: Move reset logic out of XHCI core Resetting an XHCI controller inside xhci_register undoes any register setup performed by the platform driver. And at least on the Allwinner H6, resetting the XHCI controller also resets the PHY, which prevents the controller from working. That means the controller must be taken out of reset before initializing the PHY, which must be done before calling xhci_register. The logic in the XHCI core was added to support the Raspberry Pi 4 (although this was not mentioned in the commit log!), which uses the xhci-pci platform driver. Move the reset logic to the platform driver, where it belongs, and where it cannot interfere with other platform drivers. This also fixes a failure to call reset_free if xhci_register failed. Fixes: 0b80371b350e ("usb: xhci: Add reset controller support") Signed-off-by: Samuel Holland Reviewed-by: Bin Meng Signed-off-by: Andre Przywara --- drivers/usb/host/xhci-mem.c | 2 -- drivers/usb/host/xhci-pci.c | 52 ++++++++++++++++++++++++++++++++++--- drivers/usb/host/xhci.c | 35 ------------------------- include/usb/xhci.h | 2 -- 4 files changed, 48 insertions(+), 43 deletions(-) diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 1c11c2e7e0..0d9da62bab 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -180,8 +180,6 @@ void xhci_cleanup(struct xhci_ctrl *ctrl) xhci_free_virt_devices(ctrl); free(ctrl->erst.entries); free(ctrl->dcbaa); - if (reset_valid(&ctrl->reset)) - reset_free(&ctrl->reset); memset(ctrl, '\0', sizeof(struct xhci_ctrl)); } diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index aaa243f291..630bc20be1 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -7,12 +7,18 @@ #include #include +#include #include #include #include +#include #include #include +struct xhci_pci_plat { + struct reset_ctl reset; +}; + static int xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor) { @@ -45,15 +51,53 @@ static int xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, static int xhci_pci_probe(struct udevice *dev) { + struct xhci_pci_plat *plat = dev_get_plat(dev); struct xhci_hccr *hccr; struct xhci_hcor *hcor; int ret; + ret = reset_get_by_index(dev, 0, &plat->reset); + if (ret && ret != -ENOENT && ret != -ENOTSUPP) { + dev_err(dev, "failed to get reset\n"); + return ret; + } + + if (reset_valid(&plat->reset)) { + ret = reset_assert(&plat->reset); + if (ret) + goto err_reset; + + ret = reset_deassert(&plat->reset); + if (ret) + goto err_reset; + } + ret = xhci_pci_init(dev, &hccr, &hcor); if (ret) - return ret; + goto err_reset; - return xhci_register(dev, hccr, hcor); + ret = xhci_register(dev, hccr, hcor); + if (ret) + goto err_reset; + + return 0; + +err_reset: + if (reset_valid(&plat->reset)) + reset_free(&plat->reset); + + return ret; +} + +static int xhci_pci_remove(struct udevice *dev) +{ + struct xhci_pci_plat *plat = dev_get_plat(dev); + + xhci_deregister(dev); + if (reset_valid(&plat->reset)) + reset_free(&plat->reset); + + return 0; } static const struct udevice_id xhci_pci_ids[] = { @@ -65,10 +109,10 @@ U_BOOT_DRIVER(xhci_pci) = { .name = "xhci_pci", .id = UCLASS_USB, .probe = xhci_pci_probe, - .remove = xhci_deregister, + .remove = xhci_pci_remove, .of_match = xhci_pci_ids, .ops = &xhci_usb_ops, - .plat_auto = sizeof(struct usb_plat), + .plat_auto = sizeof(struct xhci_pci_plat), .priv_auto = sizeof(struct xhci_ctrl), .flags = DM_FLAG_OS_PREPARE | DM_FLAG_ALLOC_PRIV_DMA, }; diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index d27ac01c83..452dacc0af 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -188,37 +188,6 @@ static int xhci_start(struct xhci_hcor *hcor) return ret; } -#if CONFIG_IS_ENABLED(DM_USB) -/** - * Resets XHCI Hardware - * - * @param ctrl pointer to host controller - * @return 0 if OK, or a negative error code. - */ -static int xhci_reset_hw(struct xhci_ctrl *ctrl) -{ - int ret; - - ret = reset_get_by_index(ctrl->dev, 0, &ctrl->reset); - if (ret && ret != -ENOENT && ret != -ENOTSUPP) { - dev_err(ctrl->dev, "failed to get reset\n"); - return ret; - } - - if (reset_valid(&ctrl->reset)) { - ret = reset_assert(&ctrl->reset); - if (ret) - return ret; - - ret = reset_deassert(&ctrl->reset); - if (ret) - return ret; - } - - return 0; -} -#endif - /** * Resets the XHCI Controller * @@ -1534,10 +1503,6 @@ int xhci_register(struct udevice *dev, struct xhci_hccr *hccr, ctrl->dev = dev; - ret = xhci_reset_hw(ctrl); - if (ret) - goto err; - /* * XHCI needs to issue a Address device command to setup * proper device context structures, before it can interact diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 8d95e213b0..01e63cf0fc 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -17,7 +17,6 @@ #define HOST_XHCI_H_ #include -#include #include #include #include @@ -1200,7 +1199,6 @@ struct xhci_ctrl { #if CONFIG_IS_ENABLED(DM_USB) struct udevice *dev; #endif - struct reset_ctl reset; struct xhci_hccr *hccr; /* R/O registers, not need for volatile */ struct xhci_hcor *hcor; struct xhci_doorbell_array *dba; From 91ce84a56b3419fc7b8bd75575d470c0d22ae2b0 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Mon, 5 Jul 2021 13:29:03 +0100 Subject: [PATCH 24/51] usb: xhci-dwc3: Add support for clocks/resets Some platforms, like the Allwinner H6, do not have a separate glue layer around the dwc3. Instead, they rely on the clocks/resets/phys referenced from the dwc3 DT node itself. Add support for enabling the clocks/resets referenced from the dwc3 DT node. Signed-off-by: Samuel Holland Signed-off-by: Andre Przywara --- drivers/usb/host/xhci-dwc3.c | 56 ++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 3e0ae80cec..5b12d1358e 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -7,10 +7,12 @@ * Author: Ramneek Mehresh */ +#include #include #include #include #include +#include #include #include #include @@ -21,7 +23,9 @@ #include struct xhci_dwc3_plat { + struct clk_bulk clks; struct phy_bulk phys; + struct reset_ctl_bulk resets; }; void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) @@ -111,6 +115,46 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) } #if CONFIG_IS_ENABLED(DM_USB) +static int xhci_dwc3_reset_init(struct udevice *dev, + struct xhci_dwc3_plat *plat) +{ + int ret; + + ret = reset_get_bulk(dev, &plat->resets); + if (ret == -ENOTSUPP || ret == -ENOENT) + return 0; + else if (ret) + return ret; + + ret = reset_deassert_bulk(&plat->resets); + if (ret) { + reset_release_bulk(&plat->resets); + return ret; + } + + return 0; +} + +static int xhci_dwc3_clk_init(struct udevice *dev, + struct xhci_dwc3_plat *plat) +{ + int ret; + + ret = clk_get_bulk(dev, &plat->clks); + if (ret == -ENOSYS || ret == -ENOENT) + return 0; + if (ret) + return ret; + + ret = clk_enable_bulk(&plat->clks); + if (ret) { + clk_release_bulk(&plat->clks); + return ret; + } + + return 0; +} + static int xhci_dwc3_probe(struct udevice *dev) { struct xhci_hcor *hcor; @@ -122,6 +166,14 @@ static int xhci_dwc3_probe(struct udevice *dev) u32 reg; int ret; + ret = xhci_dwc3_reset_init(dev, plat); + if (ret) + return ret; + + ret = xhci_dwc3_clk_init(dev, plat); + if (ret) + return ret; + hccr = (struct xhci_hccr *)((uintptr_t)dev_remap_addr(dev)); hcor = (struct xhci_hcor *)((uintptr_t)hccr + HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); @@ -171,6 +223,10 @@ static int xhci_dwc3_remove(struct udevice *dev) dwc3_shutdown_phy(dev, &plat->phys); + clk_release_bulk(&plat->clks); + + reset_release_bulk(&plat->resets); + return xhci_deregister(dev); } From 672ee240d978354882bca1ec5cdd1a7a462cc597 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Mon, 5 Jul 2021 13:29:04 +0100 Subject: [PATCH 25/51] configs: Enable USB3 on Allwinner H6 boards Pine H64 and Orange Pi 3 both provide a USB3 type A port. Enable it in U-Boot. Signed-off-by: Samuel Holland Signed-off-by: Andre Przywara --- configs/orangepi_3_defconfig | 5 +++++ configs/pine_h64_defconfig | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig index c243a58200..ebecf49ebd 100644 --- a/configs/orangepi_3_defconfig +++ b/configs/orangepi_3_defconfig @@ -8,5 +8,10 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_BLUETOOTH_DT_DEVICE_FIXUP="brcm,bcm4345c5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_PHY_SUN50I_USB3=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 4e621db0c0..1928509dd7 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -12,5 +12,10 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SUN8I_EMAC=y +CONFIG_PHY_SUN50I_USB3=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set From 950cb1f25f0bf7aaa83db41b14fc2aaab214125c Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 20 Sep 2021 15:37:22 +0200 Subject: [PATCH 26/51] usb: add support for ULPI/SERIAL/HSIC PHY modes Import usb_phy_interface enum values and DT match strings from the Linux kernel. Signed-off-by: Markus Niebel Signed-off-by: Matthias Schiffer --- drivers/usb/common/common.c | 3 +++ include/linux/usb/phy.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c index 2a47f40bba..43564c9fba 100644 --- a/drivers/usb/common/common.c +++ b/drivers/usb/common/common.c @@ -80,6 +80,9 @@ static const char *const usbphy_modes[] = { [USBPHY_INTERFACE_MODE_UNKNOWN] = "", [USBPHY_INTERFACE_MODE_UTMI] = "utmi", [USBPHY_INTERFACE_MODE_UTMIW] = "utmi_wide", + [USBPHY_INTERFACE_MODE_ULPI] = "ulpi", + [USBPHY_INTERFACE_MODE_SERIAL] = "serial", + [USBPHY_INTERFACE_MODE_HSIC] = "hsic", }; enum usb_phy_interface usb_get_phy_mode(ofnode node) diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h index 1e1217a958..14b2c7eb2e 100644 --- a/include/linux/usb/phy.h +++ b/include/linux/usb/phy.h @@ -16,6 +16,9 @@ enum usb_phy_interface { USBPHY_INTERFACE_MODE_UNKNOWN, USBPHY_INTERFACE_MODE_UTMI, USBPHY_INTERFACE_MODE_UTMIW, + USBPHY_INTERFACE_MODE_ULPI, + USBPHY_INTERFACE_MODE_SERIAL, + USBPHY_INTERFACE_MODE_HSIC, }; #if CONFIG_IS_ENABLED(DM_USB) From f2a4c890e390eb0e5d131a027a259801e8f07ff3 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 20 Sep 2021 15:37:23 +0200 Subject: [PATCH 27/51] include/configs: replace MXC_EHCI_MODE_SERIAL with PORT_PTS_SERIAL The MXC_EHCI_MODE_ definitions are redundant. Replace MXC_EHCI_MODE_SERIAL with the equivalent PORT_PTS_SERIAL. Only the zmx25 platform is affected. Signed-off-by: Markus Niebel Signed-off-by: Matthias Schiffer --- include/configs/zmx25.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 88a885463d..8b571da021 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -57,7 +57,7 @@ #define CONFIG_USB_EHCI_MXC #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL +#define CONFIG_MXC_USB_PORTSC PORT_PTS_SERIAL #define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN) #define CONFIG_EHCI_IS_TDI #endif /* CONFIG_CMD_USB */ From 8709228b5c61d56c21461a797b12e275bdd3c044 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 20 Sep 2021 15:37:24 +0200 Subject: [PATCH 28/51] usb: ehci-ci: remove redundant PORTSC flag definitions These definitions are unused, all boards that define portsc flags use the equivalent PORT_* definitions instead. Signed-off-by: Markus Niebel Signed-off-by: Matthias Schiffer --- include/usb/ehci-ci.h | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index efb2eec5ce..bf5d26faa5 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -249,17 +249,6 @@ struct usb_ehci { * For MXC SOCs */ -/* values for portsc field */ -#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) -#define MXC_EHCI_FORCE_FS (1 << 24) -#define MXC_EHCI_UTMI_8BIT (0 << 28) -#define MXC_EHCI_UTMI_16BIT (1 << 28) -#define MXC_EHCI_SERIAL (1 << 29) -#define MXC_EHCI_MODE_UTMI (0 << 30) -#define MXC_EHCI_MODE_PHILIPS (1 << 30) -#define MXC_EHCI_MODE_ULPI (2 << 30) -#define MXC_EHCI_MODE_SERIAL (3 << 30) - /* values for flags field */ #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) #define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) From 0f513c5975105a8cfdf80cc9862e4c65826ead84 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 20 Sep 2021 15:37:25 +0200 Subject: [PATCH 29/51] usb: ehci-mx6: use phy_type from device tree Allow using different PHY interfaces for multiple USB controllers. When no value is set in DT, we fall back to CONFIG_MXC_USB_PORTSC for now to stay compatible with current board configurations. This also adds support for the HSIC mode of the i.MX7. Signed-off-by: Markus Niebel Signed-off-by: Matthias Schiffer --- drivers/usb/host/ehci-mx6.c | 25 +++++++++++++++++++++++-- include/usb/ehci-ci.h | 1 + 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index c3e4170513..1bd6147c76 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "ehci.h" @@ -435,6 +436,7 @@ struct ehci_mx6_priv_data { struct clk clk; struct phy phy; enum usb_init_type init_type; + enum usb_phy_interface phy_type; #if !defined(CONFIG_PHY) int portnr; void __iomem *phy_addr; @@ -443,6 +445,24 @@ struct ehci_mx6_priv_data { #endif }; +static u32 mx6_portsc(enum usb_phy_interface phy_type) +{ + switch (phy_type) { + case USBPHY_INTERFACE_MODE_UTMI: + return PORT_PTS_UTMI; + case USBPHY_INTERFACE_MODE_UTMIW: + return PORT_PTS_UTMI | PORT_PTS_PTW; + case USBPHY_INTERFACE_MODE_ULPI: + return PORT_PTS_ULPI; + case USBPHY_INTERFACE_MODE_SERIAL: + return PORT_PTS_SERIAL; + case USBPHY_INTERFACE_MODE_HSIC: + return PORT_PTS_HSIC; + default: + return CONFIG_MXC_USB_PORTSC; + } +} + static int mx6_init_after_reset(struct ehci_ctrl *dev) { struct ehci_mx6_priv_data *priv = dev->priv; @@ -479,7 +499,7 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) return 0; setbits_le32(&ehci->usbmode, CM_HOST); - writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + writel(mx6_portsc(priv->phy_type), &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); mdelay(10); @@ -641,6 +661,7 @@ static int ehci_usb_probe(struct udevice *dev) priv->ehci = ehci; priv->init_type = type; + priv->phy_type = usb_get_phy_mode(dev_ofnode(dev)); #if CONFIG_IS_ENABLED(CLK) ret = clk_get_by_index(dev, 0, &priv->clk); @@ -690,7 +711,7 @@ static int ehci_usb_probe(struct udevice *dev) if (priv->init_type == USB_INIT_HOST) { setbits_le32(&ehci->usbmode, CM_HOST); - writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + writel(mx6_portsc(priv->phy_type), &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); } diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index bf5d26faa5..2cdb3146e8 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -23,6 +23,7 @@ #define PORT_PTS_ULPI (2 << 30) #define PORT_PTS_SERIAL (3 << 30) #define PORT_PTS_PTW (1 << 28) +#define PORT_PTS_HSIC (1 << 25) #define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */ #define PORT_PTS_PHCD (1 << 23) #define PORT_PP (1 << 12) From 53eed9adfac17921511ebf9e00c429bcb385d231 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Thu, 16 Sep 2021 16:00:09 +0200 Subject: [PATCH 30/51] usb: xhci-dwc3: Add support for USB 3.1 controllers This adds support for the DWC_sub31 controllers such as those found on Apple's M1 SoC. This version of the controller seems to work fine with the existing driver. Signed-off-by: Mark Kettenis --- drivers/usb/host/xhci-dwc3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 5b12d1358e..bec0d98081 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -74,7 +74,8 @@ int dwc3_core_init(struct dwc3 *dwc3_reg) revision = readl(&dwc3_reg->g_snpsid); /* This should read as U3 followed by revision number */ - if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { + if ((revision & DWC3_GSNPSID_MASK) != 0x55330000 && + (revision & DWC3_GSNPSID_MASK) != 0x33310000) { puts("this is not a DesignWare USB3 DRD Core\n"); return -1; } From e984db0f9b2cf562cbf878d363e00203725c7bfe Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:29 +0200 Subject: [PATCH 31/51] arm: socfpga: vining: Drop meaningless comment The comment is no longer meaningful due to DT conversion, drop it. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- include/configs/socfpga_vining_fpga.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 06976d804c..38a7753589 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -17,8 +17,6 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* Extra Environment */ #define CONFIG_HOSTNAME "socfpga_vining_fpga" From 513f7d1c5d65a0be1d19b1898eeb4c8a24e05e4e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:30 +0200 Subject: [PATCH 32/51] arm: socfpga: vining: Increase environment size Increase the environment size from 4k to 16k to prevent environment from becoming full. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- configs/socfpga_vining_fpga_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index b418efbf89..452e5b48f3 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y From 3cb04b895df7b18b32ce9d91b82a9cb82047b795 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:31 +0200 Subject: [PATCH 33/51] arm: socfpga: vining: Set USB gadget manufacturer to Softing with capital S This was configured in downstream, so it is likely that most of the custom software used around the device depends on it. Make upstream compatible. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- configs/socfpga_vining_fpga_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 452e5b48f3..5d8970e57c 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -91,7 +91,7 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="softing" +CONFIG_USB_GADGET_MANUFACTURER="Softing" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y From 4e106ef9efd7d309c5f830c5ee0e99e62a96a508 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:32 +0200 Subject: [PATCH 34/51] arm: socfpga: vining: Set default SPI NOR mode and frequency The SPI NOR bus mode is 0 on this system, update it accordingly. Increase frequency to 40 MHz and enable SFDP parsing, since the flashes on this system support that and it is a huge performance improvement. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- configs/socfpga_vining_fpga_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 5d8970e57c..4dcf4f7bf9 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -74,6 +74,9 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70 CONFIG_MMC_DW=y CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set From e21bbffa1d6d2634dabee393dd342764e2931441 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:33 +0200 Subject: [PATCH 35/51] arm: socfpga: vining: Un-disable WDT in DT The WDT on this system should be enabled, make it so. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 2e4468e8d8..9e8be28200 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -15,10 +15,6 @@ }; }; -&watchdog0 { - status = "disabled"; -}; - &mmc { status = "disabled"; }; From c3880e65975bd40ba025b9fafa5732a98ea9e736 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:34 +0200 Subject: [PATCH 36/51] arm: socfpga: vining: Fix UDC controller phandle in DT The USB peripheral controller is the DWC2 controller 1, not 0. Update the phandle to fix UDC support on this board. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 9e8be28200..fb05c31d87 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -11,7 +11,7 @@ /{ aliases { spi0 = "/soc/spi@ff705000"; - udc0 = &usb0; + udc0 = &usb1; }; }; From cb3ed86cf1f4ba97250cf3649a2d43012dd661fd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:35 +0200 Subject: [PATCH 37/51] arm: socfpga: vining: Enable DW I2C driver The Designware I2C IP is used to communicate with I2C peripherals on SoCFPGA, and required to access I2C EEPROM on this board. Enable it. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- configs/socfpga_vining_fpga_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 4dcf4f7bf9..cbdb897f19 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -56,6 +56,7 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y CONFIG_LED_STATUS0=y From b207cc92a2e74774f05df2b281a7f530e76d1f61 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:36 +0200 Subject: [PATCH 38/51] arm: socfpga: vining: Let DWMAC configure PHY reset GPIO The DM DWMAC driver is perfectly capable of configuring the ethernet PHY reset GPIO, let the driver do it instead of doing it in the board file. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- board/softing/vining_fpga/socfpga.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c index aaedf03450..2299227391 100644 --- a/board/softing/vining_fpga/socfpga.c +++ b/board/softing/vining_fpga/socfpga.c @@ -23,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; */ int board_late_init(void) { - const unsigned int phy_nrst_gpio = 0; const unsigned int usb_nrst_gpio = 35; int ret; @@ -33,12 +32,6 @@ int board_late_init(void) /* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio"); - if (!ret) - gpio_direction_output(phy_nrst_gpio, 1); - else - printf("Cannot remove PHY from reset!\n"); - ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio"); if (!ret) gpio_direction_output(usb_nrst_gpio, 1); From 532010da67329a1c3dbe92a167486df6e61d4f4a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:20:19 +0200 Subject: [PATCH 39/51] ddr: altera: use KBUILD_BASENAME instead of __FILE__ The KBUILD_BASENAME contains just the name of the compiled module, in this case 'sequencer', rather than a full path to the compiled file. Use it to prevent pulling the full path into the U-Boot binary, which is useless and annoying. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- drivers/ddr/altera/sequencer.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 6b9b2e9094..8a016f0628 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3714,7 +3714,7 @@ static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass) u32 debug_info; if (pass) { - debug("%s: CALIBRATION PASSED\n", __FILE__); + debug(KBUILD_BASENAME ": CALIBRATION PASSED\n"); seq->gbl.fom_in /= 2; seq->gbl.fom_out /= 2; @@ -3733,7 +3733,7 @@ static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass) writel(debug_info, &phy_mgr_cfg->cal_debug_info); writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status); } else { - debug("%s: CALIBRATION FAILED\n", __FILE__); + debug(KBUILD_BASENAME ": CALIBRATION FAILED\n"); debug_info = seq->gbl.error_stage; debug_info |= seq->gbl.error_substage << 8; @@ -3750,7 +3750,7 @@ static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass) writel(debug_info, &sdr_reg_file->failing_stage); } - debug("%s: Calibration complete\n", __FILE__); + debug(KBUILD_BASENAME ": Calibration complete\n"); } /** @@ -3934,7 +3934,7 @@ int sdram_calibration_full(struct socfpga_sdr *sdr) initialize_tracking(&seq); - debug("%s: Preparing to start memory calibration\n", __FILE__); + debug(KBUILD_BASENAME ": Preparing to start memory calibration\n"); debug("%s:%d\n", __func__, __LINE__); debug_cond(DLEVEL >= 1, From 8870daaa25feee6ab73ec2e52f731a19131cc314 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Fri, 23 Jul 2021 06:18:26 -0600 Subject: [PATCH 40/51] test/py: tpm2: Skip tpm pytest based on env variable Tpm test cases relies on tpm device setup. Provide an environment variable "env__tpm_device_test_skip = True" to skip the test case if tpm device is not present. Only needed will have to add variable to the py-test framework. Test runs successfully even this variable is absent. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma Acked-by: Ilias Apalodimas --- test/py/tests/test_tpm2.py | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/test/py/tests/test_tpm2.py b/test/py/tests/test_tpm2.py index ac04f7191e..c7a9dc19bd 100644 --- a/test/py/tests/test_tpm2.py +++ b/test/py/tests/test_tpm2.py @@ -18,6 +18,15 @@ any password. * Commands like pcr_setauthpolicy and pcr_resetauthpolicy are not implemented here because they would fail the tests in most cases (TPMs do not implement them and return an error). + + +Note: +This test doesn't rely on boardenv_* configuration value but can change test +behavior. + +* Setup env__tpm_device_test_skip to True if tests with TPM devices should be +skipped. + """ updates = 0 @@ -29,6 +38,9 @@ def force_init(u_boot_console, force=False): twice will spawn an error used to detect that the TPM was not reset and no initialization code should be run. """ + skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) + if skip_test: + pytest.skip('skip TPM device test') output = u_boot_console.run_command('tpm2 init') if force or not 'Error' in output: u_boot_console.run_command('echo --- start of init ---') @@ -44,6 +56,10 @@ def force_init(u_boot_console, force=False): def test_tpm2_init(u_boot_console): """Init the software stack to use TPMv2 commands.""" + skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) + if skip_test: + pytest.skip('skip TPM device test') + u_boot_console.run_command('tpm2 init') output = u_boot_console.run_command('echo $?') assert output.endswith('0') @@ -55,6 +71,9 @@ def test_tpm2_startup(u_boot_console): Initiate the TPM internal state machine. """ + skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) + if skip_test: + pytest.skip('skip TPM device test') u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR') output = u_boot_console.run_command('echo $?') assert output.endswith('0') @@ -66,6 +85,9 @@ def test_tpm2_self_test_full(u_boot_console): Ask the TPM to perform all self tests to also enable full capabilities. """ + skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) + if skip_test: + pytest.skip('skip TPM device test') u_boot_console.run_command('tpm2 self_test full') output = u_boot_console.run_command('echo $?') assert output.endswith('0') @@ -78,6 +100,9 @@ def test_tpm2_continue_self_test(u_boot_console): to enter a fully operational state. """ + skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) + if skip_test: + pytest.skip('skip TPM device test') u_boot_console.run_command('tpm2 self_test continue') output = u_boot_console.run_command('echo $?') assert output.endswith('0') @@ -95,6 +120,9 @@ def test_tpm2_clear(u_boot_console): PLATFORM hierarchies are also available. """ + skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) + if skip_test: + pytest.skip('skip TPM device test') u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT') output = u_boot_console.run_command('echo $?') assert output.endswith('0') From 9aab28b6f2c223912cc195833d1877ef70bfb5ba Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 16 Sep 2021 10:59:12 +0200 Subject: [PATCH 41/51] scripts/mailmapper: enable running with Python 3 Our mailmapper script required Python 2 which is no longer maintained. A main difference when converting to Python 3 is that byte strings are not character strings. So add conversion and skip over conversion errors. Signed-off-by: Heinrich Schuchardt --- scripts/mailmapper | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/scripts/mailmapper b/scripts/mailmapper index 2e2d7faff5..0e744ec1a0 100755 --- a/scripts/mailmapper +++ b/scripts/mailmapper @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2014, Masahiro Yamada @@ -89,9 +89,10 @@ output = {} for line in shortlog.splitlines(): # tmp, mail = line.rsplit(None, 1) is not safe # because weird email addresses might include whitespaces - tmp, mail = line.split('<') - mail = '<' + mail.rstrip() try: + line = line.decode("utf-8") + tmp, mail = line.split('<') + mail = '<' + mail.rstrip() _, name = tmp.rstrip().split(None, 1) except ValueError: # author name is empty @@ -100,8 +101,11 @@ for line in shortlog.splitlines(): # another name for the same email address prev_name = mail_vs_name[mail] # Take the name with more commits - major_name = sorted([prev_name, name], - key=lambda x: commits_per_name[x] if x else 0)[1] + try: + major_name = sorted([prev_name, name], + key=lambda x: commits_per_name[x] if x else 0)[1] + except: + continue mail_vs_name[mail] = major_name if commits_per_name[major_name] > MIN_COMMITS: output[mail] = major_name From 3bd0e2caa974aa300aadad171abe741d6edbc3b3 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 20 Sep 2021 14:15:03 +0200 Subject: [PATCH 42/51] fs: avoid superfluous messages Output like the following is quite irritating: => bootefi hello Scanning disk mmc2.blk... No valid Btrfs found Bad magic number for SquashFS image. ** Unrecognized filesystem type ** Scanning disk mmc1.blk... No valid Btrfs found Bad magic number for SquashFS image. ** Unrecognized filesystem type ** Scanning disk mmc0.blk... No valid Btrfs found Bad magic number for SquashFS image. ** Unrecognized filesystem type ** Albeit a whole disk may be formatted with a filesystem in most cases a partition table is used and the whole disk (partition number 0) doesn't contain a filesytem. Some partitions may only contain a blob. Not seeing a filesytem on the whole disk or on any partition is only worth a debug message. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- fs/fs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/fs.c b/fs/fs.c index 7c682582c8..023f89cafe 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -37,7 +37,7 @@ static int fs_type = FS_TYPE_ANY; static inline int fs_probe_unsupported(struct blk_desc *fs_dev_desc, struct disk_partition *fs_partition) { - log_err("** Unrecognized filesystem type **\n"); + log_debug("Unrecognized filesystem type\n"); return -1; } From 6941ff7619073ee316df104ada917076bf1eaa2f Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 21 Sep 2021 18:18:51 +0200 Subject: [PATCH 43/51] MAINTAINERS: remove SPEAR entry As the lastest spear directories are removed, delete the associated entry in the MAINTAINERS file: - arch/arm/cpu/arm926ejs/spear/ - arch/arm/include/asm/arch-spear/ Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support") Signed-off-by: Patrick Delaunay Reviewed-by: Bin Meng --- MAINTAINERS | 7 ------- 1 file changed, 7 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 67c96a6045..5370b55064 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -412,13 +412,6 @@ F: include/dt-bindings/clock/stih407-clks.h F: include/dt-bindings/clock/stih410-clks.h F: include/dt-bindings/reset/stih407-resets.h -ARM STM SPEAR -#M: Vipin Kumar -S: Orphaned (Since 2016-02) -T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git -F: arch/arm/cpu/arm926ejs/spear/ -F: arch/arm/include/asm/arch-spear/ - ARM STM STM32MP M: Patrick Delaunay M: Patrice Chotard From cff383caa30e1bcdbb2d66aea39b8f1963f1e962 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 21 Sep 2021 17:35:06 +0100 Subject: [PATCH 44/51] Taking over responsibility for GE boards from Sebastian I am taking over responsibility for the GE board from Sebastian Reichel. Updating the MAINTAINERS files to reflect this. Signed-off-by: Martyn Welch Acked-by: Sebastian Reichel --- board/ge/b1x5v2/MAINTAINERS | 2 +- board/ge/bx50v3/MAINTAINERS | 2 +- board/ge/mx53ppd/MAINTAINERS | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/ge/b1x5v2/MAINTAINERS b/board/ge/b1x5v2/MAINTAINERS index f22d492835..3196ddbb51 100644 --- a/board/ge/b1x5v2/MAINTAINERS +++ b/board/ge/b1x5v2/MAINTAINERS @@ -1,7 +1,7 @@ GE B1X5V2 BOARD M: Huan 'Kitty' Wang M: Ian Ray -M: Sebastian Reichel +M: Martyn Welch S: Maintained F: arch/arm/dts/imx6dl-b1x5v2.dts F: board/ge/b1x5v2/ diff --git a/board/ge/bx50v3/MAINTAINERS b/board/ge/bx50v3/MAINTAINERS index fafbd78c2a..c165048336 100644 --- a/board/ge/bx50v3/MAINTAINERS +++ b/board/ge/bx50v3/MAINTAINERS @@ -1,6 +1,6 @@ GE BX50V3 BOARD M: Ian Ray -M: Sebastian Reichel +M: Martyn Welch S: Maintained F: arch/arm/dts/imx6q-b450v3.dts F: arch/arm/dts/imx6q-b650v3.dts diff --git a/board/ge/mx53ppd/MAINTAINERS b/board/ge/mx53ppd/MAINTAINERS index 2c06c8ee86..146a460e7e 100644 --- a/board/ge/mx53ppd/MAINTAINERS +++ b/board/ge/mx53ppd/MAINTAINERS @@ -1,7 +1,7 @@ GE PPD BOARD M: Antti Mäentausta M: Ian Ray -M: Sebastian Reichel +M: Martyn Welch S: Maintained F: arch/arm/dts/imx53-ppd* F: board/ge/mx53ppd/ From b071431d52e38220f4627e21c61ea82e47680e2f Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 22 Sep 2021 11:02:26 +0200 Subject: [PATCH 45/51] mtd: remove SPEAr flash driver st_smi Remove the driver st_smic.c used in SPEAr products and the associated config CONFIG_ST_SMI; this driver is no more used in U-Boot after the commit 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support"). Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support") Signed-off-by: Patrick Delaunay Reviewed-by: Stefan Roese Reviewed-by: Tom Rini --- drivers/mtd/Makefile | 1 - drivers/mtd/st_smi.c | 565 ----------------------------------- include/configs/bcmstb.h | 1 - include/linux/mtd/st_smi.h | 100 ------- scripts/config_whitelist.txt | 1 - 5 files changed, 668 deletions(-) delete mode 100644 drivers/mtd/st_smi.c delete mode 100644 include/linux/mtd/st_smi.h diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 6d77ebfaa5..ce0451108e 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -12,7 +12,6 @@ mtd-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o mtd-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o mtd-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o mtd-$(CONFIG_FLASH_PIC32) += pic32_flash.o -mtd-$(CONFIG_ST_SMI) += st_smi.o mtd-$(CONFIG_STM32_FLASH) += stm32_flash.o mtd-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o mtd-$(CONFIG_HBMC_AM654) += hbmc-am654.o diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c deleted file mode 100644 index 7c652e6c53..0000000000 --- a/drivers/mtd/st_smi.c +++ /dev/null @@ -1,565 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com. - */ - -#include -#include -#include -#include -#include - -#include -#include - -#if defined(CONFIG_MTD_NOR_FLASH) - -static struct smi_regs *const smicntl = - (struct smi_regs * const)CONFIG_SYS_SMI_BASE; -static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = - CONFIG_SYS_FLASH_ADDR_BASE; -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/* data structure to maintain flash ids from different vendors */ -struct flash_device { - char *name; - u8 erase_cmd; - u32 device_id; - u32 pagesize; - unsigned long sectorsize; - unsigned long size_in_bytes; -}; - -#define FLASH_ID(n, es, id, psize, ssize, size) \ -{ \ - .name = n, \ - .erase_cmd = es, \ - .device_id = id, \ - .pagesize = psize, \ - .sectorsize = ssize, \ - .size_in_bytes = size \ -} - -/* - * List of supported flash devices. - * Currently the erase_cmd field is not used in this driver. - */ -static struct flash_device flash_devices[] = { - FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000), - FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000), - FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000), - FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000), - FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000), - FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000), - FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000), - FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000), - FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000), - FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000), - FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000), - FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000), - FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000), - FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000), - FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000), - FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000), - FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000), - FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000), - FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000), - FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000), - FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000), - FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000), - FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000), - FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000), - FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000), - FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000), - FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), - FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), - FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000), - FLASH_ID("wbd w25q128" , 0xd8, 0x001840EF, 0x100, 0x10000, 0x1000000), -}; - -/* - * smi_wait_xfer_finish - Wait until TFF is set in status register - * @timeout: timeout in milliseconds - * - * Wait until TFF is set in status register - */ -static int smi_wait_xfer_finish(int timeout) -{ - ulong start = get_timer(0); - - while (get_timer(start) < timeout) { - if (readl(&smicntl->smi_sr) & TFF) - return 0; - - /* Try after 10 ms */ - udelay(10); - }; - - return -1; -} - -/* - * smi_read_id - Read flash id - * @info: flash_info structure pointer - * @banknum: bank number - * - * Read the flash id present at bank #banknum - */ -static unsigned int smi_read_id(flash_info_t *info, int banknum) -{ - unsigned int value; - - writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); - writel(READ_ID, &smicntl->smi_tr); - writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3, - &smicntl->smi_cr2); - - if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) - return -EIO; - - value = (readl(&smicntl->smi_rr) & 0x00FFFFFF); - - writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr); - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); - - return value; -} - -/* - * flash_get_size - Detect the SMI flash by reading the ID. - * @base: Base address of the flash area bank #banknum - * @banknum: Bank number - * - * Detect the SMI flash by reading the ID. Initializes the flash_info structure - * with size, sector count etc. - */ -static ulong flash_get_size(ulong base, int banknum) -{ - flash_info_t *info = &flash_info[banknum]; - int value; - int i; - - value = smi_read_id(info, banknum); - - if (value < 0) { - printf("Flash id could not be read\n"); - return 0; - } - - /* Matches chip-id to entire list of 'serial-nor flash' ids */ - for (i = 0; i < ARRAY_SIZE(flash_devices); i++) { - if (flash_devices[i].device_id == value) { - info->size = flash_devices[i].size_in_bytes; - info->flash_id = value; - info->start[0] = base; - info->sector_count = - info->size/flash_devices[i].sectorsize; - - return info->size; - } - } - - return 0; -} - -/* - * smi_read_sr - Read status register of SMI - * @bank: bank number - * - * This routine will get the status register of the flash chip present at the - * given bank - */ -static int smi_read_sr(int bank) -{ - u32 ctrlreg1, val; - - /* store the CTRL REG1 state */ - ctrlreg1 = readl(&smicntl->smi_cr1); - - /* Program SMI in HW Mode */ - writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE), - &smicntl->smi_cr1); - - /* Performing a RSR instruction in HW mode */ - writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2); - - if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) - return -1; - - val = readl(&smicntl->smi_sr); - - /* Restore the CTRL REG1 state */ - writel(ctrlreg1, &smicntl->smi_cr1); - - return val; -} - -/* - * smi_wait_till_ready - Wait till last operation is over. - * @bank: bank number shifted. - * @timeout: timeout in milliseconds. - * - * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0) - * The routine checks for #timeout loops, each at interval of 1 milli-second. - * If successful the routine returns 0. - */ -static int smi_wait_till_ready(int bank, int timeout) -{ - int sr; - ulong start = get_timer(0); - - /* One chip guarantees max 5 msec wait here after page writes, - but potentially three seconds (!) after page erase. */ - while (get_timer(start) < timeout) { - sr = smi_read_sr(bank); - if ((sr >= 0) && (!(sr & WIP_BIT))) - return 0; - - /* Try again after 10 usec */ - udelay(10); - } while (timeout--); - - printf("SMI controller is still in wait, timeout=%d\n", timeout); - return -EIO; -} - -/* - * smi_write_enable - Enable the flash to do write operation - * @bank: bank number - * - * Set write enable latch with Write Enable command. - * Returns negative if error occurred. - */ -static int smi_write_enable(int bank) -{ - u32 ctrlreg1; - u32 start; - int timeout = WMODE_TOUT; - int sr; - - /* Store the CTRL REG1 state */ - ctrlreg1 = readl(&smicntl->smi_cr1); - - /* Program SMI in H/W Mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); - - /* Give the Flash, Write Enable command */ - writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2); - - if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) - return -1; - - /* Restore the CTRL REG1 state */ - writel(ctrlreg1, &smicntl->smi_cr1); - - start = get_timer(0); - while (get_timer(start) < timeout) { - sr = smi_read_sr(bank); - if ((sr >= 0) && (sr & (1 << (bank + WM_SHIFT)))) - return 0; - - /* Try again after 10 usec */ - udelay(10); - }; - - return -1; -} - -/* - * smi_init - SMI initialization routine - * - * SMI initialization routine. Sets SMI control register1. - */ -void smi_init(void) -{ - /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ - writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, - &smicntl->smi_cr1); -} - -/* - * smi_sector_erase - Erase flash sector - * @info: flash_info structure pointer - * @sector: sector number - * - * Set write enable latch with Write Enable command. - * Returns negative if error occurred. - */ -static int smi_sector_erase(flash_info_t *info, unsigned int sector) -{ - int bank; - unsigned int sect_add; - unsigned int instruction; - - switch (info->start[0]) { - case SMIBANK0_BASE: - bank = BANK0; - break; - case SMIBANK1_BASE: - bank = BANK1; - break; - case SMIBANK2_BASE: - bank = BANK2; - break; - case SMIBANK3_BASE: - bank = BANK3; - break; - default: - return -1; - } - - sect_add = sector * (info->size / info->sector_count); - instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE; - - writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr); - - /* Wait until finished previous write command. */ - if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) - return -EBUSY; - - /* Send write enable, before erase commands. */ - if (smi_write_enable(bank)) - return -EIO; - - /* Put SMI in SW mode */ - writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); - - /* Send Sector Erase command in SW Mode */ - writel(instruction, &smicntl->smi_tr); - writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, - &smicntl->smi_cr2); - if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) - return -EIO; - - if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) - return -EBUSY; - - /* Put SMI in HW mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, - &smicntl->smi_cr1); - - return 0; -} - -/* - * smi_write - Write to SMI flash - * @src_addr: source buffer - * @dst_addr: destination buffer - * @length: length to write in bytes - * @bank: bank base address - * - * Write to SMI flash - */ -static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, - unsigned int length, ulong bank_addr) -{ - u8 *src_addr8 = (u8 *)src_addr; - u8 *dst_addr8 = (u8 *)dst_addr; - int banknum; - int i; - - switch (bank_addr) { - case SMIBANK0_BASE: - banknum = BANK0; - break; - case SMIBANK1_BASE: - banknum = BANK1; - break; - case SMIBANK2_BASE: - banknum = BANK2; - break; - case SMIBANK3_BASE: - banknum = BANK3; - break; - default: - return -1; - } - - if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) - return -EBUSY; - - /* Set SMI in Hardware Mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); - - if (smi_write_enable(banknum)) - return -EIO; - - /* Perform the write command */ - for (i = 0; i < length; i += 4) { - if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) { - if (smi_wait_till_ready(banknum, - CONFIG_SYS_FLASH_WRITE_TOUT)) - return -EBUSY; - - if (smi_write_enable(banknum)) - return -EIO; - } - - if (length < 4) { - int k; - - /* - * Handle special case, where length < 4 (redundant env) - */ - for (k = 0; k < length; k++) - *dst_addr8++ = *src_addr8++; - } else { - /* Normal 32bit write */ - *dst_addr++ = *src_addr++; - } - - if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2))) - return -EIO; - } - - if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) - return -EBUSY; - - writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr); - - return 0; -} - -/* - * write_buff - Write to SMI flash - * @info: flash info structure - * @src: source buffer - * @dest_addr: destination buffer - * @length: length to write in words - * - * Write to SMI flash - */ -int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length) -{ - return smi_write((unsigned int *)src, (unsigned int *)dest_addr, - length, info->start[0]); -} - -/* - * flash_init - SMI flash initialization - * - * SMI flash initialization - */ -unsigned long flash_init(void) -{ - unsigned long size = 0; - int i, j; - - smi_init(); - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(bank_base[i], i); - } - - for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) { - for (i = 1; i < flash_info[j].sector_count; i++) - flash_info[j].start[i] = - flash_info[j].start[i - 1] + - flash_info->size / flash_info->sector_count; - - } - - return size; -} - -/* - * flash_print_info - Print SMI flash information - * - * Print SMI flash information - */ -void flash_print_info(flash_info_t *info) -{ - int i; - if (info->flash_id == FLASH_UNKNOWN) { - puts("missing or unknown FLASH type\n"); - return; - } - - if (info->size >= 0x100000) - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - else - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - puts(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { -#ifdef CONFIG_SYS_FLASH_EMPTY_INFO - int size; - int erased; - u32 *flash; - - /* - * Check if whole sector is erased - */ - size = (info->size) / (info->sector_count); - flash = (u32 *) info->start[i]; - size = size / sizeof(int); - - while ((size--) && (*flash++ == ~0)) - ; - - size++; - if (size) - erased = 0; - else - erased = 1; - - if ((i % 5) == 0) - printf("\n"); - - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO) " : " "); -#endif - } - putc('\n'); - return; -} - -/* - * flash_erase - Erase SMI flash - * - * Erase SMI flash - */ -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot = 0; - flash_sect_t sect; - - if ((s_first < 0) || (s_first > s_last)) { - puts("- no sectors to erase\n"); - return 1; - } - - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - putc('\n'); - } - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { - if (smi_sector_erase(info, sect)) - rcode = 1; - else - putc('.'); - } - } - puts(" done\n"); - return rcode; -} -#endif diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 2660d18f35..d7f9e5bc06 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -130,7 +130,6 @@ extern phys_addr_t prior_stage_fdt_address; /* * Flash configuration. */ -#define CONFIG_ST_SMI #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_MACRONIX diff --git a/include/linux/mtd/st_smi.h b/include/linux/mtd/st_smi.h deleted file mode 100644 index 6058969787..0000000000 --- a/include/linux/mtd/st_smi.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - */ - -#ifndef ST_SMI_H -#define ST_SMI_H - -/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ -/* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ - -#define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE -#define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE - -#define SMIBANK0_BASE (FLASH_START_ADDRESS) -#define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) -#define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) -#define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) - -#define BANK0 0 -#define BANK1 1 -#define BANK2 2 -#define BANK3 3 - -struct smi_regs { - u32 smi_cr1; - u32 smi_cr2; - u32 smi_sr; - u32 smi_tr; - u32 smi_rr; -}; - -/* CONTROL REG 1 */ -#define BANK_EN 0x0000000F /* enables all banks */ -#define DSEL_TIME 0x00000060 /* Deselect time */ -#define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ -#define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ -#define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ -#define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ -#define SW_MODE 0x10000000 /* enables SW Mode */ -#define WB_MODE 0x20000000 /* Write Burst Mode */ -#define FAST_MODE 0x00008000 /* Fast Mode */ -#define HOLD1 0x00010000 - -/* CONTROL REG 2 */ -#define RD_STATUS_REG 0x00000400 /* reads status reg */ -#define WE 0x00000800 /* Write Enable */ -#define BANK0_SEL 0x00000000 /* Select Banck0 */ -#define BANK1_SEL 0x00001000 /* Select Banck1 */ -#define BANK2_SEL 0x00002000 /* Select Banck2 */ -#define BANK3_SEL 0x00003000 /* Select Banck3 */ -#define BANKSEL_SHIFT 12 -#define SEND 0x00000080 /* Send data */ -#define TX_LEN_1 0x00000001 /* data length = 1 byte */ -#define TX_LEN_2 0x00000002 /* data length = 2 byte */ -#define TX_LEN_3 0x00000003 /* data length = 3 byte */ -#define TX_LEN_4 0x00000004 /* data length = 4 byte */ -#define RX_LEN_1 0x00000010 /* data length = 1 byte */ -#define RX_LEN_2 0x00000020 /* data length = 2 byte */ -#define RX_LEN_3 0x00000030 /* data length = 3 byte */ -#define RX_LEN_4 0x00000040 /* data length = 4 byte */ -#define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ -#define WCIE 0x00000200 /* WCF Interrupt Enable */ - -/* STATUS_REG */ -#define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ -#define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ -#define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ -#define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ -#define RSR 0x00000005 /* Read Status regiser */ -#define TFF 0x00000100 /* Transfer Finished FLag */ -#define WCF 0x00000200 /* Transfer Finished FLag */ -#define ERF1 0x00000400 /* Error Flag 1 */ -#define ERF2 0x00000800 /* Error Flag 2 */ -#define WM0 0x00001000 /* WM Bank 0 */ -#define WM1 0x00002000 /* WM Bank 1 */ -#define WM2 0x00004000 /* WM Bank 2 */ -#define WM3 0x00008000 /* WM Bank 3 */ -#define WM_SHIFT 12 - -/* TR REG */ -#define READ_ID 0x0000009F /* Read Identification */ -#define BULK_ERASE 0x000000C7 /* BULK erase */ -#define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ -#define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ - -struct flash_dev { - u32 density; - ulong size; - ushort sector_count; -}; - -#define SFLASH_PAGE_SIZE 0x100 /* flash page size */ -#define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */ -#define WMODE_TOUT 15 /* write enable timeout(in ms) */ - -extern void smi_init(void); - -#endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ff24ab1873..a9c2380d17 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1427,7 +1427,6 @@ CONFIG_STM32_FLASH CONFIG_STV0991 CONFIG_STV0991_HZ CONFIG_STV0991_HZ_CLOCK -CONFIG_ST_SMI CONFIG_SXNI855T CONFIG_SYSFS CONFIG_SYSMGR_ISWGRP_HANDOFF From 19de51f7a5a9a8e25f2a52033a39c17686d3a4e1 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Wed, 15 Sep 2021 15:01:51 +0200 Subject: [PATCH 46/51] arm: orion5x: edminiv2: change maintainer Since Albert Aribaud is not maintaining anymore the LaCie Ethernet Disk mini V2 board, then I am taking over. Signed-off-by: Simon Guinot Reviewed-by: Tom Rini Reviewed-by: Stefan Roese --- board/LaCie/edminiv2/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/LaCie/edminiv2/MAINTAINERS b/board/LaCie/edminiv2/MAINTAINERS index e0591f4b80..055afd0e76 100644 --- a/board/LaCie/edminiv2/MAINTAINERS +++ b/board/LaCie/edminiv2/MAINTAINERS @@ -1,5 +1,5 @@ EDMINIV2 BOARD -M: Albert ARIBAUD +M: Simon Guinot S: Maintained F: board/LaCie/edminiv2/ F: include/configs/edminiv2.h From 269d2d14d243f214e8eb5c63810d73272d6fd3f3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 19 Sep 2021 15:51:10 -0600 Subject: [PATCH 47/51] doc: Add mention of the /config binding The devicetree binding files are in their own directory and use a simple text format. Add a link for the binding for the /config node, since it is otherwise hard to find. Suggested-by: Heinrich Schuchardt Signed-off-by: Simon Glass Reviewed-by: Heinrich Schuchardt --- doc/develop/config_binding.rst | 10 ++++++++++ doc/develop/index.rst | 1 + 2 files changed, 11 insertions(+) create mode 100644 doc/develop/config_binding.rst diff --git a/doc/develop/config_binding.rst b/doc/develop/config_binding.rst new file mode 100644 index 0000000000..c90e99c7ba --- /dev/null +++ b/doc/develop/config_binding.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot configuration node +========================= + +U-Boot supports a number of runtime configuration options which can be selected +in the devicetree. + +These are documented in +:download:`The /config node <../../doc/device-tree-bindings/config.txt>`. diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 2a32645cfd..24056b10fd 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -12,6 +12,7 @@ Implementation bloblist ci_testing commands + config_binding devicetree/index driver-model/index global_data From 346cee3ac5782fefeaeda2b54914b029547adf52 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Tue, 14 Sep 2021 12:14:31 +0530 Subject: [PATCH 48/51] efi_loader: Fix spec ID event creation TCG EFI Protocol Specification defines the number_of_algorithms field in spec ID event to be equal to the number of active algorithms supported by the TPM device. In current implementation, this field is populated with the count of all algorithms supported by the TPM which leads to incorrect spec ID event creation. Similarly, the algorithm array in spec ID event should be a variable length array with length being equal to the number_of_algorithms field. In current implementation this is defined as a fixed length array which has been fixed. Signed-off-by: Ruchika Gupta CC: Masahisa Kojima CC: Ilias Apalodimas CC: Heinrich Schuchardt Reviewed-by: Ilias Apalodimas --- include/efi_tcg2.h | 7 +----- lib/efi_loader/efi_tcg2.c | 48 ++++++++++++++++++++++----------------- 2 files changed, 28 insertions(+), 27 deletions(-) diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h index 5a1a36212e..8f02d4fb0b 100644 --- a/include/efi_tcg2.h +++ b/include/efi_tcg2.h @@ -165,8 +165,6 @@ struct tcg_efi_spec_id_event_algorithm_size { * @digest_sizes: array of number_of_algorithms pairs * 1st member defines the algorithm id * 2nd member defines the algorithm size - * @vendor_info_size: size in bytes for vendor specific info - * @vendor_info: vendor specific info */ struct tcg_efi_spec_id_event { u8 signature[16]; @@ -176,10 +174,7 @@ struct tcg_efi_spec_id_event { u8 spec_errata; u8 uintn_size; u32 number_of_algorithms; - struct tcg_efi_spec_id_event_algorithm_size digest_sizes[TPM2_NUM_PCR_BANKS]; - u8 vendor_info_size; - /* U-Boot does not provide any vendor info */ - u8 vendor_info[]; + struct tcg_efi_spec_id_event_algorithm_size digest_sizes[]; } __packed; /** diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index cb48919223..d3b8f93f14 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -575,9 +575,10 @@ static efi_status_t tcg2_create_digest(const u8 *input, u32 length, EFI_PRINT("Unsupported algorithm %x\n", hash_alg); return EFI_INVALID_PARAMETER; } + digest_list->digests[digest_list->count].hash_alg = hash_alg; + memcpy(&digest_list->digests[digest_list->count].digest, final, + (u32)alg_to_len(hash_alg)); digest_list->count++; - digest_list->digests[i].hash_alg = hash_alg; - memcpy(&digest_list->digests[i].digest, final, (u32)alg_to_len(hash_alg)); } return EFI_SUCCESS; @@ -798,8 +799,9 @@ static efi_status_t tcg2_hash_pe_image(void *efi, u64 efi_size, EFI_PRINT("Unsupported algorithm %x\n", hash_alg); return EFI_INVALID_PARAMETER; } - digest_list->digests[i].hash_alg = hash_alg; - memcpy(&digest_list->digests[i].digest, hash, (u32)alg_to_len(hash_alg)); + digest_list->digests[digest_list->count].hash_alg = hash_alg; + memcpy(&digest_list->digests[digest_list->count].digest, hash, + (u32)alg_to_len(hash_alg)); digest_list->count++; } @@ -1120,7 +1122,7 @@ static efi_status_t create_specid_event(struct udevice *dev, void *buffer, struct tcg_efi_spec_id_event *spec_event; size_t spec_event_size; efi_status_t ret = EFI_DEVICE_ERROR; - u32 active = 0, supported = 0; + u32 active = 0, supported = 0, pcr_count = 0, alg_count = 0; int err; size_t i; @@ -1142,25 +1144,29 @@ static efi_status_t create_specid_event(struct udevice *dev, void *buffer, TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2; spec_event->uintn_size = sizeof(efi_uintn_t) / sizeof(u32); - err = tpm2_get_pcr_info(dev, &supported, &active, - &spec_event->number_of_algorithms); + err = tpm2_get_pcr_info(dev, &supported, &active, &pcr_count); + if (err) goto out; + + for (i = 0; i < pcr_count; i++) { + u16 hash_alg = hash_algo_list[i].hash_alg; + u16 hash_len = hash_algo_list[i].hash_len; + + if (active & alg_to_mask(hash_alg)) { + put_unaligned_le16(hash_alg, + &spec_event->digest_sizes[alg_count].algorithm_id); + put_unaligned_le16(hash_len, + &spec_event->digest_sizes[alg_count].digest_size); + alg_count++; + } + } + + spec_event->number_of_algorithms = alg_count; if (spec_event->number_of_algorithms > MAX_HASH_COUNT || spec_event->number_of_algorithms < 1) goto out; - for (i = 0; i < spec_event->number_of_algorithms; i++) { - u16 hash_alg = hash_algo_list[i].hash_alg; - u16 hash_len = hash_algo_list[i].hash_len; - - if (active && alg_to_mask(hash_alg)) { - put_unaligned_le16(hash_alg, - &spec_event->digest_sizes[i].algorithm_id); - put_unaligned_le16(hash_len, - &spec_event->digest_sizes[i].digest_size); - } - } /* * the size of the spec event and placement of vendor_info_size * depends on supported algoriths @@ -1169,9 +1175,9 @@ static efi_status_t create_specid_event(struct udevice *dev, void *buffer, offsetof(struct tcg_efi_spec_id_event, digest_sizes) + spec_event->number_of_algorithms * sizeof(spec_event->digest_sizes[0]); /* no vendor info for us */ - memset(buffer + spec_event_size, 0, - sizeof(spec_event->vendor_info_size)); - spec_event_size += sizeof(spec_event->vendor_info_size); + memset(buffer + spec_event_size, 0, 1); + /* add a byte for vendor_info_size in the spec event */ + spec_event_size += 1; *event_size = spec_event_size; return EFI_SUCCESS; From 0ef476e68ef6391c2358894b5e6ba51083718883 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sat, 25 Sep 2021 02:49:18 +0200 Subject: [PATCH 49/51] arm: mvebu: turris_omnia: fix leaked mtd device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After getting MTD device via get_mtd_device_nm(), we need to put it with put_mtd_device(), otherwise we get Removing MTD device #0 (mx25l6405d) with use count 1 before booting kernel. Signed-off-by: Marek Behún Reviewed-by: Pali Rohár Tested-by: Pali Rohár Reviewed-by: Stefan Roese --- board/CZ.NIC/turris_omnia/turris_omnia.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index bac78af04e..a48e1f5c30 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -647,10 +647,13 @@ int ft_board_setup(void *blob, struct bd_info *bd) if (!fixup_mtd_partitions(blob, node, mtd)) goto fail; + put_mtd_device(mtd); return 0; fail: printf("Failed fixing SPI NOR partitions!\n"); + if (!IS_ERR_OR_NULL(mtd)) + put_mtd_device(mtd); return 0; } #endif From ccee8ea1dd90f0ccb31ed9662e064eaa814e6254 Mon Sep 17 00:00:00 2001 From: Denis Odintsov Date: Wed, 15 Sep 2021 15:45:31 +0200 Subject: [PATCH 50/51] phy: marvell: cp110: Support SATA invert polarity In commit b24bb99d cp110 configuration initially done in u-boot was removed and delegated to atf firmware as smc call. That commit didn't account for later introduced in d13b740c SATA invert polarity support. This patch adds support of passing SATA invert polarity flags to atf firmware during the smc call. Signed-off-by: Denis Odintsov Cc: Baruch Siach Cc: Rabeeh Khoury Cc: Stefan Roese Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_cp110.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 418318d12f..4fe2dfcdd1 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -36,6 +36,10 @@ DECLARE_GLOBAL_DATA_PTR; (COMPHY_CALLER_UBOOT | ((pcie_width) << 18) | \ ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds)) +/* Invert polarity are bits 1-0 of the mode */ +#define COMPHY_FW_SATA_FORMAT(mode, invert) \ + ((invert) | COMPHY_FW_MODE_FORMAT(mode)) + #define COMPHY_SATA_MODE 0x1 #define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */ #define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */ @@ -607,7 +611,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, break; case COMPHY_TYPE_SATA0: case COMPHY_TYPE_SATA1: - mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE); + mode = COMPHY_FW_SATA_FORMAT(COMPHY_SATA_MODE, + serdes_map[lane].invert); ret = comphy_sata_power_up(lane, hpipe_base_addr, comphy_base_addr, ptr_chip_cfg->cp_index, From 0b9bcf665cd98fe9db0956c894006b250a7d465f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 27 Sep 2021 09:34:20 -0400 Subject: [PATCH 51/51] Prepare v2021.10-rc5 Signed-off-by: Tom Rini --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3014788e14..732d702947 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2021 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc5 NAME = # *DOCUMENTATION*