Update Freescale 85xx boards to sys_eeprom.c
The new sys_eeprom.c supports both the old CCID EEPROM format and the new NXID format, and so it obsoletes board/freescale/common/cds_eeprom.c. Freescale 86xx boards already use sys_eeprom.c, so this patch migrates the remaining Freescale 85xx boards to use it as well. cds_eeprom.c is deleted. Signed-off-by: Timur Tabi <timur@freescale.com>
This commit is contained in:
committed by
Wolfgang Denk
parent
aab2bf0202
commit
e8d18541c6
@@ -44,7 +44,6 @@
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_VIA
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#define CONFIG_FSL_CDS_EEPROM
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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@@ -328,11 +327,17 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CFG_I2C_EEPROM_CCID
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#define CFG_ID_EEPROM
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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@@ -50,7 +50,6 @@
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_VIA
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#define CONFIG_FSL_CDS_EEPROM
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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@@ -352,11 +351,17 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CFG_I2C_EEPROM_CCID
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#define CFG_ID_EEPROM
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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@@ -43,7 +43,7 @@
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_VIA
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#define CONFIG_FSL_CDS_EEPROM
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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@@ -325,11 +325,17 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CFG_I2C_EEPROM_CCID
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#define CFG_ID_EEPROM
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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/*
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* General PCI
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* Addresses are mapped 1-1.
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