Update Freescale 85xx boards to sys_eeprom.c

The new sys_eeprom.c supports both the old CCID EEPROM format and the new NXID
format, and so it obsoletes board/freescale/common/cds_eeprom.c.  Freescale
86xx boards already use sys_eeprom.c, so this patch migrates the remaining
Freescale 85xx boards to use it as well.  cds_eeprom.c is deleted.

Signed-off-by: Timur Tabi <timur@freescale.com>
This commit is contained in:
Timur Tabi
2008-07-18 16:52:23 +02:00
committed by Wolfgang Denk
parent aab2bf0202
commit e8d18541c6
5 changed files with 22 additions and 67 deletions

View File

@@ -44,7 +44,6 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA
#define CONFIG_FSL_CDS_EEPROM
/*
* When initializing flash, if we cannot find the manufacturer ID,
@@ -328,11 +327,17 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CFG_I2C_EEPROM_CCID
#define CFG_ID_EEPROM
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_EEPROM_ADDR_LEN 2
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.

View File

@@ -50,7 +50,6 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA
#define CONFIG_FSL_CDS_EEPROM
/*
* When initializing flash, if we cannot find the manufacturer ID,
@@ -352,11 +351,17 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CFG_I2C_EEPROM_CCID
#define CFG_ID_EEPROM
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_EEPROM_ADDR_LEN 2
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.

View File

@@ -43,7 +43,7 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA
#define CONFIG_FSL_CDS_EEPROM
/*
* When initializing flash, if we cannot find the manufacturer ID,
@@ -325,11 +325,17 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CFG_I2C_EEPROM_CCID
#define CFG_ID_EEPROM
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_EEPROM_ADDR_LEN 2
/*
* General PCI
* Addresses are mapped 1-1.